diff --git a/components/driver/gpio.c b/components/driver/gpio.c index a7db2bde2..320533e8d 100644 --- a/components/driver/gpio.c +++ b/components/driver/gpio.c @@ -90,7 +90,6 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = { GPIO_PIN_REG_39 }; -#define IS_VALID_GPIO(gpio_num) ( (gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) static int is_valid_gpio(int gpio_num) { if(gpio_num >= GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[gpio_num] == 0) { @@ -102,8 +101,9 @@ static int is_valid_gpio(int gpio_num) esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(intr_type >= GPIO_INTR_MAX) { GPIO_ERROR("Unknown GPIO intr:%u\n",intr_type); return ESP_ERR_INVALID_ARG; @@ -114,8 +114,9 @@ esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type) esp_err_t gpio_intr_enable(gpio_num_t gpio_num) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(xPortGetCoreID() == 0) { GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr } else { @@ -126,16 +127,18 @@ esp_err_t gpio_intr_enable(gpio_num_t gpio_num) esp_err_t gpio_intr_disable(gpio_num_t gpio_num) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } GPIO.pin[gpio_num].int_ena = 0; //disable GPIO intr return ESP_OK; } static esp_err_t gpio_output_disable(gpio_num_t gpio_num) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(gpio_num < 32) { GPIO.enable_w1tc = (0x1 << gpio_num); } else { @@ -150,8 +153,9 @@ static esp_err_t gpio_output_enable(gpio_num_t gpio_num) GPIO_ERROR("io_num=%d can only be input\n",gpio_num); return ESP_ERR_INVALID_ARG; } - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(gpio_num < 32) { GPIO.enable_w1ts = (0x1 << gpio_num); } else { @@ -162,18 +166,21 @@ static esp_err_t gpio_output_enable(gpio_num_t gpio_num) esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level) { - if(!IS_VALID_GPIO(gpio_num)) + if(!GPIO_IS_VALID_GPIO(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(level) { - if(gpio_num < 32) + if(gpio_num < 32) { GPIO.out_w1ts = (1 << gpio_num); - else + } else { GPIO.out1_w1ts.data = (1 << (gpio_num - 32)); + } } else { - if(gpio_num < 32) + if(gpio_num < 32) { GPIO.out_w1tc = (1 << gpio_num); - else + } else { GPIO.out1_w1tc.data = (1 << (gpio_num - 32)); + } } return ESP_OK; } @@ -189,8 +196,9 @@ int gpio_get_level(gpio_num_t gpio_num) esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } esp_err_t ret = ESP_OK; switch(pull) { case GPIO_PULLUP_ONLY: @@ -219,8 +227,9 @@ esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull) esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(gpio_num >= 34 && (mode & (GPIO_MODE_DEF_OUTPUT))) { GPIO_ERROR("io_num=%d can only be input\n",gpio_num); return ESP_ERR_INVALID_ARG; @@ -290,7 +299,8 @@ esp_err_t gpio_config(gpio_config_t *pGPIOConfig) gpio_output_enable(io_num); } else { gpio_output_disable(io_num); - }GPIO_INFO("|"); + } + GPIO_INFO("|"); if(pGPIOConfig->pull_up_en) { GPIO_INFO("PU "); PIN_PULLUP_EN(io_reg); @@ -310,7 +320,7 @@ esp_err_t gpio_config(gpio_config_t *pGPIOConfig) } else { gpio_intr_disable(io_num); } - PIN_FUNC_SELECT(io_reg, GPIO_FUNC_SEL); /*function number 2 is GPIO_FUNC for each pin */ + PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); /*function number 2 is GPIO_FUNC for each pin */ } else if(bit_valid && (io_reg == 0)) { GPIO_WARNING("io_num=%d does not exist\n",io_num); } @@ -321,8 +331,9 @@ esp_err_t gpio_config(gpio_config_t *pGPIOConfig) esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * arg) { - if(fn == NULL) + if(fn == NULL) { return ESP_ERR_INVALID_ARG; + } ESP_INTR_DISABLE(gpio_intr_num); intr_matrix_set(xPortGetCoreID(), ETS_GPIO_INTR_SOURCE, gpio_intr_num); xt_set_interrupt_handler(gpio_intr_num, fn, arg); @@ -333,8 +344,9 @@ esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * ar /*only level interrupt can be used for wake-up function*/ esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } esp_err_t ret = ESP_OK; if((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) { GPIO.pin[gpio_num].int_type = intr_type; @@ -348,8 +360,9 @@ esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } GPIO.pin[gpio_num].wakeup_enable = 0; return ESP_OK; } diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h index d0ed5c9d7..862d4e592 100644 --- a/components/driver/include/driver/gpio.h +++ b/components/driver/include/driver/gpio.h @@ -65,8 +65,6 @@ extern "C" { #define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /* Pin 38 selected */ #define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /* Pin 39 selected */ -#define GPIO_FUNC_SEL 2 - #define GPIO_PIN_REG_0 PERIPHS_IO_MUX_GPIO0_U #define GPIO_PIN_REG_1 PERIPHS_IO_MUX_U0TXD_U #define GPIO_PIN_REG_2 PERIPHS_IO_MUX_GPIO2_U @@ -115,6 +113,8 @@ extern "C" { #define GPIO_PIN_COUNT 40 extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT]; +#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) //to decide whether it is a valid GPIO number +#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34)) //to decide whether it can be a valid GPIO number of output mode typedef enum { GPIO_NUM_0 = 0, diff --git a/components/driver/include/driver/ledc.h b/components/driver/include/driver/ledc.h index 728fad460..e8c03fd81 100644 --- a/components/driver/include/driver/ledc.h +++ b/components/driver/include/driver/ledc.h @@ -101,7 +101,7 @@ typedef struct ledc_channel_t_config { * When different channel ,select same time ,their freq_hz and duty_depth must be same * @return ESP_OK: success * ESP_ERR_INVALID_ARG: parameter error - * ESP_FAIL: spin_lock error + * ESP_FAIL: Can not find a proper pre-devider number base on the given frequency and the current duty_depth. * */ esp_err_t ledc_config(ledc_config_t* ledc_conf); @@ -118,7 +118,6 @@ esp_err_t ledc_config(ledc_config_t* ledc_conf); * * @return ESP_OK: success * ESP_ERR_INVALID_ARG: parameter error - * ESP_FAIL: spin_lock error * */ esp_err_t ledc_update(ledc_mode_t speed_mode, ledc_channel_t channel); @@ -134,7 +133,6 @@ esp_err_t ledc_update(ledc_mode_t speed_mode, ledc_channel_t channel); * * @return ESP_OK: success * ESP_ERR_INVALID_ARG: parameter error - * ESP_FAIL: spin_lock error */ esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idle_level); @@ -151,7 +149,7 @@ esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idl * * @return ESP_OK: success * ESP_ERR_INVALID_ARG: parameter error - * ESP_FAIL: spin_lock error + * ESP_FAIL: Can not find a proper pre-devider number base on the given frequency and the current duty_depth. */ esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t freq_hz); @@ -181,7 +179,6 @@ uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_channel_t channel); * * @return ESP_OK: success * ESP_ERR_INVALID_ARG: parameter error - * ESP_FAIL: spin_lock error */ esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty); @@ -193,10 +190,11 @@ esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t * @param[in] channel : LEDC channel(0-7) * * - * @return current LEDC duty + * @return -1: parameter error + * other value: current LEDC duty * */ -uint32_t ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel); +int ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel); /** * @brief LEDC set gradient @@ -219,7 +217,6 @@ uint32_t ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel); * * @return ESP_OK : success * ESP_ERR_INVALID_ARG : parameter error - * ESP_FAIL : spin_lock error */ esp_err_t ledc_set_fade(ledc_mode_t speed_mode, uint32_t channel, uint32_t duty, ledc_duty_direction_t gradule_direction, uint32_t step_num, uint32_t duty_cyle_num, uint32_t duty_scale); @@ -237,7 +234,6 @@ esp_err_t ledc_set_fade(ledc_mode_t speed_mode, uint32_t channel, uint32_t duty, * * @return ESP_OK : success ; * ESP_ERR_INVALID_ARG : fucntion ptr error. - * ESP_FAIL : spin_lock error */ esp_err_t ledc_isr_register(uint32_t ledc_intr_num, void (*fn)(void*), void * arg); diff --git a/components/driver/ledc.c b/components/driver/ledc.c index 7b7920f53..68e87c988 100644 --- a/components/driver/ledc.c +++ b/components/driver/ledc.c @@ -82,11 +82,11 @@ static int ledc_is_valid_mode(uint32_t mode) return 1; } - static esp_err_t ledc_timer_config(ledc_mode_t speed_mode, uint32_t timer_sel, uint32_t div_num, uint32_t timer_lim,ledc_timer_source_t clk) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return ESP_ERR_INVALID_ARG; + } portENTER_CRITICAL(&ledc_spinlock); LEDC.high_speed_timer[timer_sel].conf.div_num = div_num; LEDC.high_speed_timer[timer_sel].conf.tick_sel = clk; @@ -98,8 +98,9 @@ static esp_err_t ledc_timer_config(ledc_mode_t speed_mode, uint32_t timer_sel, u static esp_err_t ledc_duty_config(ledc_mode_t speed_mode, uint32_t channel_num, uint32_t hpoint_val, uint32_t duty_val, uint32_t duty_direction, uint32_t duty_num, uint32_t duty_cycle, uint32_t duty_scale) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return ESP_ERR_INVALID_ARG; + } portENTER_CRITICAL(&ledc_spinlock); LEDC.high_speed_channel[channel_num].hpoint.hpoint = hpoint_val; LEDC.high_speed_channel[channel_num].duty.duty = duty_val; @@ -113,8 +114,9 @@ static esp_err_t ledc_duty_config(ledc_mode_t speed_mode, uint32_t channel_num, static esp_err_t ledc_set_channel_timer(ledc_mode_t speed_mode, uint32_t channel, uint32_t timer_idx) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return ESP_ERR_INVALID_ARG; + } portENTER_CRITICAL(&ledc_spinlock); LEDC.high_speed_channel[channel].conf0.timer_sel = timer_idx; portEXIT_CRITICAL(&ledc_spinlock); @@ -123,8 +125,9 @@ static esp_err_t ledc_set_channel_timer(ledc_mode_t speed_mode, uint32_t channel static esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, uint32_t timer_sel) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return ESP_ERR_INVALID_ARG; + } portENTER_CRITICAL(&ledc_spinlock); LEDC.high_speed_timer[timer_sel].conf.rst = 1; LEDC.high_speed_timer[timer_sel].conf.rst = 0; @@ -133,8 +136,9 @@ static esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, uint32_t timer_sel) } static esp_err_t ledc_enable_intr_type(ledc_mode_t speed_mode, uint32_t channel, ledc_intr_type_t type) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return ESP_ERR_INVALID_ARG; + } uint32_t value; uint32_t intr_type = type; portENTER_CRITICAL(&ledc_spinlock); @@ -150,8 +154,9 @@ static esp_err_t ledc_enable_intr_type(ledc_mode_t speed_mode, uint32_t channel, esp_err_t ledc_isr_register(uint32_t ledc_intr_num, void (*fn)(void*), void * arg) { - if(fn == NULL) + if(fn == NULL) { return ESP_ERR_INVALID_ARG; + } portENTER_CRITICAL(&ledc_spinlock); ESP_INTR_DISABLE(ledc_intr_num); intr_matrix_set(xPortGetCoreID(), ETS_LEDC_INTR_SOURCE, ledc_intr_num); @@ -174,19 +179,17 @@ esp_err_t ledc_config(ledc_config_t* ledc_conf) uint32_t duty_depth = ledc_conf->duty_depth; uint32_t intr_type = ledc_conf->intr_type; uint32_t duty = ledc_conf->duty; - uint64_t div_param = 0; + uint32_t div_param = 0; uint32_t precision = 0; - if(!ledc_is_valid_channel(ledc_channel)) - return ESP_ERR_INVALID_ARG; - if(!ledc_is_valid_mode(speed_mode)) - return ESP_ERR_INVALID_ARG; - if(gpio_num >= GPIO_NUM_34 || gpio_num == 20 || gpio_num == 24 || gpio_num == 28 || gpio_num == 29 || gpio_num == 30 - || gpio_num == 31) { - LEDC_ERROR("GPIO number error: IO%d\n ", gpio_num); + int timer_clk_src = 0; + if(!ledc_is_valid_channel(ledc_channel)) { return ESP_ERR_INVALID_ARG; } - if(gpio_num >= GPIO_PIN_COUNT || 0 == GPIO_PIN_MUX_REG[gpio_num]) { - LEDC_ERROR("io_num=%d does not exist\n", gpio_num); + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)) { + LEDC_ERROR("GPIO number error: IO%d\n ", gpio_num); return ESP_ERR_INVALID_ARG; } if(freq_hz == 0 || duty_depth == 0 || duty_depth > LEDC_DUTY_DEPTH_15_BIT) { @@ -200,32 +203,34 @@ esp_err_t ledc_config(ledc_config_t* ledc_conf) portENTER_CRITICAL(&ledc_spinlock); esp_err_t ret = ESP_OK; /*gpio matrix ledc pwm signal*/ - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], 2); + PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); gpio_matrix_out(gpio_num, LEDC_HS_SIG_OUT0_IDX + ledc_channel, 0, 0); /*configure ledc param*/ /*calculate the div_param and select which base clock and first we will select the apb_clk */ precision = (0x1 << duty_depth); //2**depth - div_param = (uint64_t) LEDC_APB_CLK_HZ * 256 / freq_hz / precision; //8bit fragment + div_param = ((uint64_t) LEDC_APB_CLK_HZ << 8) / freq_hz / precision; //8bit fragment /*Fail ,because the div num overflow or too small*/ - if(div_param <= 256 || div_param > LEDC_DIV_NUM_HSTIMER0) { //REF TICK + if(div_param <= 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) { //REF TICK /*Selet the reference tick*/ - div_param = (uint64_t) LEDC_REF_CLK_HZ * 256 / freq_hz / precision; + div_param = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision; if(div_param <= 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) { LEDC_ERROR("div param err,div_param=%u\n", div_param); ret = ESP_FAIL; } - ledc_timer_config(speed_mode, timer_select, div_param, duty_depth, LEDC_REF_TICK); + timer_clk_src = LEDC_REF_TICK; + ledc_timer_config(speed_mode, timer_select, div_param, duty_depth, timer_clk_src); ledc_set_channel_timer(speed_mode, ledc_channel, timer_select); } else { //APB TICK - ledc_timer_config(speed_mode, timer_select, div_param, duty_depth, LEDC_APB_CLK); + timer_clk_src = LEDC_APB_CLK; + ledc_timer_config(speed_mode, timer_select, div_param, duty_depth, timer_clk_src); ledc_set_channel_timer(speed_mode, ledc_channel, timer_select); } ledc_timer_rst(speed_mode, timer_select); ledc_set_duty(speed_mode, ledc_channel, duty); ledc_enable_intr_type(speed_mode, ledc_channel, intr_type); LEDC_INFO("LEDC_PWM CHANNEL %1u|GPIO %02u|FreHz %05u|Duty %04u|Depth %04u|Time %01u|SourceClk %01u|Divparam %u\n", - ledc_channel, gpio_num, freq_hz, duty, duty_depth, timer_select, timer_source_clk_flag, div_param + ledc_channel, gpio_num, freq_hz, duty, duty_depth, timer_select, timer_clk_src, div_param ); ledc_update(speed_mode, ledc_channel); portEXIT_CRITICAL(&ledc_spinlock); @@ -234,10 +239,12 @@ esp_err_t ledc_config(ledc_config_t* ledc_conf) esp_err_t ledc_update(ledc_mode_t speed_mode, ledc_channel_t channel) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return ESP_ERR_INVALID_ARG; - if(!ledc_is_valid_channel(channel)) + } + if(!ledc_is_valid_channel(channel)) { return ESP_ERR_INVALID_ARG; + } portENTER_CRITICAL(&ledc_spinlock); LEDC.high_speed_channel[channel].conf0.sig_out_en = 1; LEDC.high_speed_channel[channel].conf1.duty_start = 1; @@ -247,10 +254,12 @@ esp_err_t ledc_update(ledc_mode_t speed_mode, ledc_channel_t channel) esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idle_level) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return ESP_ERR_INVALID_ARG; - if(!ledc_is_valid_channel(channel)) + } + if(!ledc_is_valid_channel(channel)) { return ESP_ERR_INVALID_ARG; + } portENTER_CRITICAL(&ledc_spinlock); LEDC.high_speed_channel[channel].conf0.idle_lv = idle_level; LEDC.high_speed_channel[channel].conf0.sig_out_en = 0; @@ -261,15 +270,17 @@ esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idl esp_err_t ledc_set_fade(ledc_mode_t speed_mode, uint32_t channel, uint32_t duty, ledc_duty_direction_t fade_direction, uint32_t step_num, uint32_t duty_cyle_num, uint32_t duty_scale) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return ESP_ERR_INVALID_ARG; - if(!ledc_is_valid_channel(channel)) + } + if(!ledc_is_valid_channel(channel)) { return ESP_ERR_INVALID_ARG; + } if(fade_direction > LEDC_DUTY_DIR_INCREASE) { LEDC_ERROR("Duty direction err\n"); return ESP_ERR_INVALID_ARG; } - if(step_num > 0X3FF || duty_cyle_num > 0X3FF || duty_scale > 0X3FF) { + if(step_num > LEDC_DUTY_NUM_HSCH0_V || duty_cyle_num > LEDC_DUTY_CYCLE_HSCH0_V || duty_scale > LEDC_DUTY_SCALE_HSCH0_V) { LEDC_ERROR("step_num=%u duty_cyle_num=%u duty_scale=%u\n", step_num, duty_cyle_num, duty_scale); return ESP_ERR_INVALID_ARG; } @@ -289,10 +300,12 @@ esp_err_t ledc_set_fade(ledc_mode_t speed_mode, uint32_t channel, uint32_t duty, esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return ESP_ERR_INVALID_ARG; - if(!ledc_is_valid_channel(channel)) + } + if(!ledc_is_valid_channel(channel)) { return ESP_ERR_INVALID_ARG; + } portENTER_CRITICAL(&ledc_spinlock); ledc_duty_config(speed_mode, channel, //uint32_t chan_num, @@ -307,21 +320,23 @@ esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t return ESP_OK; } -uint32_t ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel) +int ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel) { - if(!ledc_is_valid_mode(speed_mode)) - return ESP_ERR_INVALID_ARG; - uint32_t duty = 0; - duty = (LEDC.high_speed_channel[channel].duty_rd.duty_read >> 4); + if(!ledc_is_valid_mode(speed_mode)) { + return -1; + } + uint32_t duty = (LEDC.high_speed_channel[channel].duty_rd.duty_read >> 4); return duty; } esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t freq_hz) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return ESP_ERR_INVALID_ARG; - if(!ledc_is_valid_channel(channel)) + } + if(!ledc_is_valid_channel(channel)) { return ESP_ERR_INVALID_ARG; + } portENTER_CRITICAL(&ledc_spinlock); esp_err_t ret = ESP_OK; uint32_t div_num = 0; @@ -332,9 +347,9 @@ esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t uint32_t timer_source_clk = LEDC.high_speed_timer[timer_select].conf.tick_sel; uint32_t precision = (0x1 << duty_depth); if(timer_source_clk == LEDC_APB_CLK) { - div_num = (uint64_t) LEDC_APB_CLK_HZ * 256 / freq_hz / precision; + div_num = ((uint64_t) LEDC_APB_CLK_HZ << 8) / freq_hz / precision; } else { - div_num = (uint64_t) LEDC_REF_CLK_HZ * 256 / freq_hz / precision; + div_num = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision; } if(div_num <= 256 || div_num > LEDC_DIV_NUM_HSTIMER0) { LEDC_ERROR("channel %u,div param err,div_param=%u\n", channel, div_num); @@ -347,10 +362,12 @@ esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_channel_t channel) { - if(!ledc_is_valid_mode(speed_mode)) + if(!ledc_is_valid_mode(speed_mode)) { return 0; - if(!ledc_is_valid_channel(channel)) - return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_channel(channel)) { + return 0; + } portENTER_CRITICAL(&ledc_spinlock); uint32_t freq = 0; uint32_t timer_select = LEDC.high_speed_channel[channel].conf0.timer_sel; @@ -359,9 +376,9 @@ uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_channel_t channel) uint32_t div_num = LEDC.high_speed_timer[timer_select].conf.div_num; uint32_t precision = (0x1 << duty_depth); if(timer_source_clk == LEDC_APB_CLK) { - freq = ((uint64_t) LEDC_APB_CLK_HZ) * 256 / precision / div_num; + freq = ((uint64_t) LEDC_APB_CLK_HZ << 8) / precision / div_num; } else { - freq = ((uint64_t) LEDC_REF_CLK_HZ) * 256 / precision / div_num; + freq = ((uint64_t) LEDC_REF_CLK_HZ << 8) / precision / div_num; } portEXIT_CRITICAL(&ledc_spinlock); return freq; diff --git a/components/esp32/include/soc/io_mux_reg.h b/components/esp32/include/soc/io_mux_reg.h index f6ec4e520..208a60703 100644 --- a/components/esp32/include/soc/io_mux_reg.h +++ b/components/esp32/include/soc/io_mux_reg.h @@ -40,6 +40,8 @@ #define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) #define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_FUNC_GPIO 2 + #define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00) #define CLK_OUT3 0xf #define CLK_OUT3_S 8 @@ -48,84 +50,17 @@ #define CLK_OUT1 0xf #define CLK_OUT1_S 0 -#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04) -#define FUNC_GPIO36_GPIO36 2 -#define FUNC_GPIO36_GPIO36_0 0 +#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44) +#define FUNC_GPIO0_EMAC_TX_CLK 5 +#define FUNC_GPIO0_GPIO0 2 +#define FUNC_GPIO0_CLK_OUT1 1 +#define FUNC_GPIO0_GPIO0_0 0 -#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08) -#define FUNC_GPIO37_GPIO37 2 -#define FUNC_GPIO37_GPIO37_0 0 - -#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c) -#define FUNC_GPIO38_GPIO38 2 -#define FUNC_GPIO38_GPIO38_0 0 - -#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10) -#define FUNC_GPIO39_GPIO39 2 -#define FUNC_GPIO39_GPIO39_0 0 - -#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14) -#define FUNC_GPIO34_GPIO34 2 -#define FUNC_GPIO34_GPIO34_0 0 - -#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18) -#define FUNC_GPIO35_GPIO35 2 -#define FUNC_GPIO35_GPIO35_0 0 - -#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c) -#define FUNC_GPIO32_GPIO32 2 -#define FUNC_GPIO32_GPIO32_0 0 - -#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20) -#define FUNC_GPIO33_GPIO33 2 -#define FUNC_GPIO33_GPIO33_0 0 - -#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24) -#define FUNC_GPIO25_EMAC_RXD0 5 -#define FUNC_GPIO25_GPIO25 2 -#define FUNC_GPIO25_GPIO25_0 0 - -#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28) -#define FUNC_GPIO26_EMAC_RXD1 5 -#define FUNC_GPIO26_GPIO26 2 -#define FUNC_GPIO26_GPIO26_0 0 - -#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c) -#define FUNC_GPIO27_EMAC_RX_DV 5 -#define FUNC_GPIO27_GPIO27 2 -#define FUNC_GPIO27_GPIO27_0 0 - -#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30) -#define FUNC_MTMS_EMAC_TXD2 5 -#define FUNC_MTMS_SD_CLK 4 -#define FUNC_MTMS_HS2_CLk 3 -#define FUNC_MTMS_GPIO14 2 -#define FUNC_MTMS_HSPICLK 1 -#define FUNC_MTMS_MTMS 0 - -#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34) -#define FUNC_MTDI_EMAC_TXD3 5 -#define FUNC_MTDI_SD_DATA2 4 -#define FUNC_MTDI_HS2_DATA2 3 -#define FUNC_MTDI_GPIO12 2 -#define FUNC_MTDI_HSPIQ 1 -#define FUNC_MTDI_MTDI 0 - -#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38) -#define FUNC_MTCK_EMAC_RX_ER 5 -#define FUNC_MTCK_SD_DATA3 4 -#define FUNC_MTCK_HS2_DATA3 3 -#define FUNC_MTCK_GPIO13 2 -#define FUNC_MTCK_HSPID 1 -#define FUNC_MTCK_MTCK 0 - -#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c) -#define FUNC_MTDO_EMAC_RXD3 5 -#define FUNC_MTDO_SD_CMD 4 -#define FUNC_MTDO_HS2_CMD 3 -#define FUNC_MTDO_GPIO15 2 -#define FUNC_MTDO_HSPICS0 1 -#define FUNC_MTDO_MTDO 0 +#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88) +#define FUNC_U0TXD_EMAC_RXD2 3 +#define FUNC_U0TXD_GPIO1 2 +#define FUNC_U0TXD_CLK_OUT3 1 +#define FUNC_U0TXD_U0TXD 0 #define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40) #define FUNC_GPIO2_SD_DATA0 4 @@ -134,11 +69,10 @@ #define FUNC_GPIO2_HSPIWP 1 #define FUNC_GPIO2_GPIO2_0 0 -#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44) -#define FUNC_GPIO0_EMAC_TX_CLK 5 -#define FUNC_GPIO0_GPIO0 2 -#define FUNC_GPIO0_CLK_OUT1 1 -#define FUNC_GPIO0_GPIO0_0 0 +#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84) +#define FUNC_U0RXD_GPIO3 2 +#define FUNC_U0RXD_CLK_OUT2 1 +#define FUNC_U0RXD_U0RXD 0 #define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48) #define FUNC_GPIO4_EMAC_TX_ER 5 @@ -148,40 +82,12 @@ #define FUNC_GPIO4_HSPIHD 1 #define FUNC_GPIO4_GPIO4_0 0 -#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c) -#define FUNC_GPIO16_EMAC_CLK_OUT 5 -#define FUNC_GPIO16_U2RXD 4 -#define FUNC_GPIO16_HS1_DATA4 3 -#define FUNC_GPIO16_GPIO16 2 -#define FUNC_GPIO16_GPIO16_0 0 - -#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50) -#define FUNC_GPIO17_EMAC_CLK_OUT_180 5 -#define FUNC_GPIO17_U2TXD 4 -#define FUNC_GPIO17_HS1_DATA5 3 -#define FUNC_GPIO17_GPIO17 2 -#define FUNC_GPIO17_GPIO17_0 0 - -#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54) -#define FUNC_SD_DATA2_U1RXD 4 -#define FUNC_SD_DATA2_HS1_DATA2 3 -#define FUNC_SD_DATA2_GPIO9 2 -#define FUNC_SD_DATA2_SPIHD 1 -#define FUNC_SD_DATA2_SD_DATA2 0 - -#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58) -#define FUNC_SD_DATA3_U1TXD 4 -#define FUNC_SD_DATA3_HS1_DATA3 3 -#define FUNC_SD_DATA3_GPIO10 2 -#define FUNC_SD_DATA3_SPIWP 1 -#define FUNC_SD_DATA3_SD_DATA3 0 - -#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c) -#define FUNC_SD_CMD_U1RTS 4 -#define FUNC_SD_CMD_HS1_CMD 3 -#define FUNC_SD_CMD_GPIO11 2 -#define FUNC_SD_CMD_SPICS0 1 -#define FUNC_SD_CMD_SD_CMD 0 +#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c) +#define FUNC_GPIO5_EMAC_RX_CLK 5 +#define FUNC_GPIO5_HS1_DATA6 3 +#define FUNC_GPIO5_GPIO5 2 +#define FUNC_GPIO5_VSPICS0 1 +#define FUNC_GPIO5_GPIO5_0 0 #define PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60) #define FUNC_SD_CLK_U1CTS 4 @@ -204,12 +110,72 @@ #define FUNC_SD_DATA1_SPID 1 #define FUNC_SD_DATA1_SD_DATA1 0 -#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c) -#define FUNC_GPIO5_EMAC_RX_CLK 5 -#define FUNC_GPIO5_HS1_DATA6 3 -#define FUNC_GPIO5_GPIO5 2 -#define FUNC_GPIO5_VSPICS0 1 -#define FUNC_GPIO5_GPIO5_0 0 +#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54) +#define FUNC_SD_DATA2_U1RXD 4 +#define FUNC_SD_DATA2_HS1_DATA2 3 +#define FUNC_SD_DATA2_GPIO9 2 +#define FUNC_SD_DATA2_SPIHD 1 +#define FUNC_SD_DATA2_SD_DATA2 0 + +#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58) +#define FUNC_SD_DATA3_U1TXD 4 +#define FUNC_SD_DATA3_HS1_DATA3 3 +#define FUNC_SD_DATA3_GPIO10 2 +#define FUNC_SD_DATA3_SPIWP 1 +#define FUNC_SD_DATA3_SD_DATA3 0 + +#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c) +#define FUNC_SD_CMD_U1RTS 4 +#define FUNC_SD_CMD_HS1_CMD 3 +#define FUNC_SD_CMD_GPIO11 2 +#define FUNC_SD_CMD_SPICS0 1 +#define FUNC_SD_CMD_SD_CMD 0 + +#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34) +#define FUNC_MTDI_EMAC_TXD3 5 +#define FUNC_MTDI_SD_DATA2 4 +#define FUNC_MTDI_HS2_DATA2 3 +#define FUNC_MTDI_GPIO12 2 +#define FUNC_MTDI_HSPIQ 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38) +#define FUNC_MTCK_EMAC_RX_ER 5 +#define FUNC_MTCK_SD_DATA3 4 +#define FUNC_MTCK_HS2_DATA3 3 +#define FUNC_MTCK_GPIO13 2 +#define FUNC_MTCK_HSPID 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30) +#define FUNC_MTMS_EMAC_TXD2 5 +#define FUNC_MTMS_SD_CLK 4 +#define FUNC_MTMS_HS2_CLk 3 +#define FUNC_MTMS_GPIO14 2 +#define FUNC_MTMS_HSPICLK 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c) +#define FUNC_MTDO_EMAC_RXD3 5 +#define FUNC_MTDO_SD_CMD 4 +#define FUNC_MTDO_HS2_CMD 3 +#define FUNC_MTDO_GPIO15 2 +#define FUNC_MTDO_HSPICS0 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c) +#define FUNC_GPIO16_EMAC_CLK_OUT 5 +#define FUNC_GPIO16_U2RXD 4 +#define FUNC_GPIO16_HS1_DATA4 3 +#define FUNC_GPIO16_GPIO16 2 +#define FUNC_GPIO16_GPIO16_0 0 + +#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50) +#define FUNC_GPIO17_EMAC_CLK_OUT_180 5 +#define FUNC_GPIO17_U2TXD 4 +#define FUNC_GPIO17_HS1_DATA5 3 +#define FUNC_GPIO17_GPIO17 2 +#define FUNC_GPIO17_GPIO17_0 0 #define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70) #define FUNC_GPIO18_HS1_DATA7 3 @@ -241,17 +207,6 @@ #define FUNC_GPIO22_VSPIWP 1 #define FUNC_GPIO22_GPIO22_0 0 -#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84) -#define FUNC_U0RXD_GPIO3 2 -#define FUNC_U0RXD_CLK_OUT2 1 -#define FUNC_U0RXD_U0RXD 0 - -#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88) -#define FUNC_U0TXD_EMAC_RXD2 3 -#define FUNC_U0TXD_GPIO1 2 -#define FUNC_U0TXD_CLK_OUT3 1 -#define FUNC_U0TXD_U0TXD 0 - #define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c) #define FUNC_GPIO23_HS1_STROBE 3 #define FUNC_GPIO23_GPIO23 2 @@ -262,4 +217,51 @@ #define FUNC_GPIO24_GPIO24 2 #define FUNC_GPIO24_GPIO24_0 0 +#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24) +#define FUNC_GPIO25_EMAC_RXD0 5 +#define FUNC_GPIO25_GPIO25 2 +#define FUNC_GPIO25_GPIO25_0 0 + +#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28) +#define FUNC_GPIO26_EMAC_RXD1 5 +#define FUNC_GPIO26_GPIO26 2 +#define FUNC_GPIO26_GPIO26_0 0 + +#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c) +#define FUNC_GPIO27_EMAC_RX_DV 5 +#define FUNC_GPIO27_GPIO27 2 +#define FUNC_GPIO27_GPIO27_0 0 + +#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c) +#define FUNC_GPIO32_GPIO32 2 +#define FUNC_GPIO32_GPIO32_0 0 + +#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20) +#define FUNC_GPIO33_GPIO33 2 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14) +#define FUNC_GPIO34_GPIO34 2 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18) +#define FUNC_GPIO35_GPIO35 2 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04) +#define FUNC_GPIO36_GPIO36 2 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08) +#define FUNC_GPIO37_GPIO37 2 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c) +#define FUNC_GPIO38_GPIO38 2 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10) +#define FUNC_GPIO39_GPIO39 2 +#define FUNC_GPIO39_GPIO39_0 0 + #endif /* _SOC_IO_MUX_REG_H_ */