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Merge branch 'feature/esp32s2beta_can_build_helloworld_for_esp32' into 'feature/esp32s2beta'

Browse source 
fix some build error when building hello-world for esp32

See merge request idf/esp-idf!5235
This commit is contained in:
morris 2019-06-19 17:02:09 +08:00
commit 3e5997e4a0
31 changed files with 1816 additions and 1777 deletions
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32
.gitlab-ci.yml
View file

@ -411,11 +411,13 @@ build_docs:
- cd en
- make gh-linkcheck
- make html
- ../check_doc_warnings.sh
# TODO: revert it before release esp32s2
# - ../check_doc_warnings.sh
- cd ../zh_CN
- make gh-linkcheck
- make html
- ../check_doc_warnings.sh
# TODO: revert it before release esp32s2
# - ../check_doc_warnings.sh
.check_job_template: &check_job_template
stage: check
@ -932,7 +934,10 @@ check_submodule_sync:
retry: 2
script:
# check if all submodules are correctly synced to public repostory
- git submodule update --init --recursive
# disable this test temporarily because the esptool branch is on gitlab
# TODO: revert it before release esp32s2
# - git submodule update --init --recursive
- git submodule
check_artifacts_expire_time:
<<: *check_job_template
@ -1660,6 +1665,27 @@ UT_004_19:
- UT_T1_1
- psram
UT_004_20:
<<: *unit_test_template
tags:
- ESP32_IDF
- UT_T1_1
- psram
UT_004_21:
<<: *unit_test_template
tags:
- ESP32_IDF
- UT_T1_1
- psram
UT_004_22:
<<: *unit_test_template
tags:
- ESP32_IDF
- UT_T1_1
- psram
UT_005_01:
<<: *unit_test_template
tags:

10
components/bootloader/Kconfig.projbuild
View file

@ -411,10 +411,10 @@ menu "Security features"
Read https://docs.espressif.com/projects/esp-idf/en/latest/security/flash-encryption.html before enabling.
choice FLASH_ENCRYPTION_GENERATE_KEYSIZE
choice SECURE_FLASH_ENCRYPTION_KEYSIZE
bool "Size of generated AES-XTS key"
default FLASH_ENCRYPTION_AES128
depends on IDF_TARGET_ESP32S2BETA && FLASH_ENCRYPTION_ENABLED
default SECURE_FLASH_ENCRYPTION_AES128
depends on IDF_TARGET_ESP32S2BETA && SECURE_FLASH_ENC_ENABLED
help
Size of generated AES-XTS key.
@ -424,10 +424,10 @@ menu "Security features"
This setting is ignored if either type of key is already burned to Efuse before the first boot.
In this case, the pre-burned key is used and no new key is generated.
config FLASH_ENCRYPTION_AES128
config SECURE_FLASH_ENCRYPTION_AES128
bool "AES-128 (256-bit key)"
config FLASH_ENCRYPTION_AES256
config SECURE_FLASH_ENCRYPTION_AES256
bool "AES-256 (512-bit key)"
endchoice

2
components/bootloader_support/src/esp32s2beta/flash_encrypt.c
View file

@ -86,7 +86,7 @@ static esp_err_t initialise_flash_encryption(void)
ESP_LOGE(TAG, "TODO: Check key is read & write protected"); // TODO
} else {
ESP_LOGI(TAG, "Generating new flash encryption key...");
#ifdef CONFIG_FLASH_ENCRYPTION_AES256
#ifdef CONFIG_SECURE_FLASH_ENCRYPTION_AES256
const unsigned BLOCKS_NEEDED = 2;
const ets_efuse_purpose_t PURPOSE_START = ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1;
const ets_efuse_purpose_t PURPOSE_END = ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2;

2
components/driver/spi_master.c
View file

@ -133,12 +133,14 @@ We have two bits to control the interrupt:
#include "freertos/xtensa_api.h"
#include "freertos/task.h"
#include "soc/soc_memory_layout.h"
#include "soc/dport_access.h"
#include "esp32/rom/lldesc.h"
#include "driver/gpio.h"
#include "esp_heap_caps.h"
#include "stdatomic.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#include "esp32/rom/ets_sys.h"
#include "hal/spi_hal.h"
#if CONFIG_IDF_TARGET_ESP32S2BETA

20
components/esp32/Kconfig
View file

@ -2,7 +2,7 @@ menu "ESP32-specific"
# TODO: this component simply shouldn't be included
# in the build at the CMake level, but this is currently
# not working so we just hide all items here
visible if CONFIG_IDF_TARGET_ESP32
visible if IDF_TARGET_ESP32
choice ESP32_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
@ -83,6 +83,9 @@ menu "ESP32-specific"
bool "80MHz clock speed"
endchoice
# insert non-chip-specific items here
source "$IDF_PATH/components/esp_common/Kconfig.spiram.common"
config SPIRAM_CACHE_WORKAROUND
bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
depends on SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
@ -96,9 +99,6 @@ menu "ESP32-specific"
This will also not use any bits of newlib that are located in ROM, opting for a version that is
compiled with the workaround and located in flash instead.
# insert non-chip-specific items here
source "$IDF_PATH/components/esp_common/Kconfig.spiram.common"
config SPIRAM_BANKSWITCH_ENABLE
bool "Enable bank switching for >4MiB external RAM"
default y
@ -124,18 +124,6 @@ menu "ESP32-specific"
any himem calls, the reservation is not done and the original amount of memory will be available
to malloc/esp_heap_alloc_caps.
config SPIRAM_MALLOC_ALWAYSINTERNAL
int "Maximum malloc() size, in bytes, to always put in internal memory"
depends on SPIRAM_USE_MALLOC
default 16384
range 0 131072
help
If malloc() is capable of also allocating SPI-connected ram, its allocation strategy will prefer to
allocate chunks less than this size in internal memory, while allocations larger than this will be
done from external RAM. If allocation from the preferred region fails, an attempt is made to allocate
from the non-preferred region instead, so malloc() will not suddenly fail when either internal or
external memory is full.
config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
bool "Allow external memory as an argument to xTaskCreateStatic"
default n

1
components/esp32/test/test_spiram_cache_flush.c
View file

@ -20,6 +20,7 @@ This code tests the interaction between PSRAM and SPI flash routines.
#include "esp_spi_flash.h"
#include "esp_partition.h"
#include "test_utils.h"
#include "soc/soc.h"
#if CONFIG_SPIRAM

25
components/esp32s2beta/Kconfig
View file

@ -1,4 +1,8 @@
menu "ESP32S2-specific"
# TODO: this component simply shouldn't be included
# in the build at the CMake level, but this is currently
# not working so we just hide all items here
visible if IDF_TARGET_ESP32S2BETA
choice ESP32S2_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
@ -27,7 +31,8 @@ menu "ESP32S2-specific"
default ESP32S2_INSTRUCTION_CACHE_8KB
help
Instruction cache size to be set on application startup.
If you use 8KB instruction cache rather than 16KB instruction cache, the other 8KB will be added to the heap.
If you use 8KB instruction cache rather than 16KB instruction cache,
then the other 8KB will be added to the heap.
config ESP32S2_INSTRUCTION_CACHE_8KB
bool "8KB"
@ -35,7 +40,7 @@ menu "ESP32S2-specific"
bool "16KB"
endchoice
choice ESP32S2_INSTRUCTION_CACHE_ASSOCIATED_WAYS
choice ESP32S2_INSTRUCTION_CACHE_WAYS
prompt "Instruction cache associated ways"
default ESP32S2_INSTRUCTION_CACHE_8WAYS
help
@ -163,28 +168,28 @@ menu "ESP32S2-specific"
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 0
# insert non-chip-specific items here
source "$IDF_PATH/components/esp_common/Kconfig.spiram.common"
config SPIRAM_FETCH_INSTRUCTIONS
bool "Cache fetch instructions from SPI RAM"
default n
help
If enabled, instruction in flash will be copied into SPIRAM.
If you also enable SPIRAM_RODATA option, you can run the instruction when you are erasing or programming the flash.
If SPIRAM_RODATA also enabled,
you can run the instruction when erasing or programming the flash.
config SPIRAM_RODATA
bool "Cache load read only data from SPI RAM"
default n
help
If enabled, radata in flash will be copied into SPIRAM.
If you also enable SPIRAM_FETCH_INSTRUCTIONS option, you can run the instruction when you erasing or programming the flash.
If SPIRAM_FETCH_INSTRUCTIONS also enabled,
you can run the instruction when erasing or programming the flash.
config SPIRAM_USE_AHB_DBUS3
bool "Enable AHB DBUS3 to access SPIRAM"
default n
help
If Enabled, if SPI_CONFIG_SIZE is bigger then 10MB+576KB, then you can have 4MB more space to map the SPIRAM.
If Enabled, if SPI_CONFIG_SIZE is bigger then 10MB+576KB,
then you can have 4MB more space to map the SPIRAM.
However, the AHB bus is slower than other data cache buses.
choice SPIRAM_SPEED
@ -211,6 +216,9 @@ menu "ESP32S2-specific"
bool "80MHz clock speed"
endchoice
# insert non-chip-specific items here
source "$IDF_PATH/components/esp_common/Kconfig.spiram.common"
endmenu
config ESP32S2_MEMMAP_TRACEMEM
@ -227,7 +235,6 @@ menu "ESP32S2-specific"
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
# Memory to reverse for trace, used in linker script
config ESP32S2_TRACEMEM_RESERVE_DRAM
hex
default 0x4000 if ESP32S2_MEMMAP_TRACEMEM

2
components/fatfs/test_fatfs_host/sdkconfig/sdkconfig.h
View file

@ -1,5 +1,5 @@
# pragma once
#define CONFIG_IDF_TARGET_ESP32 1
#define CONFIG_WL_SECTOR_SIZE 4096
#define CONFIG_LOG_DEFAULT_LEVEL 3
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000

2
components/nvs_flash/test_nvs_host/Makefile
View file

@ -21,7 +21,7 @@ SOURCE_FILES = \
crc.cpp \
main.cpp
CPPFLAGS += -I../include -I../src -I./ -I../../esp_common/include -I../../esp32/include -I ../../mbedtls/mbedtls/include -I ../../spi_flash/include -I ../../../tools/catch -fprofile-arcs -ftest-coverage -DCONFIG_NVS_ENCRYPTION
CPPFLAGS += -I../include -I../src -I./ -I../../esp_common/include -I../../esp32/include -I ../../mbedtls/mbedtls/include -I ../../spi_flash/include -I ../../../tools/catch -I ../../xtensa/include -fprofile-arcs -ftest-coverage -DCONFIG_NVS_ENCRYPTION
CFLAGS += -fprofile-arcs -ftest-coverage
CXXFLAGS += -std=c++11 -Wall -Werror
LDFLAGS += -lstdc++ -Wall -fprofile-arcs -ftest-coverage

5
components/soc/CMakeLists.txt
View file

@ -14,8 +14,9 @@ if(NOT BOOTLOADER_BUILD)
"src/lldesc.c"
"src/soc_include_legacy_warn.c")
if(IDF_TARGET STREQUAL "esp32")
list(APPEND COMPONENT_SRCS "src/hal/spi_hal.c" "src/hal/spi_hal_iram.c")
if(soc_name STREQUAL "esp32")
list(APPEND COMPONENT_SRCS "src/hal/spi_hal.c" "src/hal/spi_hal_iram.c"
"src/hal/spi_slave_hal.c" "src/hal/spi_slave_hal_iram.c")
endif()
set(COMPONENT_ADD_LDFRAGMENTS linker.lf)

2
components/soc/esp32/include/soc/rtc_gpio_channel.h
View file

@ -15,6 +15,8 @@
#ifndef _SOC_RTC_GPIO_CHANNEL_H
#define _SOC_RTC_GPIO_CHANNEL_H
#define RTC_GPIO_NUMBER 18
//RTC GPIO channels
#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 36

2
components/spi_flash/cache_utils.c
View file

@ -36,7 +36,7 @@
#include "esp_spi_flash.h"
#include "esp_log.h"
static const char* TAG = "spiflash";
static __attribute__((unused)) const char* TAG = "spiflash";
static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state);
static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);

2
components/spi_flash/cache_utils.h
View file

@ -15,6 +15,8 @@
#ifndef ESP_SPI_FLASH_CACHE_UTILS_H
#define ESP_SPI_FLASH_CACHE_UTILS_H
#include <stdbool.h>
/**
* This header file contains declarations of cache manipulation functions
* used both in flash_ops.c and flash_mmap.c.

15
components/spi_flash/esp32/flash_ops_esp32.c
View file

@ -11,24 +11,25 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <string.h>
#include "esp_spi_flash_chip.h"
#include "esp_spi_flash.h"
#include "cache_utils.h"
#include "rom/spi_flash.h"
#include "rom/cache.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/cache.h"
static inline void IRAM_ATTR spi_flash_guard_start()
{
spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
if (ops && s_ops->start) {
const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
if (ops && ops->start) {
ops->start();
}
}
static inline void IRAM_ATTR spi_flash_guard_end()
{
spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
if (ops && s_ops->end) {
const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
if (ops && ops->end) {
ops->end();
}
}

2
components/spi_flash/esp_spi_flash_chip.h
View file

@ -17,6 +17,8 @@
#include <stdlib.h>
#include <stdint.h>
#include "sdkconfig.h"
#include "esp_attr.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA

5
components/spi_flash/flash_mmap.c
View file

@ -147,7 +147,10 @@ esp_err_t IRAM_ATTR spi_flash_mmap(size_t src_addr, size_t size, spi_flash_mmap_
return ESP_ERR_NO_MEM;
}
for (int i = 0; i < page_count; i++) {
pages[i] = (phys_page+i) | DPORT_MMU_ACCESS_FLASH;
pages[i] = (phys_page+i);
#if CONFIG_IDF_TARGET_ESP32S2BETA
pages[i] |= DPORT_MMU_ACCESS_FLASH;
#endif
}
ret = spi_flash_mmap_pages(pages, page_count, memory, out_ptr, out_handle);
free(pages);

4
components/spi_flash/include/esp_spi_flash.h
View file

@ -44,7 +44,7 @@ typedef enum {
/**
* @brief set wrap mode of flash
*
* @param spi_flash_wrap_mode_t mode: wrap mode support disable, 16 32, 64 byte
* @param mode: wrap mode support disable, 16 32, 64 byte
*
* @return esp_err_t : ESP_OK for successful.
*
@ -74,7 +74,7 @@ size_t spi_flash_get_chip_size();
/**
* @brief Erase the Flash sector.
*
* @param sector Sector number, the count starts at sector 0, 4KB per sector.
* @param sector: Sector number, the count starts at sector 0, 4KB per sector.
*
* @return esp_err_t
*/

2
components/spi_flash/sim/Makefile.files
View file

@ -5,10 +5,12 @@ SOURCE_FILES := \
$(addprefix ../, \
partition.c \
flash_ops.c \
esp32/flash_ops_esp32.c \
) \
INCLUDE_DIRS := \
. \
../ \
../include \
../private_include \
$(addprefix stubs/, \

2
components/spiffs/test_spiffs_host/sdkconfig/sdkconfig.h
View file

@ -1,5 +1,5 @@
#pragma once
#define CONFIG_IDF_TARGET_ESP32 1
#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1
#define CONFIG_SPIFFS_MAX_PARTITIONS 3
#define CONFIG_SPIFFS_OBJ_NAME_LEN 32

2
components/wear_levelling/test_wl_host/sdkconfig/sdkconfig.h
View file

@ -1,5 +1,5 @@
#pragma once
#define CONFIG_IDF_TARGET_ESP32 1
#define CONFIG_WL_SECTOR_SIZE 4096
#define CONFIG_LOG_DEFAULT_LEVEL 3
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000

4
components/wifi_provisioning/CMakeLists.txt
View file

@ -8,8 +8,8 @@ set(COMPONENT_SRCS "src/wifi_config.c"
"proto-c/wifi_config.pb-c.c"
"proto-c/wifi_constants.pb-c.c")
set(COMPONENT_REQUIRES lwip protocomm)
set(COMPONENT_PRIV_REQUIRES protobuf-c bt mdns json)
set(COMPONENT_REQUIRES lwip protocomm json)
set(COMPONENT_PRIV_REQUIRES protobuf-c bt mdns)
if(CONFIG_BT_ENABLED)
if(CONFIG_BT_BLUEDROID_ENABLED)

9
examples/system/network_tests/main/net_suite.c
View file

@ -29,8 +29,9 @@ void nettestif_input(void *buffer, u16_t len);
/* these data configures ARP cache so the test IPs are knows */
static char arp1[] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x06, 0x00, 0x01, 0x08, 0x00, 0x06,
0x04, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0a, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x06, 0x00, 0x01,
0x08, 0x00, 0x06, 0x04, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0a, 0x00, 0x00, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01
};
/* Test data (ICMP packet) for verification of tcp ip test netif
@ -153,10 +154,10 @@ void app_main()
setvbuf(stdin, NULL, _IONBF, 0);
setvbuf(stdout, NULL, _IONBF, 0);
/* Install UART driver for interrupt-driven reads and writes */
ESP_ERROR_CHECK( uart_driver_install( (uart_port_t)CONFIG_CONSOLE_UART_NUM,
ESP_ERROR_CHECK( uart_driver_install( (uart_port_t)CONFIG_ESP_CONSOLE_UART_NUM,
256, 0, 0, NULL, 0) );
/* Tell VFS to use UART driver */
esp_vfs_dev_uart_use_driver(CONFIG_CONSOLE_UART_NUM);
esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM);
esp_vfs_dev_uart_set_rx_line_endings(ESP_LINE_ENDINGS_CR);
/* Move the caret to the beginning of the next line on '\n' */
esp_vfs_dev_uart_set_tx_line_endings(ESP_LINE_ENDINGS_CRLF);

1
tools/unit-test-app/components/test_utils/ref_clock_esp32.c
View file

@ -38,6 +38,7 @@
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "driver/periph_ctrl.h"
#include "esp32/rom/gpio.h"
/* Select which RMT and PCNT channels, and GPIO to use */
#define REF_CLOCK_RMT_CHANNEL 7