From 3c78faa0a929188598ef4ee6c24f6fafed29495d Mon Sep 17 00:00:00 2001
From: Ivan Grokhotkov <ivan@espressif.com>
Date: Tue, 3 Apr 2018 18:14:55 +0800
Subject: [PATCH] =?UTF-8?q?soc/rtc:=20don=E2=80=99t=20switch=20frequency?=
 =?UTF-8?q?=20in=20rtc=5Fsleep=5Finit?=
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---
 components/soc/esp32/include/soc/rtc.h |  2 --
 components/soc/esp32/rtc_pm.c          |  1 -
 components/soc/esp32/rtc_sleep.c       | 13 -------------
 3 files changed, 16 deletions(-)

diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h
index ec9935fd5..3fe26eed5 100644
--- a/components/soc/esp32/include/soc/rtc.h
+++ b/components/soc/esp32/include/soc/rtc.h
@@ -427,7 +427,6 @@ void rtc_clk_wait_for_slow_cycle();
  * @brief sleep configuration for rtc_sleep_init function
  */
 typedef struct {
-    uint32_t soc_clk_sel : 2;           //!< SoC clock select, see RTC_CNTL_SOC_CLK_SEL
     uint32_t lslp_mem_inf_fpu : 1;      //!< force normal voltage in sleep mode (digital domain memory)
     uint32_t rtc_mem_inf_fpu : 1;       //!< force normal voltage in sleep mode (RTC memory)
     uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
@@ -455,7 +454,6 @@ typedef struct {
  * @param RTC_SLEEP_PD_x flags combined using bitwise OR
  */
 #define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
-    .soc_clk_sel = RTC_CNTL_SOC_CLK_SEL_XTL, \
     .lslp_mem_inf_fpu = 0, \
     .rtc_mem_inf_fpu = 0, \
     .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
diff --git a/components/soc/esp32/rtc_pm.c b/components/soc/esp32/rtc_pm.c
index 2023bd824..e5e737725 100644
--- a/components/soc/esp32/rtc_pm.c
+++ b/components/soc/esp32/rtc_pm.c
@@ -48,7 +48,6 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par
     }
 
     rtc_sleep_config_t cfg = { 0 };
-    cfg.soc_clk_sel = RTC_CNTL_SOC_CLK_SEL_XTL;
 
     switch (sleep_mode) {
         case PM_LIGHT_SLEEP:
diff --git a/components/soc/esp32/rtc_sleep.c b/components/soc/esp32/rtc_sleep.c
index 82a04d8ca..60cddf17e 100644
--- a/components/soc/esp32/rtc_sleep.c
+++ b/components/soc/esp32/rtc_sleep.c
@@ -89,9 +89,6 @@ static void rtc_sleep_pd(rtc_sleep_pd_config_t cfg)
 
 void rtc_sleep_init(rtc_sleep_config_t cfg)
 {
-    rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
-    REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, cfg.soc_clk_sel);
-
     //set 5 PWC state machine times to fit in main state machine time
     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, 1);
     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, RTC_CNTL_XTL_BUF_WAIT_DEFAULT);
@@ -112,16 +109,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, RTC_MEM_POWERUP_DELAY);
     REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, RTC_MEM_WAIT_DELAY);
 
-    if (cfg.soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) {
-        REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_DEFAULT);
-    } else if (cfg.soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_XTL) {
-        ets_update_cpu_frequency(xtal_freq);
-        rtc_clk_apb_freq_update(xtal_freq * MHZ);
-    } else if (cfg.soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_8M) {
-        ets_update_cpu_frequency(8);
-        rtc_clk_apb_freq_update(8 * MHZ);
-    }
-
     if (cfg.lslp_mem_inf_fpu) {
         SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
     } else {