diff --git a/components/bootloader/src/main/bootloader_start.c b/components/bootloader/src/main/bootloader_start.c
index bcbc64f79..345f35e49 100644
--- a/components/bootloader/src/main/bootloader_start.c
+++ b/components/bootloader/src/main/bootloader_start.c
@@ -580,7 +580,9 @@ static void set_cache_and_start_app(
     rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
     ESP_LOGV(TAG, "rc=%d", rc );
 
+#if CONFIG_MEMMAP_SPIRAM_ENABLE
     cache_sram_mmu_set( 0, 0, 0x3f800000, 0, 32, 128 );
+#endif
 
     DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
     DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
diff --git a/components/esp32/psram.c b/components/esp32/psram.c
index 607ab278f..b84923338 100644
--- a/components/esp32/psram.c
+++ b/components/esp32/psram.c
@@ -205,7 +205,6 @@ static void IRAM_ATTR psram_recv_start(psram_spi_num_t spiNum,uint32_t* pRxData,
 //setup spi command/addr/data/dummy in user mode
 static int psram_cmd_config(psram_spi_num_t spiNum, psram_cmd_t* pInData)
 {
-    uint8_t idx = 0;
     while (READ_PERI_REG(SPI_CMD_REG(spiNum))&SPI_USR);
 
     // Set command by user.
@@ -239,11 +238,9 @@ static int psram_cmd_config(psram_spi_num_t spiNum, psram_cmd_t* pInData)
         // Enable MOSI
         SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MOSI);
         // Load send buffer
-        int len = ((pInData->txDataBitLen / 32) + ((pInData->txDataBitLen % 32) ? 1 : 0));
+        int len = (pInData->txDataBitLen + 31) / 32;
         if(pTxVal != NULL) {
-            do {
-                WRITE_PERI_REG((SPI_W0_REG(spiNum) + (idx << 2)), *pTxVal++);
-            } while(++idx < len);
+            memcpy((void*)SPI_W0_REG(spiNum), pTxVal, len*4);
         }
         // Set data send buffer length.Max data length 64 bytes.
         SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spiNum), SPI_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1), SPI_USR_MOSI_DBITLEN_S);
@@ -551,9 +548,7 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spiNum,psram_cache_mode_t mode)
     }
     // Enable MOSI
     SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI);
-    for (i = 0; i < 16; ++i) {
-        WRITE_PERI_REG((SPI_W0_REG(spiNum) + (i << 2)), 0);
-    }
+    memset((void*)SPI_W0_REG(spiNum), 0, 16*4);
 }
 
 
@@ -562,7 +557,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
 {
     WRITE_PERI_REG(GPIO_ENABLE_W1TC_REG,BIT16|BIT17);//DISABLE OUPUT FOR IO16/17
 
-    assert(mode==PSRAM_CACHE_F40M_S40M); //we don't support any other mode for now.
+    assert(mode==PSRAM_CACHE_F40M_S40M && "we don't support any other mode for now.");
 
     s_psram_mode = mode;