Merge branch 'bugfix/reset_log_uart_port_v3.1' into 'release/v3.1'
esp32: Add reset CONSOLE_UART port (v3.1) See merge request idf/esp-idf!5122
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commit
34f18da855
2 changed files with 5 additions and 1 deletions
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@ -426,6 +426,7 @@ static void uart_console_configure(void)
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// (arrays should be optimized away by the compiler)
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// (arrays should be optimized away by the compiler)
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const uint32_t tx_idx_list[3] = { U0TXD_OUT_IDX, U1TXD_OUT_IDX, U2TXD_OUT_IDX };
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const uint32_t tx_idx_list[3] = { U0TXD_OUT_IDX, U1TXD_OUT_IDX, U2TXD_OUT_IDX };
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const uint32_t rx_idx_list[3] = { U0RXD_IN_IDX, U1RXD_IN_IDX, U2RXD_IN_IDX };
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const uint32_t rx_idx_list[3] = { U0RXD_IN_IDX, U1RXD_IN_IDX, U2RXD_IN_IDX };
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const uint32_t uart_reset[3] = { DPORT_UART_RST, DPORT_UART1_RST, DPORT_UART2_RST };
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const uint32_t tx_idx = tx_idx_list[uart_num];
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const uint32_t tx_idx = tx_idx_list[uart_num];
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const uint32_t rx_idx = rx_idx_list[uart_num];
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const uint32_t rx_idx = rx_idx_list[uart_num];
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@ -434,6 +435,9 @@ static void uart_console_configure(void)
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gpio_matrix_out(uart_tx_gpio, tx_idx, 0, 0);
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gpio_matrix_out(uart_tx_gpio, tx_idx, 0, 0);
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gpio_matrix_in(uart_rx_gpio, rx_idx, 0);
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gpio_matrix_in(uart_rx_gpio, rx_idx, 0);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, uart_reset[uart_num]);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, uart_reset[uart_num]);
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}
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}
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#endif // CONFIG_CONSOLE_UART_CUSTOM
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#endif // CONFIG_CONSOLE_UART_CUSTOM
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@ -327,7 +327,7 @@ void IRAM_ATTR esp_restart_noos()
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// Reset timer/spi/uart
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// Reset timer/spi/uart
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST);
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST);
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DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
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DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
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// Set CPU back to XTAL source, no PLL, same as hard reset
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// Set CPU back to XTAL source, no PLL, same as hard reset
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