freertos/test: added spill register timer measurement test
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3 changed files with 81 additions and 5 deletions
61
components/freertos/test/test_improved_isr_time.c
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61
components/freertos/test/test_improved_isr_time.c
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@ -0,0 +1,61 @@
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#include <esp_types.h>
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#include <stdio.h>
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#include "esp32/rom/ets_sys.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/xtensa_api.h"
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#include "esp_intr_alloc.h"
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#include "xtensa/hal.h"
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#include "unity.h"
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#include "soc/cpu.h"
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#include "test_utils.h"
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static SemaphoreHandle_t end_sema;
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extern uint32_t isr_enter_spent_time_cycles;
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volatile static uint32_t isr_enter_spent_time_cycles_copy;
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static void testint(void *arg) {
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xthal_set_ccompare(1, xthal_get_ccount()+8000000);
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}
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static void nested3(void) {
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intr_handle_t handle;
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esp_err_t err = esp_intr_alloc(ETS_INTERNAL_TIMER1_INTR_SOURCE, 0, &testint, NULL, &handle);
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TEST_ASSERT_EQUAL_HEX32(ESP_OK, err);
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xthal_set_ccompare(1, xthal_get_ccount()+8000000);
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vTaskDelay(10);
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isr_enter_spent_time_cycles_copy = isr_enter_spent_time_cycles;
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ets_printf("Average time spent on context save is: %d cycles\n\n", isr_enter_spent_time_cycles_copy);
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xSemaphoreGive(end_sema);
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vTaskDelete(NULL);
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}
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static void nested2(void) {
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nested3();
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}
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static void nested1(void) {
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nested2();
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}
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static void test_task(void *arg) {
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(void)arg;
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nested1();
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}
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TEST_CASE("isr handling time test", "[freertos]")
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{
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end_sema = xSemaphoreCreateBinary();
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TEST_ASSERT(end_sema != NULL);
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xTaskCreatePinnedToCore(test_task, "tst" , 4096, NULL, 3, NULL, 0);
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BaseType_t result = xSemaphoreTake(end_sema, portMAX_DELAY);
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TEST_ASSERT_EQUAL_HEX32(pdTRUE, result);
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TEST_PERFORMANCE_LESS_THAN(SPILL_REG_CYCLES, "%d cycles" ,isr_enter_spent_time_cycles_copy);
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}
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@ -57,10 +57,19 @@ NOERROR: .error "C preprocessor needed for this file: make sure its filename\
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#include <xtensa/overlay_os_asm.h>
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#include <xtensa/overlay_os_asm.h>
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#endif
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#endif
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/*
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--------------------------------------------------------------------------------
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ISR overhead statistics data:
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--------------------------------------------------------------------------------
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*/
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.data
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.align 16
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.global isr_enter_spent_time_cycles
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isr_enter_spent_time_cycles:
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.word 0
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.text
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.text
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/*******************************************************************************
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/*******************************************************************************
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_xt_context_save
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_xt_context_save
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@ -99,7 +108,6 @@ Exit conditions:
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.literal_position
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.literal_position
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.align 4
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.align 4
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_xt_context_save:
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_xt_context_save:
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s32i a2, sp, XT_STK_A2
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s32i a2, sp, XT_STK_A2
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s32i a3, sp, XT_STK_A3
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s32i a3, sp, XT_STK_A3
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s32i a4, sp, XT_STK_A4
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s32i a4, sp, XT_STK_A4
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@ -183,9 +191,16 @@ _not_l1:
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wsr a2, PS
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wsr a2, PS
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rsync
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rsync
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rsr a2, CCOUNT
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addi sp, sp, XT_STK_FRMSZ /* go back to spill register region */
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addi sp, sp, XT_STK_FRMSZ /* go back to spill register region */
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SPILL_ALL_WINDOWS /* place the live register windows there */
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SPILL_ALL_WINDOWS /* place the live register windows there */
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addi sp, sp, -XT_STK_FRMSZ /* return the current stack pointer and proceed with conext save*/
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addi sp, sp, -XT_STK_FRMSZ /* return the current stack pointer and proceed with conext save*/
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rsr a3, CCOUNT
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sub a3, a3, a2
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movi a2, isr_enter_spent_time_cycles
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s32i a3,a2,0
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#endif
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#endif
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l32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */
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l32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */
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@ -197,7 +212,6 @@ _not_l1:
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#endif
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#endif
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ret
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ret
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/*******************************************************************************
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/*******************************************************************************
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_xt_context_restore
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_xt_context_restore
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@ -32,6 +32,7 @@
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#define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_SQRT 140
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#define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_SQRT 140
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// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
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// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
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#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 9.0
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#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 9.0
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#define IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES 150
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 180000
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 180000
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