From 542e544faa5977408d08d49406ace1d6f6e488cb Mon Sep 17 00:00:00 2001 From: Gautier Seidel Date: Mon, 25 Mar 2019 15:45:57 +0100 Subject: [PATCH] esp32: Allow fixed static RAM size and DRAM heap size Merges https://github.com/espressif/esp-idf/pull/3222 --- .../subproject/main/esp32.bootloader.ld | 1 - components/esp32/Kconfig | 21 ++++++++++++++ components/esp32/ld/esp32.ld | 28 +++++++++++++++---- components/esp32/ld/esp32.project.ld.in | 2 -- components/soc/src/memory_layout_utils.c | 4 +-- tools/ldgen/samples/template.ld | 1 - 6 files changed, 46 insertions(+), 11 deletions(-) diff --git a/components/bootloader/subproject/main/esp32.bootloader.ld b/components/bootloader/subproject/main/esp32.bootloader.ld index 1eb345f76..847049096 100644 --- a/components/bootloader/subproject/main/esp32.bootloader.ld +++ b/components/bootloader/subproject/main/esp32.bootloader.ld @@ -149,7 +149,6 @@ SECTIONS *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); . = ALIGN(4); - _heap_start = ABSOLUTE(.); } >dram_seg .iram.text : diff --git a/components/esp32/Kconfig b/components/esp32/Kconfig index 8546448bb..ad7f228d9 100644 --- a/components/esp32/Kconfig +++ b/components/esp32/Kconfig @@ -719,6 +719,27 @@ menu "ESP32-specific" This option depends on the CONFIG_FREERTOS_UNICORE option because RTC fast memory can be accessed only by PRO_CPU core. + config ESP32_USE_FIXED_STATIC_RAM_SIZE + bool "Use fixed static RAM size" + default n + help + If this option is disabled, the DRAM part of the heap starts right after the .bss section, + within the dram0_0 region. As a result, adding or removing some static variables + will change the available heap size. + + If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region, + where its length is set with ESP32_FIXED_STATIC_RAM_SIZE + + config ESP32_FIXED_STATIC_RAM_SIZE + hex "Fixed Static RAM size" + default 0x1E000 + range 0 0x2c200 + depends on ESP32_USE_FIXED_STATIC_RAM_SIZE + help + RAM size dedicated for static variables (.data & .bss sections). + Please note that the actual length will be reduced by BT_RESERVE_DRAM if Bluetooth + controller is enabled. + endmenu # ESP32-Specific menu "Power Management" diff --git a/components/esp32/ld/esp32.ld b/components/esp32/ld/esp32.ld index c50c70a7f..d88cdc034 100644 --- a/components/esp32/ld/esp32.ld +++ b/components/esp32/ld/esp32.ld @@ -21,6 +21,17 @@ #define CONFIG_BT_RESERVE_DRAM 0 #endif +#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE) + +ASSERT((CONFIG_ESP32_FIXED_STATIC_RAM_SIZE <= 0x2c200), + "Fixed static ram data does not fit.") + +#define DRAM0_0_SEG_LEN CONFIG_ESP32_FIXED_STATIC_RAM_SIZE + +#else +#define DRAM0_0_SEG_LEN 0x2c200 +#endif + MEMORY { /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length @@ -51,7 +62,7 @@ MEMORY additional static memory temporarily cannot be used. */ dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM, - len = 0x2c200 - CONFIG_BT_RESERVE_DRAM + len = DRAM0_0_SEG_LEN - CONFIG_BT_RESERVE_DRAM /* Flash mapped constant data */ drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18 @@ -61,7 +72,7 @@ MEMORY /* RTC fast memory (executable). Persists over deep sleep. */ rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 - + /* RTC fast memory (same block as above), viewed from data bus */ rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000 @@ -77,14 +88,21 @@ MEMORY len = 0x400000 } +#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE) +/* static data ends at defined address */ +_static_data_end = 0x3FFB0000 + DRAM0_0_SEG_LEN; +#else +_static_data_end = _bss_end; +#endif + /* Heap ends at top of dram0_0_seg */ _heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM; _data_seg_org = ORIGIN(rtc_data_seg); -/* The lines below define location alias for .rtc.data section based on Kconfig option. - When the option is not defined then use slow memory segment - else the data will be placed in fast memory segment */ +/* The lines below define location alias for .rtc.data section based on Kconfig option. + When the option is not defined then use slow memory segment + else the data will be placed in fast memory segment */ #ifndef CONFIG_ESP32_RTCDATA_IN_FAST_MEM REGION_ALIAS("rtc_data_location", rtc_slow_seg ); #else diff --git a/components/esp32/ld/esp32.project.ld.in b/components/esp32/ld/esp32.project.ld.in index a38abce64..774ebcefb 100644 --- a/components/esp32/ld/esp32.project.ld.in +++ b/components/esp32/ld/esp32.project.ld.in @@ -239,8 +239,6 @@ SECTIONS . = ALIGN (8); _bss_end = ABSOLUTE(.); - /* The heap starts right after end of this section */ - _heap_start = ABSOLUTE(.); } > dram0_0_seg ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), diff --git a/components/soc/src/memory_layout_utils.c b/components/soc/src/memory_layout_utils.c index c1abc98ae..b43865fd6 100644 --- a/components/soc/src/memory_layout_utils.c +++ b/components/soc/src/memory_layout_utils.c @@ -29,7 +29,7 @@ extern soc_reserved_region_t soc_reserved_memory_region_end; These variables have the start and end of the data and static IRAM area used by the program. Defined in the linker script. */ -extern int _data_start, _bss_end, _iram_start, _iram_end; +extern int _data_start, _static_data_end, _iram_start, _iram_end; /* static DRAM & IRAM chunks */ static const size_t EXTRA_RESERVED_REGIONS = 2; @@ -68,7 +68,7 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c /* Add the EXTRA_RESERVED_REGIONS at the beginning */ reserved[0].start = (intptr_t)&_data_start; /* DRAM used by data+bss */ - reserved[0].end = (intptr_t)&_bss_end; + reserved[0].end = (intptr_t)&_static_data_end; reserved[1].start = (intptr_t)&_iram_start; /* IRAM used by code */ reserved[1].end = (intptr_t)&_iram_end; diff --git a/tools/ldgen/samples/template.ld b/tools/ldgen/samples/template.ld index 512f724e2..743cf5c69 100644 --- a/tools/ldgen/samples/template.ld +++ b/tools/ldgen/samples/template.ld @@ -134,7 +134,6 @@ SECTIONS . = ALIGN (8); _bss_end = ABSOLUTE(.); - _heap_start = ABSOLUTE(.); } >dram0_0_seg .flash.rodata :