diff --git a/components/esp32/cache_err_int.c b/components/esp32/cache_err_int.c
index d8fa649a0..a6de81ce6 100644
--- a/components/esp32/cache_err_int.c
+++ b/components/esp32/cache_err_int.c
@@ -29,6 +29,7 @@
 #include "esp_attr.h"
 #include "soc/dport_reg.h"
 #include "sdkconfig.h"
+#include "esp_dport_access.h"
 
 void esp_cache_err_int_init()
 {
@@ -72,6 +73,7 @@ void esp_cache_err_int_init()
 
 int IRAM_ATTR esp_cache_err_get_cpuid()
 {
+    esp_dport_access_int_pause();
     const uint32_t pro_mask =
             DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 |
             DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 |
diff --git a/components/esp32/dport_access.c b/components/esp32/dport_access.c
index 8cafeb456..af6c92e1a 100644
--- a/components/esp32/dport_access.c
+++ b/components/esp32/dport_access.c
@@ -184,7 +184,7 @@ void esp_dport_access_int_init(void)
     assert(res == pdTRUE);
 }
 
-void esp_dport_access_int_pause(void)
+void IRAM_ATTR esp_dport_access_int_pause(void)
 {
     portENTER_CRITICAL_ISR(&g_dport_mux);
     dport_core_state[0] = DPORT_CORE_STATE_IDLE;
@@ -194,7 +194,7 @@ void esp_dport_access_int_pause(void)
     portEXIT_CRITICAL_ISR(&g_dport_mux);
 }
 
-void esp_dport_access_int_resume(void)
+void IRAM_ATTR esp_dport_access_int_resume(void)
 {
     portENTER_CRITICAL_ISR(&g_dport_mux);
     dport_core_state[0] = DPORT_CORE_STATE_RUNNING;