bugfix(80m flash): cherry pick from idf3.0, add gpio config and vddsdio config
1. raise vddsdio for 1.8v flash 2. gpio matrix config for flash 3. fix esp_restart function todo: to decide whether to raise core voltage to test deep-sleep current
This commit is contained in:
Wangjialin
parent
f108f5394f
commit
305e2695d6
8 changed files with 209 additions and 6 deletions
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@ -28,8 +28,17 @@ config LOG_BOOTLOADER_LEVEL
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default 4 if LOG_BOOTLOADER_LEVEL_DEBUG
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default 5 if LOG_BOOTLOADER_LEVEL_VERBOSE
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endmenu
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config BOOTLOADER_VDDSDIO_BOOST
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bool "Increase VDDSDIO LDO voltage to 1.9V"
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default y
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help
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If this option is enabled, and VDDSDIO LDO is set to 1.8V (using EFUSE
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or MTDI bootstrapping pin), bootloader will change LDO settings to
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output 1.9V instead. This helps prevent flash chip from browning out
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during flash programming operations.
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For 3.3V flash, this option has no effect.
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endmenu # Bootloader
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menu "Security features"
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@ -72,6 +72,8 @@ static void set_cache_and_start_app(uint32_t drom_addr,
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uint32_t irom_size,
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uint32_t entry_addr);
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static void update_flash_config(const esp_image_header_t* pfhdr);
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static void vddsdio_configure();
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static void flash_gpio_configure();
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static void clock_configure(void);
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static void uart_console_configure(void);
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static void wdt_reset_check(void);
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@ -237,6 +239,8 @@ static bool ota_select_valid(const esp_ota_select_entry_t *s)
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void bootloader_main()
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{
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vddsdio_configure();
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flash_gpio_configure();
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clock_configure();
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uart_console_configure();
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wdt_reset_check();
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@ -697,6 +701,104 @@ void print_flash_info(const esp_image_header_t* phdr)
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#endif
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}
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static void vddsdio_configure()
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{
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#if CONFIG_BOOTLOADER_VDDSDIO_BOOST
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rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
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if (cfg.tieh == 0) { // 1.8V is used
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cfg.drefh = 3;
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cfg.drefm = 3;
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cfg.drefl = 3;
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cfg.force = 1;
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cfg.enable = 1;
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rtc_vddsdio_set_config(cfg);
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ets_delay_us(10); // wait for regulator to become stable
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}
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#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
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}
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#define FLASH_CLK_IO 6
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#define FLASH_CS_IO 11
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#define FLASH_SPIQ_IO 7
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#define FLASH_SPID_IO 8
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#define FLASH_SPIWP_IO 10
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#define FLASH_SPIHD_IO 9
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#define FLASH_IO_MATRIX_DUMMY_40M 1
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#define FLASH_IO_MATRIX_DUMMY_80M 2
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static void IRAM_ATTR flash_gpio_configure()
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{
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int spi_cache_dummy = 0;
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int drv = 2;
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#if CONFIG_FLASHMODE_QIO
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spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN; //qio 3
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#elif CONFIG_FLASHMODE_QOUT
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; //qout 7
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#elif CONFIG_FLASHMODE_DIO
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; //dio 3
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#elif CONFIG_FLASHMODE_DOUT
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; //dout 7
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#endif
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/* dummy_len_plus values defined in ROM for SPI flash configuration */
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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#if CONFIG_ESPTOOLPY_FLASHFREQ_40M
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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drv = 3;
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#endif
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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uint32_t pkg_ver = chip_ver & 0x7;
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if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
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// For ESP32D2WD the SPI pins are already configured
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ESP_LOGI(TAG, "Detected ESP32D2WD");
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//flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
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// For ESP32PICOD2 the SPI pins are already configured
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ESP_LOGI(TAG, "Detected ESP32PICOD2");
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//flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
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// For ESP32PICOD4 the SPI pins are already configured
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ESP_LOGI(TAG, "Detected ESP32PICOD4");
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//flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else {
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ESP_LOGI(TAG, "Detected ESP32");
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
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gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
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gpio_matrix_out(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
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gpio_matrix_out(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPID_IO, SPID_IN_IDX, 0);
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gpio_matrix_out(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
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gpio_matrix_out(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
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//select pin function gpio
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
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// flash clock signal should come from IO MUX.
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// set drive ability for clock
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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}
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}
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}
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static void clock_configure(void)
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{
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@ -163,7 +163,7 @@ static void enable_qio_mode(read_status_fn_t read_status_fn,
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// spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP.
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//
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// For now, in this situation we only support Quad I/O mode for ESP32-D2WD where WP pin is known.
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_RESERVE);
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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uint32_t pkg_ver = chip_ver & 0x7;
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const uint32_t PKG_VER_ESP32_D2WD = 2; // TODO: use chip detection API once available
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if (pkg_ver != PKG_VER_ESP32_D2WD) {
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@ -291,6 +291,14 @@ void IRAM_ATTR esp_restart_noos()
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uart_tx_wait_idle(0);
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uart_tx_wait_idle(1);
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uart_tx_wait_idle(2);
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// 2nd stage bootloader reconfigures SPI flash signals.
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// Reset them to the defaults expected by ROM.
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WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
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// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
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DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
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@ -364,8 +372,10 @@ static void get_chip_info_esp32(esp_chip_info_t* out_info)
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if ((reg & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
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out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
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}
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if (((reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S) ==
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EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
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int package = (reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S;
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if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
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package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
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package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
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out_info->features |= CHIP_FEATURE_EMB_FLASH;
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}
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}
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@ -100,6 +100,9 @@
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#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0
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#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1
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#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2
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#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4
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#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5
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/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */
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/*description: read for SPI_pad_config_hd*/
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#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F
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@ -129,8 +129,7 @@
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#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038)
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/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */
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/*description: GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel
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boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5}*/
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/*description: {10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} */
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#define GPIO_STRAPPING 0x0000FFFF
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#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
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#define GPIO_STRAPPING_V 0xFFFF
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@ -524,6 +524,36 @@ typedef struct {
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*/
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void rtc_init(rtc_config_t cfg);
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/**
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* Structure describing vddsdio configuration
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*/
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typedef struct {
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uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
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uint32_t enable : 1; //!< Enable VDDSDIO regulator
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uint32_t tieh : 1; //!< Select VDDSDIO voltage: 1 — 1.8V, 0 — 3.3V
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uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator
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uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator
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uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator
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} rtc_vddsdio_config_t;
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/**
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* Get current VDDSDIO configuration
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* If VDDSDIO configuration is overridden by RTC, get values from RTC
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* Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
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* Otherwise, use default values and the level of MTDI bootstrapping pin.
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* @return currently used VDDSDIO configuration
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*/
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rtc_vddsdio_config_t rtc_vddsdio_get_config();
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/**
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* Set new VDDSDIO configuration using RTC registers.
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* If config.force == 1, this overrides configuration done using bootstrapping
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* pins and EFUSE.
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*
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* @param config new VDDSDIO configuration
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*/
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void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
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#ifdef __cplusplus
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}
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@ -18,6 +18,8 @@
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/gpio_reg.h"
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void rtc_init(rtc_config_t cfg)
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@ -94,3 +96,51 @@ void rtc_init(rtc_config_t cfg)
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
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}
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}
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rtc_vddsdio_config_t rtc_vddsdio_get_config()
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{
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rtc_vddsdio_config_t result;
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uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);
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result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S;
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result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S;
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result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S;
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if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) {
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// Get configuration from RTC
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result.force = 1;
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result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
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result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
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return result;
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}
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uint32_t efuse_reg = REG_READ(EFUSE_BLK0_RDATA4_REG);
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if (efuse_reg & EFUSE_RD_SDIO_FORCE) {
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// Get configuration from EFUSE
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result.force = 0;
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result.enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) >> EFUSE_RD_XPD_SDIO_REG_S;
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result.tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) >> EFUSE_RD_SDIO_TIEH_S;
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// in this case, DREFH/M/L are also set from EFUSE
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result.drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) >> EFUSE_RD_SDIO_DREFH_S;
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result.drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) >> EFUSE_RD_SDIO_DREFM_S;
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result.drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) >> EFUSE_RD_SDIO_DREFL_S;
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return result;
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}
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// Otherwise, VDD_SDIO is controlled by bootstrapping pin
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uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
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result.force = 0;
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result.tieh = (strap_reg & BIT(5)) ? 0 : 1;
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result.enable = result.tieh == 0; // only power on the regulator if VDD=1.8
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return result;
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}
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void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
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{
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uint32_t val = 0;
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val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
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val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
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val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
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val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
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val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
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val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
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val |= RTC_CNTL_SDIO_PD_EN;
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REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
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}
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