feature(psram): add 80Mhz mode for psram. Since we have flash rom code patch now, we can fix the compatibility issue between SPI APIs and psram.
1. add qio enable option in bootloader for GD25LQ32C flash. 2. add option for psram mode: 40m+40m, 80m+40m, 80m+80m. 3. fix bugs in spi_flash_rom_patch
This commit is contained in:
Wangjialin
parent
983c3d7e1d
commit
2fbc62f986
5 changed files with 123 additions and 35 deletions
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@ -84,7 +84,7 @@ const static qio_info_t chip_data[] = {
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{ "MXIC", 0xC2, 0x2000, 0xFF00, read_status_8b_rdsr, write_status_8b_wrsr, 6 },
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{ "ISSI", 0x9D, 0x4000, 0xCF00, read_status_8b_rdsr, write_status_8b_wrsr, 6 }, /* IDs 0x40xx, 0x70xx */
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{ "WinBond", 0xEF, 0x4000, 0xFF00, read_status_16b_rdsr_rdsr2, write_status_16b_wrsr, 9 },
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{ "GD", 0xC8, 0x6000, 0xFF00, read_status_16b_rdsr_rdsr2, write_status_16b_wrsr, 9 },
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/* Final entry is default entry, if no other IDs have matched.
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This approach works for chips including:
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@ -157,6 +157,24 @@ config MEMMAP_SPIRAM_ENABLE
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if MEMMAP_SPIRAM_ENABLE
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choice SPIRAM_CACHE_MODE
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bool "Set FLASH and SRAM cache mode"
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default SRAM_CACHE_SPEED_40M
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help
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The ESP32 can access both of the flash and sram chip by CACHE.
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If SPI SRAM is enabled, we only support three combinations of SPI speed mode we supported now:
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1. Flash SPI running at 40Mhz and SRAM SPI running at 40Mhz
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2. Flash SPI running at 80Mhz and SRAM SPI running at 40Mhz
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3. Flash SPI running at 80Mhz and SRAM SPI running at 80Mhz
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note: If the third mode(80Mhz+80Mhz) is enabled, VSPI port will be occupied by the system,
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Application code should never touch VSPI hardware in this case.
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config SRAM_CACHE_SPEED_40M
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bool "SRAM cache speed 40M"
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config SRAM_CACHE_SPEED_80M
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bool "SRAM cache speed 80M"
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endchoice
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config SPIRAM_CACHE_WORKAROUND
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bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
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default "y"
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@ -149,10 +149,24 @@ void IRAM_ATTR call_start_cpu0()
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}
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#if CONFIG_MEMMAP_SPIRAM_ENABLE
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if ( psram_enable(PSRAM_CACHE_F40M_S40M, PSRAM_MODE) != ESP_OK) {
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int sram_mode = 0;
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#if CONFIG_SRAM_CACHE_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M
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sram_mode = PSRAM_CACHE_F40M_S40M;
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#elif CONFIG_SRAM_CACHE_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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sram_mode = PSRAM_CACHE_F80M_S40M;
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#elif CONFIG_SRAM_CACHE_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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sram_mode = PSRAM_CACHE_F80M_S80M;
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#else
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ESP_EARLY_LOGE(TAG, "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!");
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abort();
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#endif
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if ( psram_enable(sram_mode, PSRAM_MODE) != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "PSRAM enabled but initialization failed. Bailing out.");
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abort();
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} else {
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ESP_EARLY_LOGI(TAG, "PSRAM mode: %s", sram_mode == PSRAM_CACHE_F40M_S40M ? "flash 40m sram 40m" : \
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sram_mode == PSRAM_CACHE_F80M_S40M ? "flash 80m sram 40m" : \
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sram_mode == PSRAM_CACHE_F80M_S80M ? "flash 80m sram 80m" : "ERROR");
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ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", (PSRAM_MODE==PSRAM_VADDR_MODE_EVENODD)?"even/odd (2-core)":"normal (1-core");
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}
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#endif
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@ -11,28 +11,25 @@
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include "string.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "rom/ets_sys.h"
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#include "esp_psram.h"
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#include "rom/ets_sys.h"
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#include "rom/spi_flash.h"
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#include "rom/gpio.h"
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#include "rom/cache.h"
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#include "soc/io_mux_reg.h"
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#include "soc/dport_reg.h"
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#include "rom/gpio.h"
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#include "soc/gpio_sig_map.h"
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#include "esp_attr.h"
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#include "rom/cache.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/timers.h"
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#include "freertos/task.h"
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#include "string.h"
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#include "rom/spi_flash.h"
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#include "esp_err.h"
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#include "rom/cache.h"
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#include "driver/gpio.h"
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//Commands for PSRAM chip
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#define PSRAM_READ 0x03
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#define PSRAM_FAST_READ 0x0B
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#define PSRAM_FAST_READ_DUMMY 0x3
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#define PSRAM_FAST_READ_QUAD 0xEB
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#define PSRAM_WRITE 0x02
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#define PSRAM_QUAD_WRITE 0x38
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@ -50,6 +47,22 @@
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#define PSRAM_CLK_IO 17
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#define PSRAM_CS_IO 16
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#define PSRAM_IO_MATRIX_DUMMY_40M (1)
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#define PSRAM_IO_MATRIX_DUMMY_80M (2)
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#if CONFIG_FLASHMODE_QIO
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#define SPI_CACHE_DUMMY SPI0_R_QIO_DUMMY_CYCLELEN //qio 3
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#elif CONFIG_FLASHMODE_QOUT
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#define SPI_CACHE_DUMMY SPI0_R_FAST_DUMMY_CYCLELEN //qout 7
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#elif CONFIG_FLASHMODE_DIO
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#define SPI_CACHE_DUMMY SPI0_R_DIO_DUMMY_CYCLELEN //dio 3
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#elif CONFIG_FLASHMODE_DOUT
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#define SPI_CACHE_DUMMY SPI0_R_FAST_DUMMY_CYCLELEN //dout 7
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#endif
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typedef enum {
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PSRAM_SPI_1 = 0x1,
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PSRAM_SPI_2,
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@ -60,7 +73,11 @@ typedef enum {
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static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX;
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//For now, we only use F40M + S40M, and we don't have to go through gpio matrix
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#define DISABLE_GPIO_MATRIX_FOR_40M 1
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#define ENABLE_GPIO_MATRIX_SPI 1
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/* dummy_len_plus values defined in ROM for SPI flash configuration */
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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static int extra_dummy = 0;
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typedef enum {
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@ -387,7 +404,7 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
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CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_SLAVE_MODE);
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switch (mode) {
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case PSRAM_CACHE_F80M_S80M:
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WRITE_PERI_REG(SPI_CLOCK_REG(spi_num), SPI_CLK_EQU_SYSCLK); // 80Mhz speed
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// WRITE_PERI_REG(SPI_CLOCK_REG(spi_num), SPI_CLK_EQU_SYSCLK); // 80Mhz speed
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break;
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case PSRAM_CACHE_F80M_S40M:
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case PSRAM_CACHE_F40M_S40M:
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@ -407,11 +424,54 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
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memset((void*)SPI_W0_REG(spi_num), 0, 16 * 4);
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}
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static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
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{
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gpio_matrix_out(6, SPICLK_OUT_IDX, 0, 0);
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gpio_matrix_out(11, SPICS0_OUT_IDX, 0, 0);
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gpio_matrix_out(7, SPIQ_OUT_IDX, 0, 0);
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gpio_matrix_in(7,SPIQ_IN_IDX, 0);
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gpio_matrix_out(8, SPID_OUT_IDX, 0, 0);
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gpio_matrix_in(8, SPID_IN_IDX, 0);
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gpio_matrix_out(10, SPIWP_OUT_IDX, 0, 0);
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gpio_matrix_in(10, SPIWP_IN_IDX, 0);
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gpio_matrix_out(9, SPIHD_OUT_IDX, 0, 0);
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gpio_matrix_in(9, SPIHD_IN_IDX, 0);
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switch (mode) {
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case PSRAM_CACHE_F80M_S40M:
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extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
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g_rom_spiflash_dummy_len_plus[1] = PSRAM_IO_MATRIX_DUMMY_40M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, SPI_CACHE_DUMMY + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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break;
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case PSRAM_CACHE_F80M_S80M:
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extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
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g_rom_spiflash_dummy_len_plus[1] = PSRAM_IO_MATRIX_DUMMY_80M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, SPI_CACHE_DUMMY + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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break;
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case PSRAM_CACHE_F40M_S40M:
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extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
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g_rom_spiflash_dummy_len_plus[1] = PSRAM_IO_MATRIX_DUMMY_40M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, SPI_CACHE_DUMMY + PSRAM_IO_MATRIX_DUMMY_40M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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break;
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default:
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break;
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}
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SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_USR_DUMMY); // dummy en
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//select pin function gpio
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 2);
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}
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//psram gpio init , different working frequency we have different solutions
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esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init
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{
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WRITE_PERI_REG(GPIO_ENABLE_W1TC_REG, BIT(PSRAM_CLK_IO) | BIT(PSRAM_CS_IO)); //DISABLE OUPUT FOR IO16/17
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assert(mode == PSRAM_CACHE_F40M_S40M && "we don't support any other mode for now.");
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assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
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s_psram_mode = mode;
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SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN);
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@ -426,8 +486,9 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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switch (mode) {
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case PSRAM_CACHE_F80M_S80M:
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/* note: If the third mode(80Mhz+80Mhz) is enabled, VSPI port will be occupied by the system,
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Application code should never touch VSPI hardware in this case. */
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psram_spi_init(PSRAM_SPI_1, mode);
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extra_dummy = 2;
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CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_HOLD);
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gpio_matrix_out(PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
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gpio_matrix_out(PSRAM_CLK_IO, VSPICLK_OUT_IDX, 0, 0);
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@ -447,11 +508,6 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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case PSRAM_CACHE_F80M_S40M:
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case PSRAM_CACHE_F40M_S40M:
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default:
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#if DISABLE_GPIO_MATRIX_FOR_40M
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extra_dummy = 0;
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#else
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extra_dummy = 1;
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#endif
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psram_spi_init(PSRAM_SPI_1, mode);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_HOLD);
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gpio_matrix_out(PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
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@ -463,7 +519,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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}
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CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_SETUP_M);
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#if (!DISABLE_GPIO_MATRIX_FOR_40M)
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#if ENABLE_GPIO_MATRIX_SPI
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psram_gpio_config(mode);
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#endif
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WRITE_PERI_REG(GPIO_ENABLE_W1TS_REG, BIT(PSRAM_CS_IO)| BIT(PSRAM_CLK_IO));
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@ -494,7 +550,7 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psra
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CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. FLASH DIV 2+SRAM DIV4
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WRITE_PERI_REG(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M); //SET 1DIV CLOCK AND RESET OTHER PARAMS
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SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
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SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, 3 + extra_dummy,
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SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_DUMMY + extra_dummy,
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SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
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SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command
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break;
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@ -502,7 +558,7 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psra
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SET_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
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CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0.
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SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
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SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, 3 + extra_dummy,
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SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_DUMMY + extra_dummy,
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SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
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SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command
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break;
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@ -511,7 +567,7 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psra
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CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
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CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div
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SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
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SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, 3 + extra_dummy,
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SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_DUMMY + extra_dummy,
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SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
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SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command
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break;
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@ -526,11 +582,11 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psra
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case PSRAM_CACHE_F80M_S80M: //in this mode , no delay is needed
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SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
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SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
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SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, 0x38,
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SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE,
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SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
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SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
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SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
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SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, 0x0b,
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SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ,
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SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b
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break;
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case PSRAM_CACHE_F80M_S40M: //is sram is @40M, need 2 cycles of delay
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@ -538,11 +594,11 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psra
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default:
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SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15,
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SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache
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SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, 0x0b00,
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SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, ((PSRAM_FAST_READ) << 8),
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SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b, read command value,(0x00 for delay,0x0b for cmd)
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SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 15,
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SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache)
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SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, 0x3800,
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SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, ((PSRAM_QUAD_WRITE) << 8),
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SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
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break;
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}
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||||
|
|
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|||
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@ -535,14 +535,14 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t target, uint32_t *dest_
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modebit = READ_PERI_REG(PERIPHS_SPI_FLASH_CTRL);
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if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) {
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REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
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REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
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REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR | SPI_USR_COMMAND);
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REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_QIO_ADDR_BITSLEN);
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REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
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||||
//REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xEB);
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REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xEB);
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||||
} else if (modebit & SPI_FASTRD_MODE) {
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||||
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
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REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR);
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||||
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR | SPI_USR_COMMAND);
|
||||
if (modebit & SPI_FREAD_DIO) {
|
||||
if (g_rom_spiflash_dummy_len_plus[1] == 0) {
|
||||
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
||||
|
|
@ -552,7 +552,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t target, uint32_t *dest_
|
|||
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
||||
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
|
||||
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
|
||||
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xBB);
|
||||
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xBB);
|
||||
}
|
||||
} else {
|
||||
if ((modebit & SPI_FREAD_QUAD)) {
|
||||
|
|
@ -577,7 +577,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t target, uint32_t *dest_
|
|||
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
|
||||
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
|
||||
}
|
||||
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR);
|
||||
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR | SPI_USR_COMMAND);
|
||||
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_SIO_ADDR_BITSLEN);
|
||||
//REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x03);
|
||||
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x03);
|
||||
|
|
|
|||
Loading…
Reference in a new issue