Crash_Override/OVMS3-idf
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update esp32 component

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This commit is contained in:
suda-morris 2019-04-08 18:02:05 +08:00
parent c926f7515e
commit 2f4c5c51f4
4 changed files with 23 additions and 17 deletions
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6
Kconfig
View file

@ -31,11 +31,13 @@ mainmenu "Espressif IoT Development Framework Configuration"
config IDF_TARGET_ESP32 config IDF_TARGET_ESP32
bool bool
default y if IDF_TARGET="esp32" default "y" if IDF_TARGET="esp32"
default "n"
config IDF_TARGET_ESP32S2BETA config IDF_TARGET_ESP32S2BETA
bool bool
default y if IDF_TARGET="esp32s2beta" default "y" if IDF_TARGET="esp32s2beta"
default "n"
menu "SDK tool configuration" menu "SDK tool configuration"
config SDK_TOOLPREFIX config SDK_TOOLPREFIX

7
components/esp32/intr_alloc.c
View file

@ -548,9 +548,12 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
//Statusreg should have a mask //Statusreg should have a mask
if (intrstatusreg && !intrstatusmask) return ESP_ERR_INVALID_ARG; if (intrstatusreg && !intrstatusmask) return ESP_ERR_INVALID_ARG;
//If the ISR is marked to be IRAM-resident, the handler must not be in the cached region //If the ISR is marked to be IRAM-resident, the handler must not be in the cached region
//ToDo: if we are to allow placing interrupt handlers into the 0x400c0000—0x400c2000 region,
//we need to make sure the interrupt is connected to the CPU0.
//CPU1 does not have access to the RTC fast memory through this region.
if ((flags&ESP_INTR_FLAG_IRAM) && if ((flags&ESP_INTR_FLAG_IRAM) &&
(ptrdiff_t) handler >= 0x400C0000 && (ptrdiff_t) handler >= SOC_RTC_IRAM_HIGH &&
(ptrdiff_t) handler < 0x50000000 ) { (ptrdiff_t) handler < SOC_RTC_DATA_LOW ) {
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }

10
components/esp32/test/test_spiram_cache_flush.c
View file

@ -61,8 +61,8 @@ TEST_CASE("Spiram cache flush on mmap", "[spiram]")
mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM); mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM); mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
#else #else
mem[0]=(void*)0x3f800000; mem[0]=(void*)SOC_EXTRAM_DATA_LOW;
mem[1]=(void*)0x3f800000+TSTSZ; mem[1]=(void*)SOC_EXTRAM_DATA_LOW+TSTSZ;
#endif #endif
assert(mem[0]); assert(mem[0]);
assert(mem[1]); assert(mem[1]);
@ -105,8 +105,8 @@ TEST_CASE("Spiram cache flush on write/read", "[spiram]")
mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM); mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM); mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
#else #else
mem[0]=(void*)0x3f800000; mem[0]=(void*)SOC_EXTRAM_DATA_LOW;
mem[1]=(void*)0x3f800000+TSTSZ; mem[1]=(void*)SOC_EXTRAM_DATA_LOW+TSTSZ;
#endif #endif
assert(mem[0]); assert(mem[0]);
assert(mem[1]); assert(mem[1]);
@ -148,7 +148,7 @@ IRAM_ATTR TEST_CASE("Spiram memcmp weirdness at 80MHz", "[spiram]") {
#if USE_CAPS_ALLOC #if USE_CAPS_ALLOC
char *mem2=heap_caps_malloc(0x10000, MALLOC_CAP_SPIRAM); char *mem2=heap_caps_malloc(0x10000, MALLOC_CAP_SPIRAM);
#else #else
char *mem2=(void*)0x3f800000; char *mem2=(void*)SOC_EXTRAM_DATA_LOW;
#endif #endif
#if !CONFIG_SPIRAM_SPEED_80M #if !CONFIG_SPIRAM_SPEED_80M

1
components/esp_common/include/esp_system.h
View file

@ -324,6 +324,7 @@ const char* esp_get_idf_version(void);
*/ */
typedef enum { typedef enum {
CHIP_ESP32 = 1, //!< ESP32 CHIP_ESP32 = 1, //!< ESP32
CHIP_ESP32S2BETA = 2, //!< ESP32S2BETA
} esp_chip_model_t; } esp_chip_model_t;
/* Chip feature flags, used in esp_chip_info_t */ /* Chip feature flags, used in esp_chip_info_t */