From 8b6060e24ec59e9bb0edb076076cc645b326a166 Mon Sep 17 00:00:00 2001 From: Taavi Hein Date: Wed, 8 Aug 2018 15:31:17 +0300 Subject: [PATCH] gpio: Bitmask overflow fix in gpio_reset_pin For pins 32 and up the BIT(nr) macro used here overflowed, causing undetermined GPIO pins to be reset. Example: freeing SPI device/bus where CS is on pin 33 caused debug UART to cease communication, TXD0 was disabled. Fixed as BIT64(nr) macro, to be used elsewhere as needed. For example in definitions like GPIO_SEL_32..GPIO_SEL_39. --- components/driver/gpio.c | 2 +- components/soc/esp32/include/soc/soc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/components/driver/gpio.c b/components/driver/gpio.c index 07bf69885..d81d2c25c 100644 --- a/components/driver/gpio.c +++ b/components/driver/gpio.c @@ -316,7 +316,7 @@ esp_err_t gpio_reset_pin(gpio_num_t gpio_num) { assert(gpio_num >= 0 && GPIO_IS_VALID_GPIO(gpio_num)); gpio_config_t cfg = { - .pin_bit_mask = BIT(gpio_num), + .pin_bit_mask = BIT64(gpio_num), .mode = GPIO_MODE_DISABLE, //for powersave reasons, the GPIO should not be floating, select pullup .pull_up_en = true, diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 660abbdb3..bc822e236 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -133,6 +133,7 @@ #ifndef __ASSEMBLER__ #define BIT(nr) (1UL << (nr)) +#define BIT64(nr) (1ULL << (nr)) #else #define BIT(nr) (1 << (nr)) #endif