diff --git a/components/esp_timer/src/esp_timer_impl_systimer.c b/components/esp_timer/src/esp_timer_impl_systimer.c index 5bd712b3b..5c7bfaabc 100644 --- a/components/esp_timer/src/esp_timer_impl_systimer.c +++ b/components/esp_timer/src/esp_timer_impl_systimer.c @@ -1,4 +1,4 @@ -// Copyright 2017 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -12,63 +12,30 @@ // See the License for the specific language governing permissions and // limitations under the License. -#include #include "esp_timer_impl.h" #include "esp_err.h" #include "esp_timer.h" #include "esp_attr.h" #include "esp_intr_alloc.h" #include "esp_log.h" -#include "soc/rtc.h" -#include "soc/systimer_reg.h" #include "soc/periph_defs.h" #include "freertos/FreeRTOS.h" +#include "hal/systimer_ll.h" +#include "hal/systimer_types.h" +#include "hal/systimer_hal.h" /** * @file esp_timer_systimer.c - * @brief Implementation of chip-specific part of esp_timer + * @brief Implementation of esp_timer using systimer. * - * This implementation uses SYSTIMER of the ESP32-S2. This timer is - * a 64-bit up-counting timer, with a programmable compare value (called 'alarm' - * hereafter). When the timer reaches compare value, interrupt is raised. - * The timer can be configured to produce an edge or a level interrupt. + * This timer is a 64-bit up-counting timer, with a programmable compare value (called 'alarm' hereafter). + * When the timer reaches compare value, interrupt is raised. + * The timer can be configured to produce an edge interrupt. + * + * @note systimer counter0 and alarm2 are adopted to implemented esp_timer */ -/* esp_timer uses the 2 compare unit of SYSTIMER. */ -#define INTR_SOURCE_LACT (ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE) -// Registers -#define COUNT_LO_REG (SYSTIMER_VALUE_LO_REG) -#define COUNT_HI_REG (SYSTIMER_VALUE_HI_REG) -#define LOAD_LO_REG (SYSTIMER_LOAD_LO_REG) -#define LOAD_HI_REG (SYSTIMER_LOAD_HI_REG) -#define ALARM_LO_REG (SYSTIMER_TARGET2_LO_REG) -#define ALARM_HI_REG (SYSTIMER_TARGET2_HI_REG) -// Macros -#define ENABLE_CLK() (REG_SET_BIT(SYSTIMER_CONF_REG, SYSTIMER_CLK_EN)) -#define ENABLE_INT() (REG_SET_BIT(SYSTIMER_INT_ENA_REG, SYSTIMER_INT2_ENA)) -#define DISABLE_INT() (REG_CLR_BIT(SYSTIMER_INT_ENA_REG, SYSTIMER_INT2_ENA)) -#define GET_INT_FLAG() (REG_GET_FIELD(SYSTIMER_INT_RAW_REG, SYSTIMER_INT2_RAW)) -#define CLEAR_INT() (REG_WRITE(SYSTIMER_INT_CLR_REG, SYSTIMER_INT2_CLR)) -#define DISABLE_COMPARE_UNIT() (REG_WRITE(SYSTIMER_TARGET2_CONF_REG, 0)) -#define ENABLE_COMPARE_UNIT() (REG_WRITE(SYSTIMER_TARGET2_CONF_REG, SYSTIMER_TARGET2_WORK_EN)) -#define APPLY_LOADED_VAL() (REG_SET_BIT(SYSTIMER_LOAD_REG, SYSTIMER_TIMER_LOAD)) -#define SETTING_STEP_FOR_PLL_SRC(step) (REG_SET_FIELD(SYSTIMER_STEP_REG, SYSTIMER_TIMER_PLL_STEP, step)) -#define SETTING_STEP_FOR_XTAL_SRC(step) (REG_SET_FIELD(SYSTIMER_STEP_REG, SYSTIMER_TIMER_XTAL_STEP, step)) -#define UPDATE_COUNT_REG() (REG_WRITE(SYSTIMER_UPDATE_REG, SYSTIMER_TIMER_UPDATE)) -#define GET_FLAG_UPDATED_COUNT_REG() (REG_GET_BIT(SYSTIMER_UPDATE_REG, SYSTIMER_TIMER_VALUE_VALID)) - -/* Helper type to convert between a 64-bit value and a pair of 32-bit values without shifts and masks */ -typedef struct { - union { - struct { - uint32_t lo; - uint32_t hi; - }; - uint64_t val; - }; -} timer_64b_reg_t; - -static const char* TAG = "esp_timer_impl"; +static const char *TAG = "esp_timer_systimer"; /* Interrupt handle returned by the interrupt allocator */ static intr_handle_t s_timer_interrupt_handle; @@ -78,13 +45,9 @@ static intr_handle_t s_timer_interrupt_handle; */ static intr_handler_t s_alarm_handler; -/* Number of timer ticks per microsecond. */ -#define TICKS_PER_US (APB_CLK_FREQ / 1000000) - /* Spinlock used to protect access to the hardware registers. */ portMUX_TYPE s_time_update_lock = portMUX_INITIALIZER_UNLOCKED; - void esp_timer_impl_lock(void) { portENTER_CRITICAL(&s_time_update_lock); @@ -97,134 +60,89 @@ void esp_timer_impl_unlock(void) uint64_t IRAM_ATTR esp_timer_impl_get_counter_reg(void) { - uint32_t lo, lo_start, hi; - /* Set the "update" bit and wait for acknowledgment */ - UPDATE_COUNT_REG(); - while (GET_FLAG_UPDATED_COUNT_REG() == 0) { - ; - } - /* Read LO, HI, then LO again, check that LO returns the same value. - * This accounts for the case when an interrupt may happen between reading - * HI and LO values, and this function may get called from the ISR. - * In this case, the repeated read will return consistent values. - */ - lo_start = REG_READ(COUNT_LO_REG); - do { - lo = lo_start; - hi = REG_READ(COUNT_HI_REG); - lo_start = REG_READ(COUNT_LO_REG); - } while (lo_start != lo); - - timer_64b_reg_t result = { - .lo = lo, - .hi = hi - }; - return result.val; + return systimer_hal_get_counter_value(SYSTIMER_COUNTER_0); } uint64_t IRAM_ATTR esp_timer_impl_get_time(void) { - return esp_timer_impl_get_counter_reg() / TICKS_PER_US; + return systimer_hal_get_time(SYSTIMER_COUNTER_0); } void IRAM_ATTR esp_timer_impl_set_alarm(uint64_t timestamp) { portENTER_CRITICAL_SAFE(&s_time_update_lock); - int64_t offset = TICKS_PER_US * 2; - uint64_t now_time = esp_timer_impl_get_counter_reg(); - timer_64b_reg_t alarm = { .val = MAX(timestamp * TICKS_PER_US, now_time + offset) }; - do { - DISABLE_COMPARE_UNIT(); - REG_WRITE(ALARM_LO_REG, alarm.lo); - REG_WRITE(ALARM_HI_REG, alarm.hi); - ENABLE_COMPARE_UNIT(); - now_time = esp_timer_impl_get_counter_reg(); - int64_t delta = (int64_t)alarm.val - (int64_t)now_time; - if (delta <= 0 && GET_INT_FLAG() == 0) { - // new alarm is less than the counter and the interrupt flag is not set - offset += abs((int)delta) + TICKS_PER_US * 2; - alarm.val = now_time + offset; - } else { - // finish if either (alarm > counter) or the interrupt flag is already set. - break; - } - } while(1); + systimer_hal_set_alarm_value(SYSTIMER_ALARM_2, timestamp); portEXIT_CRITICAL_SAFE(&s_time_update_lock); } static void IRAM_ATTR timer_alarm_isr(void *arg) { // clear the interrupt - CLEAR_INT(); + systimer_ll_clear_alarm_int(SYSTIMER_ALARM_2); /* Call the upper layer handler */ (*s_alarm_handler)(arg); } void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us) { - /* If this function was called when switching APB clock to PLL, don't need - * do anything: the SYSTIMER_TIMER_PLL_STEP is already correct. - * If this was called when switching APB clock to XTAL, need to adjust - * XTAL_STEP value accordingly. - */ - if (apb_ticks_per_us != TICKS_PER_US) { - assert((TICKS_PER_US % apb_ticks_per_us) == 0 && "TICK_PER_US should be divisible by APB frequency (in MHz)"); - SETTING_STEP_FOR_XTAL_SRC(TICKS_PER_US / apb_ticks_per_us); - } + systimer_hal_on_apb_freq_update(apb_ticks_per_us); } void esp_timer_impl_advance(int64_t time_us) { portENTER_CRITICAL_SAFE(&s_time_update_lock); - timer_64b_reg_t new_count = { .val = esp_timer_impl_get_counter_reg() + time_us * TICKS_PER_US }; - REG_WRITE(LOAD_LO_REG, new_count.lo); - REG_WRITE(LOAD_HI_REG, new_count.hi); - APPLY_LOADED_VAL(); + systimer_hal_counter_value_advance(SYSTIMER_COUNTER_0, time_us); portEXIT_CRITICAL_SAFE(&s_time_update_lock); } esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler) { s_alarm_handler = alarm_handler; - - esp_err_t err = esp_intr_alloc(INTR_SOURCE_LACT, - ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_EDGE, - &timer_alarm_isr, NULL, &s_timer_interrupt_handle); + esp_err_t err = esp_intr_alloc(ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, + ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_EDGE, + &timer_alarm_isr, NULL, &s_timer_interrupt_handle); if (err != ESP_OK) { - ESP_EARLY_LOGE(TAG, "esp_intr_alloc failed (0x%0x)", err); - return err; + ESP_EARLY_LOGE(TAG, "esp_intr_alloc failed (%#x)", err); + goto err_intr_alloc; } - ENABLE_CLK(); - /* Configure the counter: - * - increment by 1 when running from PLL (80 ticks per microsecond), - * - increment by 2 when running from XTAL (40 ticks per microsecond). - * Note that if the APB frequency is derived from XTAL with divider != 1, - * XTAL_STEP needs to be adjusted accordingly. For example, if - * the APB frequency is XTAL/4 = 10 MHz, then XTAL_STEP should be set to 8. - * This is handled in esp_timer_impl_update_apb_freq function above. - */ - assert(rtc_clk_xtal_freq_get() == 40 && TICKS_PER_US == 80 - && "update the following code to support other XTAL:APB frequency ratios"); - SETTING_STEP_FOR_PLL_SRC(1); - SETTING_STEP_FOR_XTAL_SRC(2); + + systimer_hal_enable_counter(SYSTIMER_COUNTER_0); + systimer_hal_init(); + systimer_hal_select_alarm_mode(SYSTIMER_ALARM_2, SYSTIMER_ALARM_MODE_ONESHOT); + /* TODO: if SYSTIMER is used for anything else, access to SYSTIMER_INT_ENA_REG has to be - * protected by a shared spinlock. Since this code runs as part of early startup, this - * is practically not an issue. Same applies to SYSTIMER_CLK_EN above. - */ - ENABLE_INT(); - ESP_ERROR_CHECK(esp_intr_enable(s_timer_interrupt_handle)); + * protected by a shared spinlock. Since this code runs as part of early startup, this + * is practically not an issue. + */ + systimer_hal_enable_alarm_int(SYSTIMER_ALARM_2); + + err = esp_intr_enable(s_timer_interrupt_handle); + if (err != ESP_OK) { + ESP_EARLY_LOGE(TAG, "esp_intr_enable failed (%#x)", err); + goto err_intr_en; + } return ESP_OK; + +err_intr_en: + systimer_ll_disable_alarm(SYSTIMER_ALARM_2); + /* TODO: may need a spinlock, see the note related to SYSTIMER_INT_ENA_REG in systimer_hal_init */ + systimer_ll_disable_alarm_int(SYSTIMER_ALARM_2); + esp_intr_free(s_timer_interrupt_handle); +err_intr_alloc: + s_alarm_handler = NULL; + return err; } void esp_timer_impl_deinit(void) { esp_intr_disable(s_timer_interrupt_handle); - DISABLE_COMPARE_UNIT(); - /* TODO: may need a spinlock, see the note related to SYSTIMER_INT_ENA_REG in esp_timer_impl_init */ - DISABLE_INT(); + systimer_ll_disable_alarm(SYSTIMER_ALARM_2); + /* TODO: may need a spinlock, see the note related to SYSTIMER_INT_ENA_REG in systimer_hal_init */ + systimer_ll_disable_alarm_int(SYSTIMER_ALARM_2); esp_intr_free(s_timer_interrupt_handle); s_timer_interrupt_handle = NULL; + s_alarm_handler = NULL; } uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us(void) @@ -235,12 +153,9 @@ uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us(void) uint64_t esp_timer_impl_get_alarm_reg(void) { portENTER_CRITICAL_SAFE(&s_time_update_lock); - timer_64b_reg_t alarm = { - .lo = REG_READ(ALARM_LO_REG), - .hi = REG_READ(ALARM_HI_REG) - }; + uint64_t val = systimer_hal_get_alarm_value(SYSTIMER_ALARM_2); portEXIT_CRITICAL_SAFE(&s_time_update_lock); - return alarm.val; + return val; } void esp_timer_private_update_apb_freq(uint32_t apb_ticks_per_us) __attribute__((alias("esp_timer_impl_update_apb_freq"))); diff --git a/components/soc/include/hal/systimer_hal.h b/components/soc/include/hal/systimer_hal.h new file mode 100644 index 000000000..a26ffdde3 --- /dev/null +++ b/components/soc/include/hal/systimer_hal.h @@ -0,0 +1,76 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "hal/systimer_types.h" + +/** + * @brief enable systimer counter + */ +void systimer_hal_enable_counter(systimer_counter_id_t counter_id); + +/** + * @brief get current counter value + */ +uint64_t systimer_hal_get_counter_value(systimer_counter_id_t counter_id); + +/** + * @brief get current time (in microseconds) + */ +uint64_t systimer_hal_get_time(systimer_counter_id_t counter_id); + +/** + * @brief set alarm time + */ +void systimer_hal_set_alarm_value(systimer_alarm_id_t alarm_id, uint64_t timestamp); + +/** + * @brief get alarm time + */ +uint64_t systimer_hal_get_alarm_value(systimer_alarm_id_t alarm_id); + +/** + * @brief enable alarm interrupt + */ +void systimer_hal_enable_alarm_int(systimer_alarm_id_t alarm_id); + +/** + * @brief select alarm mode + */ +void systimer_hal_select_alarm_mode(systimer_alarm_id_t alarm_id, systimer_alarm_mode_t mode); + +/** + * @brief update systimer step when apb clock gets changed + */ +void systimer_hal_on_apb_freq_update(uint32_t apb_ticks_per_us); + +/** + * @brief move systimer counter value forward or backward + */ +void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_t time_us); + +/** + * @brief initialize systimer in HAL layer + */ +void systimer_hal_init(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/include/hal/systimer_types.h b/components/soc/include/hal/systimer_types.h new file mode 100644 index 000000000..ebe5fb4e1 --- /dev/null +++ b/components/soc/include/hal/systimer_types.h @@ -0,0 +1,74 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "soc/systimer_caps.h" + +/* + * @brief The structure of the counter value in systimer + * + */ +typedef struct { + union { + struct { + uint64_t lo : SOC_SYSTIMER_BIT_WIDTH_LO; /*!< Low part of counter value */ + uint64_t hi : SOC_SYSTIMER_BIT_WIDTH_HI; /*!< High part of counter value */ + }; + uint64_t val; /*!< counter value */ + }; +} systimer_counter_value_t; + +/** @cond */ +_Static_assert(sizeof(systimer_counter_value_t) == 8, "systimer_counter_value_t should occupy 8 bytes in memory"); +/** @endcond */ + +/** + * @brief systimer counter ID + * + */ +typedef enum { + SYSTIMER_COUNTER_0, /*!< systimer counter 0 */ +#if SOC_SYSTIMER_COUNTER_NUM > 1 + SYSTIEMR_COUNTER_1, /*!< systimer counter 1 */ +#endif +} systimer_counter_id_t; + +/** + * @brief systimer alarm ID + * + */ +typedef enum { + SYSTIMER_ALARM_0, /*!< systimer alarm 0 */ + SYSTIMER_ALARM_1, /*!< systimer alarm 1 */ + SYSTIMER_ALARM_2, /*!< systimer alarm 2 */ +} systimer_alarm_id_t; + +/** + * @brief systimer alarm mode + * + */ +typedef enum { + SYSTIMER_ALARM_MODE_ONESHOT, /*!< systimer alarm oneshot mode */ + SYSTIMER_ALARM_MODE_PERIOD, /*!< systimer alarm period mode */ +} systimer_alarm_mode_t; + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/components/soc/linker.lf b/components/soc/linker.lf index c943d6008..464d335d7 100644 --- a/components/soc/linker.lf +++ b/components/soc/linker.lf @@ -24,3 +24,4 @@ entries: cpu_hal (noflash) soc_hal (noflash) wdt_hal_iram (noflash) + systimer_hal (noflash) diff --git a/components/soc/soc/esp32s2/include/soc/systimer_caps.h b/components/soc/soc/esp32s2/include/soc/systimer_caps.h new file mode 100644 index 000000000..ca670c2e2 --- /dev/null +++ b/components/soc/soc/esp32s2/include/soc/systimer_caps.h @@ -0,0 +1,21 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units + +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part diff --git a/components/soc/src/esp32s2/CMakeLists.txt b/components/soc/src/esp32s2/CMakeLists.txt index 0321c6ec0..a00b82167 100644 --- a/components/soc/src/esp32s2/CMakeLists.txt +++ b/components/soc/src/esp32s2/CMakeLists.txt @@ -6,6 +6,7 @@ set(srcs "brownout_hal.c" "rtc_sleep.c" "rtc_time.c" "soc_memory_layout.c" + "systimer_hal.c" "touch_sensor_hal.c" "usb_hal.c") diff --git a/components/soc/src/esp32s2/include/hal/systimer_ll.h b/components/soc/src/esp32s2/include/hal/systimer_ll.h new file mode 100644 index 000000000..752ad2dd2 --- /dev/null +++ b/components/soc/src/esp32s2/include/hal/systimer_ll.h @@ -0,0 +1,138 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "soc/soc.h" +#include "soc/systimer_reg.h" + +// All these functions get invoked either from ISR or HAL that linked to IRAM. +// Always inline these functions even no gcc optimization is applied. + +/*******************counter*************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_clock(void) +{ + REG_SET_BIT(SYSTIMER_CONF_REG, SYSTIMER_CLK_EN); +} + +__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(void) +{ + REG_SET_BIT(SYSTIMER_LOAD_REG, SYSTIMER_TIMER_LOAD); +} + +__attribute__((always_inline)) static inline void systimer_ll_load_counter_value(uint64_t value) +{ + REG_WRITE(SYSTIMER_LOAD_LO_REG, value & 0xFFFFFFFF); + REG_WRITE(SYSTIMER_LOAD_HI_REG, (value & 0xFFFFFFFF00000000) >> 32); +} + +__attribute__((always_inline)) static inline void systimer_ll_set_step_for_pll(uint32_t step) +{ + REG_SET_FIELD(SYSTIMER_STEP_REG, SYSTIMER_TIMER_PLL_STEP, step); +} + +__attribute__((always_inline)) static inline void systimer_ll_set_step_for_xtal(uint32_t step) +{ + REG_SET_FIELD(SYSTIMER_STEP_REG, SYSTIMER_TIMER_XTAL_STEP, step); +} + +__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(void) +{ + REG_WRITE(SYSTIMER_UPDATE_REG, SYSTIMER_TIMER_UPDATE); +} + +__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(void) +{ + return REG_GET_BIT(SYSTIMER_UPDATE_REG, SYSTIMER_TIMER_VALUE_VALID); +} + +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(void) +{ + return REG_READ(SYSTIMER_VALUE_LO_REG); +} + +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(void) +{ + return REG_READ(SYSTIMER_VALUE_HI_REG); +} + +/*******************alarm*************************/ + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_value(uint32_t alarm_id, uint64_t value) +{ + REG_WRITE(SYSTIMER_TARGET0_LO_REG + alarm_id * 8, value & 0xFFFFFFFF); + REG_WRITE(SYSTIMER_TARGET0_HI_REG + alarm_id * 8, (value & 0xFFFFFFFF00000000) >> 32); +} + +__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_value(uint32_t alarm_id) +{ + return (uint64_t)REG_READ(SYSTIMER_TARGET0_HI_REG + alarm_id * 8) << 32 | REG_READ(SYSTIMER_TARGET0_LO_REG + alarm_id * 8); +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(uint32_t alarm_id) +{ + REG_SET_BIT(SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, BIT(31)); +} + +__attribute__((always_inline)) static inline void systimer_ll_disable_alarm(uint32_t alarm_id) +{ + REG_CLR_BIT(SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, BIT(31)); +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(uint32_t alarm_id) +{ + REG_CLR_BIT(SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, BIT(30)); +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(uint32_t alarm_id) +{ + REG_SET_BIT(SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, BIT(30)); +} + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(uint32_t alarm_id, uint32_t period) +{ + REG_SET_FIELD(SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYSTIMER_TARGET0_PERIOD, period); +} + +/*******************interrupt*************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(uint32_t alarm_id) +{ + REG_SET_BIT(SYSTIMER_INT_ENA_REG, 1 << alarm_id); +} + +__attribute__((always_inline)) static inline void systimer_ll_disable_alarm_int(uint32_t alarm_id) +{ + REG_CLR_BIT(SYSTIMER_INT_ENA_REG, 1 << alarm_id); +} + +__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(uint32_t alarm_id) +{ + return REG_GET_BIT(SYSTIMER_INT_RAW_REG, 1 << alarm_id); +} + +__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(uint32_t alarm_id) +{ + REG_SET_BIT(SYSTIMER_INT_CLR_REG, 1 << alarm_id); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/src/esp32s2/systimer_hal.c b/components/soc/src/esp32s2/systimer_hal.c new file mode 100644 index 000000000..71af0895c --- /dev/null +++ b/components/soc/src/esp32s2/systimer_hal.c @@ -0,0 +1,140 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include "hal/systimer_hal.h" +#include "hal/systimer_ll.h" +#include "hal/systimer_types.h" +#include "soc/systimer_caps.h" +#include "soc/rtc.h" + +#define SYSTIMER_TICKS_PER_US (80) // Number of timer ticks per microsecond + +uint64_t systimer_hal_get_counter_value(systimer_counter_id_t counter_id) +{ + uint32_t lo, lo_start, hi; + /* Set the "update" bit and wait for acknowledgment */ + systimer_ll_counter_snapshot(); + while (!systimer_ll_is_counter_value_valid()); + /* Read LO, HI, then LO again, check that LO returns the same value. + * This accounts for the case when an interrupt may happen between reading + * HI and LO values, and this function may get called from the ISR. + * In this case, the repeated read will return consistent values. + */ + lo_start = systimer_ll_get_counter_value_low(); + do { + lo = lo_start; + hi = systimer_ll_get_counter_value_high(); + lo_start = systimer_ll_get_counter_value_low(); + } while (lo_start != lo); + + systimer_counter_value_t result = { + .lo = lo, + .hi = hi + }; + + return result.val; +} + +uint64_t systimer_hal_get_time(systimer_counter_id_t counter_id) +{ + return systimer_hal_get_counter_value(counter_id) / SYSTIMER_TICKS_PER_US; +} + +void systimer_hal_set_alarm_value(systimer_alarm_id_t alarm_id, uint64_t timestamp) +{ + int64_t offset = SYSTIMER_TICKS_PER_US * 2; + uint64_t now_time = systimer_hal_get_counter_value(SYSTIMER_COUNTER_0); + systimer_counter_value_t alarm = { .val = MAX(timestamp * SYSTIMER_TICKS_PER_US, now_time + offset) }; + do { + systimer_ll_disable_alarm(alarm_id); + systimer_ll_set_alarm_value(alarm_id, alarm.val); + systimer_ll_enable_alarm(alarm_id); + now_time = systimer_hal_get_counter_value(SYSTIMER_COUNTER_0); + int64_t delta = (int64_t)alarm.val - (int64_t)now_time; + if (delta <= 0 && !systimer_ll_is_alarm_int_fired(alarm_id)) { + // new alarm is less than the counter and the interrupt flag is not set + offset += -1 * delta + SYSTIMER_TICKS_PER_US * 2; + alarm.val = now_time + offset; + } else { + // finish if either (alarm > counter) or the interrupt flag is already set. + break; + } + } while (1); +} + +uint64_t systimer_hal_get_alarm_value(systimer_alarm_id_t alarm_id) +{ + return systimer_ll_get_alarm_value(alarm_id); +} + +void systimer_hal_enable_alarm_int(systimer_alarm_id_t alarm_id) +{ + systimer_ll_enable_alarm_int(alarm_id); +} + +void systimer_hal_on_apb_freq_update(uint32_t apb_ticks_per_us) +{ + /* If this function was called when switching APB clock to PLL, don't need + * do anything: the SYSTIMER_TIMER_PLL_STEP is already correct. + * If this was called when switching APB clock to XTAL, need to adjust + * XTAL_STEP value accordingly. + */ + if (apb_ticks_per_us != SYSTIMER_TICKS_PER_US) { + assert((SYSTIMER_TICKS_PER_US % apb_ticks_per_us) == 0 && "TICK_PER_US should be divisible by APB frequency (in MHz)"); + systimer_ll_set_step_for_xtal(SYSTIMER_TICKS_PER_US / apb_ticks_per_us); + } +} + +void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_t time_us) +{ + systimer_counter_value_t new_count = { .val = systimer_hal_get_counter_value(counter_id) + time_us * SYSTIMER_TICKS_PER_US }; + systimer_ll_load_counter_value(new_count.val); + systimer_ll_apply_counter_value(); +} + +void systimer_hal_enable_counter(systimer_counter_id_t counter_id) +{ + systimer_ll_enable_clock(); +} + +void systimer_hal_init(void) +{ + assert(rtc_clk_xtal_freq_get() == 40 && "update the step for xtal to support other XTAL:APB frequency ratios"); + /* Configure the counter: + * - increment by 1 when running from PLL (80 ticks per microsecond), + * - increment by 2 when running from XTAL (40 ticks per microsecond). + * Note that if the APB frequency is derived from XTAL with divider != 1, + * XTAL_STEP needs to be adjusted accordingly. For example, if + * the APB frequency is XTAL/4 = 10 MHz, then XTAL_STEP should be set to 8. + * This is handled in systimer_hal_on_apb_freq_update function. + */ + systimer_ll_set_step_for_pll(1); + systimer_ll_set_step_for_xtal(2); +} + +void systimer_hal_select_alarm_mode(systimer_alarm_id_t alarm_id, systimer_alarm_mode_t mode) +{ + switch (mode) { + case SYSTIMER_ALARM_MODE_ONESHOT: + systimer_ll_enable_alarm_oneshot(alarm_id); + break; + case SYSTIMER_ALARM_MODE_PERIOD: + systimer_ll_enable_alarm_period(alarm_id); + break; + default: + break; + } +}