diff --git a/components/driver/gpio.c b/components/driver/gpio.c index bff943e43..22095cd3b 100644 --- a/components/driver/gpio.c +++ b/components/driver/gpio.c @@ -42,44 +42,60 @@ static portMUX_TYPE gpio_spinlock = portMUX_INITIALIZER_UNLOCKED; esp_err_t gpio_pullup_en(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); +#if CONFIG_IDF_TARGET_ESP32 if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { rtc_gpio_pullup_en(gpio_num); } else { REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +#endif return ESP_OK; } esp_err_t gpio_pullup_dis(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); +#if CONFIG_IDF_TARGET_ESP32 if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { rtc_gpio_pullup_dis(gpio_num); } else { REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +#endif return ESP_OK; } esp_err_t gpio_pulldown_en(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); +#if CONFIG_IDF_TARGET_ESP32 if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { rtc_gpio_pulldown_en(gpio_num); } else { REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +#endif return ESP_OK; } esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); +#if CONFIG_IDF_TARGET_ESP32 if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { rtc_gpio_pulldown_dis(gpio_num); } else { REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +#endif return ESP_OK; } @@ -104,11 +120,17 @@ static esp_err_t gpio_intr_enable_on_core (gpio_num_t gpio_num, uint32_t core_id { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); gpio_intr_status_clr(gpio_num); +#if CONFIG_IDF_TARGET_ESP32 if (core_id == 0) { GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr } else { GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + if (core_id == 0) { + GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr + } +#endif return ESP_OK; } @@ -255,6 +277,7 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig) ESP_LOGE(GPIO_TAG, "GPIO_PIN mask error "); return ESP_ERR_INVALID_ARG; } +#if CONFIG_IDF_TARGET_ESP32 if ((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) { //GPIO 34/35/36/37/38/39 can only be used as input mode; if ((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) { @@ -262,6 +285,12 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig) return ESP_ERR_INVALID_ARG; } } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + if ( (pGPIOConfig->mode & GPIO_MODE_DEF_OUTPUT) && (gpio_pin_mask & GPIO_SEL_46) ) { + ESP_LOGE(GPIO_TAG, "GPIO46 can only be used as input mode"); + return ESP_ERR_INVALID_ARG; + } +#endif do { io_reg = GPIO_PIN_MUX_REG[io_num]; if (((gpio_pin_mask >> io_num) & BIT(0))) { @@ -456,12 +485,15 @@ esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t streng { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); GPIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG); - +#if CONFIG_IDF_TARGET_ESP32 if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { rtc_gpio_set_drive_capability(gpio_num, strength); } else { SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); +#endif return ESP_OK; } @@ -469,15 +501,19 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* stren { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); GPIO_CHECK(strength != NULL, "GPIO drive capability pointer error", ESP_ERR_INVALID_ARG); - +#if CONFIG_IDF_TARGET_ESP32 if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { return rtc_gpio_get_drive_capability(gpio_num, strength); } else { *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); +#endif return ESP_OK; } +#if CONFIG_IDF_TARGET_ESP32 static const uint32_t GPIO_HOLD_MASK[34] = { 0, GPIO_SEL_1, @@ -514,6 +550,7 @@ static const uint32_t GPIO_HOLD_MASK[34] = { 0, 0, }; +#endif esp_err_t gpio_hold_en(gpio_num_t gpio_num) { @@ -521,15 +558,17 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num) esp_err_t r = ESP_OK; if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { r = rtc_gpio_hold_en(gpio_num); - } else if (GPIO_HOLD_MASK[gpio_num]) { #if CONFIG_IDF_TARGET_ESP32 + } else if (GPIO_HOLD_MASK[gpio_num]) { SET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); -#endif } else { r = ESP_ERR_NOT_SUPPORTED; } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + } else { + SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - RTC_GPIO_NUMBER)); + } +#endif return r == ESP_OK ? ESP_OK : ESP_ERR_NOT_SUPPORTED; } @@ -539,15 +578,17 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num) esp_err_t r = ESP_OK; if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { r = rtc_gpio_hold_dis(gpio_num); - } else if (GPIO_HOLD_MASK[gpio_num]) { -#if CONFIG_IDF_TARGET_ESP32 +#if CONFIG_IDF_TARGET_ESP32 + }else if (GPIO_HOLD_MASK[gpio_num]) { CLEAR_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); -#endif } else { r = ESP_ERR_NOT_SUPPORTED; } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - RTC_GPIO_NUMBER)); + } +#endif return r == ESP_OK ? ESP_OK : ESP_ERR_NOT_SUPPORTED; } @@ -561,10 +602,35 @@ void gpio_deep_sleep_hold_en(void) void gpio_deep_sleep_hold_dis(void) { portENTER_CRITICAL(&gpio_spinlock); +#if CONFIG_IDF_TARGET_ESP32 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); +#endif portEXIT_CRITICAL(&gpio_spinlock); } +#if CONFIG_IDF_TARGET_ESP32S2BETA + +esp_err_t gpio_force_hold_all() +{ + rtc_gpio_force_hold_all(); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); + return ESP_OK; +} + +esp_err_t gpio_force_unhold_all() +{ + rtc_gpio_force_hold_dis_all(); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); + return ESP_OK; +} + +#endif + void gpio_iomux_in(uint32_t gpio, uint32_t signal_idx) { GPIO.func_in_sel_cfg[signal_idx].sig_in_sel = 0; diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h index 6d7171b18..fc746bbc1 100644 --- a/components/driver/include/driver/gpio.h +++ b/components/driver/include/driver/gpio.h @@ -32,6 +32,7 @@ extern "C" { #endif +#if CONFIG_IDF_TARGET_ESP32 #define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */ #define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */ #define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected @@ -76,6 +77,53 @@ extern "C" { #define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /*!< Pin 38 selected */ #define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /*!< Pin 39 selected */ +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */ +#define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */ +#define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected */ +#define GPIO_SEL_3 (BIT(3)) /*!< Pin 3 selected */ +#define GPIO_SEL_4 (BIT(4)) /*!< Pin 4 selected */ +#define GPIO_SEL_5 (BIT(5)) /*!< Pin 5 selected */ +#define GPIO_SEL_6 (BIT(6)) /*!< Pin 6 selected */ +#define GPIO_SEL_7 (BIT(7)) /*!< Pin 7 selected */ +#define GPIO_SEL_8 (BIT(8)) /*!< Pin 8 selected */ +#define GPIO_SEL_9 (BIT(9)) /*!< Pin 9 selected */ +#define GPIO_SEL_10 (BIT(10)) /*!< Pin 10 selected */ +#define GPIO_SEL_11 (BIT(11)) /*!< Pin 11 selected */ +#define GPIO_SEL_12 (BIT(12)) /*!< Pin 12 selected */ +#define GPIO_SEL_13 (BIT(13)) /*!< Pin 13 selected */ +#define GPIO_SEL_14 (BIT(14)) /*!< Pin 14 selected */ +#define GPIO_SEL_15 (BIT(15)) /*!< Pin 15 selected */ +#define GPIO_SEL_16 (BIT(16)) /*!< Pin 16 selected */ +#define GPIO_SEL_17 (BIT(17)) /*!< Pin 17 selected */ +#define GPIO_SEL_18 (BIT(18)) /*!< Pin 18 selected */ +#define GPIO_SEL_19 (BIT(19)) /*!< Pin 19 selected */ +#define GPIO_SEL_20 (BIT(20)) /*!< Pin 20 selected */ +#define GPIO_SEL_21 (BIT(21)) /*!< Pin 21 selected */ + +#define GPIO_SEL_26 (BIT(26)) /*!< Pin 26 selected */ +#define GPIO_SEL_27 (BIT(27)) /*!< Pin 27 selected */ +#define GPIO_SEL_28 (BIT(28)) /*!< Pin 28 selected */ +#define GPIO_SEL_29 (BIT(29)) /*!< Pin 29 selected */ +#define GPIO_SEL_30 (BIT(30)) /*!< Pin 30 selected */ +#define GPIO_SEL_31 (BIT(31)) /*!< Pin 31 selected */ +#define GPIO_SEL_32 ((uint64_t)(((uint64_t)1)<<32)) /*!< Pin 32 selected */ +#define GPIO_SEL_33 ((uint64_t)(((uint64_t)1)<<33)) /*!< Pin 33 selected */ +#define GPIO_SEL_34 ((uint64_t)(((uint64_t)1)<<34)) /*!< Pin 34 selected */ +#define GPIO_SEL_35 ((uint64_t)(((uint64_t)1)<<35)) /*!< Pin 35 selected */ +#define GPIO_SEL_36 ((uint64_t)(((uint64_t)1)<<36)) /*!< Pin 36 selected */ +#define GPIO_SEL_37 ((uint64_t)(((uint64_t)1)<<37)) /*!< Pin 37 selected */ +#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /*!< Pin 38 selected */ +#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /*!< Pin 39 selected */ +#define GPIO_SEL_40 ((uint64_t)(((uint64_t)1)<<40)) /*!< Pin 40 selected */ +#define GPIO_SEL_41 ((uint64_t)(((uint64_t)1)<<41)) /*!< Pin 41 selected */ +#define GPIO_SEL_42 ((uint64_t)(((uint64_t)1)<<42)) /*!< Pin 42 selected */ +#define GPIO_SEL_43 ((uint64_t)(((uint64_t)1)<<43)) /*!< Pin 43 selected */ +#define GPIO_SEL_44 ((uint64_t)(((uint64_t)1)<<44)) /*!< Pin 44 selected */ +#define GPIO_SEL_45 ((uint64_t)(((uint64_t)1)<<45)) /*!< Pin 45 selected */ +#define GPIO_SEL_46 ((uint64_t)(((uint64_t)1)<<46)) /*!< Pin 46 selected */ +#endif + #if CONFIG_IDF_TARGET_ESP32 #define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG #define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG @@ -163,11 +211,16 @@ extern "C" { #define GPIO_PIN_REG_47 IO_MUX_GPIO47_REG #endif +#if CONFIG_IDF_TARGET_ESP32 #define GPIO_APP_CPU_INTR_ENA (BIT(0)) #define GPIO_APP_CPU_NMI_INTR_ENA (BIT(1)) #define GPIO_PRO_CPU_INTR_ENA (BIT(2)) #define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(3)) #define GPIO_SDIO_EXT_INTR_ENA (BIT(4)) +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#define GPIO_PRO_CPU_INTR_ENA (BIT(0)) +#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(1)) +#endif #define GPIO_MODE_DEF_DISABLE (0) #define GPIO_MODE_DEF_INPUT (BIT0) @@ -184,6 +237,7 @@ extern "C" { #define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */ #endif +#if CONFIG_IDF_TARGET_ESP32 typedef enum { GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ @@ -228,22 +282,60 @@ typedef enum { GPIO_NUM_37 = 37, /*!< GPIO37, input mode only */ GPIO_NUM_38 = 38, /*!< GPIO38, input mode only */ GPIO_NUM_39 = 39, /*!< GPIO39, input mode only */ -#if CONFIG_IDF_TARGET_ESP32 GPIO_NUM_MAX = 40, -#elif CONFIG_IDF_TARGET_ESP32S2BETA - GPIO_NUM_40 = 40, /*!< GPIO40, input mode only */ - GPIO_NUM_41 = 41, /*!< GPIO41, input mode only */ - GPIO_NUM_42 = 42, /*!< GPIO42, input mode only */ - GPIO_NUM_43 = 43, /*!< GPIO43, input mode only */ - GPIO_NUM_44 = 44, /*!< GPIO44, input mode only */ - GPIO_NUM_45 = 45, /*!< GPIO45, input mode only */ - GPIO_NUM_46 = 46, /*!< GPIO46, input mode only */ - GPIO_NUM_47 = 47, /*!< GPIO47, input mode only */ - GPIO_NUM_MAX = 48, -#endif /** @endcond */ } gpio_num_t; + +#elif CONFIG_IDF_TARGET_ESP32S2BETA +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + /* Note: The missing IO is because it is used inside the chip. */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ + GPIO_NUM_32 = 32, /*!< GPIO32, input and output */ + GPIO_NUM_33 = 33, /*!< GPIO33, input and output */ + GPIO_NUM_34 = 34, /*!< GPIO34, input and output */ + GPIO_NUM_35 = 35, /*!< GPIO35, input and output */ + GPIO_NUM_36 = 36, /*!< GPIO36, input and output */ + GPIO_NUM_37 = 37, /*!< GPIO37, input and output */ + GPIO_NUM_38 = 38, /*!< GPIO38, input and output */ + GPIO_NUM_39 = 39, /*!< GPIO39, input and output */ + GPIO_NUM_40 = 40, /*!< GPIO40, input and output */ + GPIO_NUM_41 = 41, /*!< GPIO41, input and output */ + GPIO_NUM_42 = 42, /*!< GPIO42, input and output */ + GPIO_NUM_43 = 43, /*!< GPIO43, input and output */ + GPIO_NUM_44 = 44, /*!< GPIO44, input and output */ + GPIO_NUM_45 = 45, /*!< GPIO45, input and output */ + GPIO_NUM_46 = 46, /*!< GPIO46, input mode only */ + GPIO_NUM_MAX = 47, +/** @endcond */ +} gpio_num_t; +#endif + typedef enum { GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */ GPIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */ @@ -680,6 +772,20 @@ void gpio_iomux_in(uint32_t gpio_num, uint32_t signal_idx); */ void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv); +#if CONFIG_IDF_TARGET_ESP32S2BETA +/** + * @brief Force hold digital and rtc gpio pad. + * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. + * */ +esp_err_t gpio_force_hold_all(void); + +/** + * @brief Force unhold digital and rtc gpio pad. + * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. + * */ +esp_err_t gpio_force_unhold_all(void); +#endif + #ifdef __cplusplus } #endif diff --git a/components/driver/include/driver/rtc_io.h b/components/driver/include/driver/rtc_io.h index c636f61cc..53ca2b566 100644 --- a/components/driver/include/driver/rtc_io.h +++ b/components/driver/include/driver/rtc_io.h @@ -24,12 +24,19 @@ extern "C" { #endif typedef enum { - RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad input */ - RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad output */ + RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad input */ + RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad output */ RTC_GPIO_MODE_INPUT_OUTPUT, /*!< Pad pull input + output */ - RTC_GPIO_MODE_DISABLED, /*!< Pad (output + input) disable */ + RTC_GPIO_MODE_DISABLED, /*!< Pad (output + input) disable */ } rtc_gpio_mode_t; +#if CONFIG_IDF_TARGET_ESP32S2BETA +typedef enum { + RTCIO_MODE_OUTPUT = 0, /*!< Pad output normal mode */ + RTCIO_MODE_OUTPUT_OD = 1, /*!< Pad output OD mode */ +} rtc_io_out_mode_t; +#endif + /** * @brief Determine if the specified GPIO is a valid RTC GPIO. * @@ -38,8 +45,12 @@ typedef enum { */ inline static bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num) { +#if CONFIG_IDF_TARGET_ESP32 return gpio_num < GPIO_PIN_COUNT && rtc_gpio_desc[gpio_num].reg != 0; +#elif CONFIG_IDF_TARGET_ESP32S2BETA + return (gpio_num < RTC_GPIO_NUMBER); +#endif } #define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num) // Deprecated, use rtc_gpio_is_valid_gpio() @@ -266,7 +277,71 @@ esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) */ esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num); +#if CONFIG_IDF_TARGET_ESP32S2BETA +/** + * @brief RTC IO set output mode + * @param gpio_num Configure GPIO pins number + * @param mode GPIO output mode + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG GPIO error + * + */ +esp_err_t rtc_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode); +/** + * @brief RTC IO get output mode + * @param gpio_num Configure GPIO pins number + * @param mode GPIO output mode + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG GPIO error + */ +esp_err_t rtc_gpio_get_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t *mode); + +/** + * @brief Set RTC IO status in deep sleep + * In some application scenarios, IO needs to have another states during deep sleep. + * @param gpio_num Configure GPIO pins number + * @param input input mode. false: close; true: open; + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG GPIO error + */ +esp_err_t rtc_gpio_sleep_input_enable(gpio_num_t gpio_num, bool input); + +/** + * @brief Set RTC IO status in deep sleep + * In some application scenarios, IO needs to have another states during deep sleep. + * @param gpio_num Configure GPIO pins number + * @param output output mode. false: close; true: open; + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG GPIO error + */ +esp_err_t rtc_gpio_sleep_output_enable(gpio_num_t gpio_num, bool output); + +/** + * @brief Close RTC IO status in deep sleep + * In some application scenarios, IO needs to have another states during deep sleep. + * @param gpio_num Configure GPIO pins number + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG GPIO error + */ +esp_err_t rtc_gpio_sleep_mode_disable(gpio_num_t gpio_num); + +/** + * @brief Enable force hold signal for all RTC IOs + * + * Each RTC pad has a "force hold" input signal from the RTC controller. + * If this signal is set, pad latches current values of input enable, + * function, output enable, and other signals which come from the RTC mux. + * Force hold signal is enabled before going into deep sleep for pins which + * are used for EXT1 wakeup. + */ +esp_err_t rtc_gpio_force_hold_all(); +#endif #ifdef __cplusplus } diff --git a/components/driver/rtc_module.c b/components/driver/rtc_module.c index 71d08ffb7..2ddb4a3b4 100644 --- a/components/driver/rtc_module.c +++ b/components/driver/rtc_module.c @@ -142,10 +142,15 @@ esp_err_t rtc_gpio_init(gpio_num_t gpio_num) { RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); portENTER_CRITICAL(&rtc_spinlock); +#if CONFIG_IDF_TARGET_ESP32 // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, (rtc_gpio_desc[gpio_num].mux)); //0:RTC FUNCIOTN 1,2,3:Reserved SET_PERI_REG_BITS(rtc_gpio_desc[gpio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, 0x0, rtc_gpio_desc[gpio_num].func); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + rtc_gpio_reg[gpio_num]->mux_sel = 0x1; + rtc_gpio_reg[gpio_num]->fun_sel = 0x0; +#endif portEXIT_CRITICAL(&rtc_spinlock); return ESP_OK; @@ -156,7 +161,11 @@ esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num) RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); portENTER_CRITICAL(&rtc_spinlock); //Select Gpio as Digital Gpio +#if CONFIG_IDF_TARGET_ESP32 CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, (rtc_gpio_desc[gpio_num].mux)); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + rtc_gpio_reg[gpio_num]->mux_sel = 0x0; +#endif portEXIT_CRITICAL(&rtc_spinlock); return ESP_OK; @@ -167,8 +176,6 @@ static esp_err_t rtc_gpio_output_enable(gpio_num_t gpio_num) int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num; RTC_MODULE_CHECK(rtc_gpio_num != -1, "RTC_GPIO number error", ESP_ERR_INVALID_ARG); SET_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TS_REG, (1 << (rtc_gpio_num + RTC_GPIO_ENABLE_W1TS_S))); - CLEAR_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TC_REG, (1 << (rtc_gpio_num + RTC_GPIO_ENABLE_W1TC_S))); - return ESP_OK; } @@ -176,7 +183,6 @@ static esp_err_t rtc_gpio_output_disable(gpio_num_t gpio_num) { int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num; RTC_MODULE_CHECK(rtc_gpio_num != -1, "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - CLEAR_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TS_REG, (1 << (rtc_gpio_num + RTC_GPIO_ENABLE_W1TS_S))); SET_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TC_REG, (1 << ( rtc_gpio_num + RTC_GPIO_ENABLE_W1TC_S))); return ESP_OK; @@ -186,7 +192,11 @@ static esp_err_t rtc_gpio_input_enable(gpio_num_t gpio_num) { RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); portENTER_CRITICAL(&rtc_spinlock); +#if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].ie); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + rtc_gpio_reg[gpio_num]->fun_ie = 1; +#endif portEXIT_CRITICAL(&rtc_spinlock); return ESP_OK; @@ -196,12 +206,41 @@ static esp_err_t rtc_gpio_input_disable(gpio_num_t gpio_num) { RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); portENTER_CRITICAL(&rtc_spinlock); +#if CONFIG_IDF_TARGET_ESP32 CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].ie); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + rtc_gpio_reg[gpio_num]->fun_ie = 0; +#endif portEXIT_CRITICAL(&rtc_spinlock); return ESP_OK; } +#if CONFIG_IDF_TARGET_ESP32S2BETA +esp_err_t rtc_gpio_sleep_output_enable(gpio_num_t gpio_num, bool output) +{ + RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); + rtc_gpio_reg[gpio_num]->slp_sel = 1; + rtc_gpio_reg[gpio_num]->slp_oe = output; + return ESP_OK; +} + +esp_err_t rtc_gpio_sleep_input_enable(gpio_num_t gpio_num, bool input) +{ + RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); + rtc_gpio_reg[gpio_num]->slp_sel = 1; + rtc_gpio_reg[gpio_num]->slp_ie = input; + return ESP_OK; +} + +esp_err_t rtc_gpio_sleep_mode_disable(gpio_num_t gpio_num) +{ + RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); + rtc_gpio_reg[gpio_num]->slp_sel = 0; + return ESP_OK; +} +#endif + esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level) { int rtc_gpio_num = rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;; @@ -219,6 +258,7 @@ esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level) uint32_t rtc_gpio_get_level(gpio_num_t gpio_num) { uint32_t level = 0; +#if CONFIG_IDF_TARGET_ESP32 int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num; RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); @@ -226,6 +266,13 @@ uint32_t rtc_gpio_get_level(gpio_num_t gpio_num) level = READ_PERI_REG(RTC_GPIO_IN_REG); portEXIT_CRITICAL(&rtc_spinlock); return ((level >> (RTC_GPIO_IN_NEXT_S + rtc_gpio_num)) & 0x01); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); + portENTER_CRITICAL(&rtc_spinlock); + level = RTCIO.in_val.in; + portEXIT_CRITICAL(&rtc_spinlock); + return ((level >> gpio_num) & 0x1); +#endif } esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength) @@ -235,7 +282,11 @@ esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t st RTC_MODULE_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG); portENTER_CRITICAL(&rtc_spinlock); +#if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_BITS(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].drv_v, strength, rtc_gpio_desc[gpio_num].drv_s); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + rtc_gpio_reg[gpio_num]->drv = strength; +#endif portEXIT_CRITICAL(&rtc_spinlock); return ESP_OK; } @@ -245,8 +296,11 @@ esp_err_t rtc_gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* s RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); RTC_MODULE_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Output pad only", ESP_ERR_INVALID_ARG); RTC_MODULE_CHECK(strength != NULL, "GPIO drive pointer error", ESP_ERR_INVALID_ARG); - +#if CONFIG_IDF_TARGET_ESP32 *strength = GET_PERI_REG_BITS2(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].drv_v, rtc_gpio_desc[gpio_num].drv_s); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + *strength = rtc_gpio_reg[gpio_num]->drv; +#endif return ESP_OK; } @@ -278,21 +332,45 @@ esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode) esp_err_t rtc_gpio_pullup_en(gpio_num_t gpio_num) { +#if CONFIG_IDF_TARGET_ESP32 //this is a digital pad if (rtc_gpio_desc[gpio_num].pullup == 0) { return ESP_ERR_INVALID_ARG; } - +#endif //this is a rtc pad portENTER_CRITICAL(&rtc_spinlock); +#if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pullup); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + rtc_gpio_reg[gpio_num]->rue = 0x1; +#endif portEXIT_CRITICAL(&rtc_spinlock); return ESP_OK; } +#if CONFIG_IDF_TARGET_ESP32S2BETA +esp_err_t rtc_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode) +{ + RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); + portENTER_CRITICAL(&rtc_spinlock); + RTCIO.pin[gpio_num].pad_driver = mode; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t rtc_gpio_get_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t *mode) +{ + RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); + *mode = RTCIO.pin[gpio_num].pad_driver; + return ESP_OK; +} +#endif + esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num) { +#if CONFIG_IDF_TARGET_ESP32 //this is a digital pad if (rtc_gpio_desc[gpio_num].pulldown == 0) { return ESP_ERR_INVALID_ARG; @@ -302,12 +380,17 @@ esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num) portENTER_CRITICAL(&rtc_spinlock); SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pulldown); portEXIT_CRITICAL(&rtc_spinlock); - +#elif CONFIG_IDF_TARGET_ESP32S2BETA + portENTER_CRITICAL(&rtc_spinlock); + rtc_gpio_reg[gpio_num]->rde = 0x1; + portEXIT_CRITICAL(&rtc_spinlock); +#endif return ESP_OK; } esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num) { +#if CONFIG_IDF_TARGET_ESP32 //this is a digital pad if ( rtc_gpio_desc[gpio_num].pullup == 0 ) { return ESP_ERR_INVALID_ARG; @@ -317,12 +400,17 @@ esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num) portENTER_CRITICAL(&rtc_spinlock); CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pullup); portEXIT_CRITICAL(&rtc_spinlock); - +#elif CONFIG_IDF_TARGET_ESP32S2BETA + portENTER_CRITICAL(&rtc_spinlock); + rtc_gpio_reg[gpio_num]->rue = 0x0; + portEXIT_CRITICAL(&rtc_spinlock); +#endif return ESP_OK; } esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num) { +#if CONFIG_IDF_TARGET_ESP32 //this is a digital pad if (rtc_gpio_desc[gpio_num].pulldown == 0) { return ESP_ERR_INVALID_ARG; @@ -332,12 +420,17 @@ esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num) portENTER_CRITICAL(&rtc_spinlock); CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pulldown); portEXIT_CRITICAL(&rtc_spinlock); - +#elif CONFIG_IDF_TARGET_ESP32S2BETA + portENTER_CRITICAL(&rtc_spinlock); + rtc_gpio_reg[gpio_num]->rde = 0x0; + portEXIT_CRITICAL(&rtc_spinlock); +#endif return ESP_OK; } esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num) { +#if CONFIG_IDF_TARGET_ESP32 // check if an RTC IO if (rtc_gpio_desc[gpio_num].pullup == 0) { return ESP_ERR_INVALID_ARG; @@ -345,11 +438,13 @@ esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num) portENTER_CRITICAL(&rtc_spinlock); SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].hold); portEXIT_CRITICAL(&rtc_spinlock); +#endif return ESP_OK; } esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num) { +#if CONFIG_IDF_TARGET_ESP32 // check if an RTC IO if (rtc_gpio_desc[gpio_num].pullup == 0) { return ESP_ERR_INVALID_ARG; @@ -357,6 +452,7 @@ esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num) portENTER_CRITICAL(&rtc_spinlock); CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].hold); portEXIT_CRITICAL(&rtc_spinlock); +#endif return ESP_OK; } @@ -376,18 +472,23 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num) void rtc_gpio_force_hold_dis_all() { +#if CONFIG_IDF_TARGET_ESP32 for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) { const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio]; if (desc->hold_force != 0) { -#if CONFIG_IDF_TARGET_ESP32 REG_CLR_BIT(RTC_CNTL_HOLD_FORCE_REG, desc->hold_force); -#endif } } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.rtc_pwc.rtc_pad_force_hold = 0; + portEXIT_CRITICAL(&rtc_spinlock); +#endif } esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) { +#if CONFIG_IDF_TARGET_ESP32 int rtc_num = rtc_gpio_desc[gpio_num].rtc_num; if (rtc_num < 0) { return ESP_ERR_INVALID_ARG; @@ -400,11 +501,21 @@ esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) /* each pin has its own register, spinlock not needed */ REG_SET_BIT(reg, RTC_GPIO_PIN0_WAKEUP_ENABLE); REG_SET_FIELD(reg, RTC_GPIO_PIN0_INT_TYPE, intr_type); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); + if (( intr_type != GPIO_INTR_LOW_LEVEL ) && ( intr_type != GPIO_INTR_HIGH_LEVEL )) { + return ESP_ERR_INVALID_ARG; + } + /* each pin has its own register, spinlock not needed */ + RTCIO.pin[gpio_num].wakeup_enable = 1; + RTCIO.pin[gpio_num].int_type = intr_type; +#endif return ESP_OK; } esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num) { +#if CONFIG_IDF_TARGET_ESP32 int rtc_num = rtc_gpio_desc[gpio_num].rtc_num; if (rtc_num < 0) { return ESP_ERR_INVALID_ARG; @@ -414,9 +525,24 @@ esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num) /* each pin has its own register, spinlock not needed */ REG_CLR_BIT(reg, RTC_GPIO_PIN0_WAKEUP_ENABLE); REG_SET_FIELD(reg, RTC_GPIO_PIN0_INT_TYPE, 0); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); + /* each pin has its own register, spinlock not needed */ + RTCIO.pin[gpio_num].wakeup_enable = 0; + RTCIO.pin[gpio_num].int_type = 0; +#endif return ESP_OK; } +#if CONFIG_IDF_TARGET_ESP32S2BETA +esp_err_t rtc_gpio_force_hold_all() +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.rtc_pwc.rtc_pad_force_hold = 1; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} +#endif /*--------------------------------------------------------------- Touch Pad @@ -1739,7 +1865,9 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int* esp_err_t adc2_vref_to_gpio(gpio_num_t gpio) { +#if CONFIG_IDF_TARGET_ESP32 int channel; + if(gpio == GPIO_NUM_25){ channel = 8; //Channel 8 bit }else if (gpio == GPIO_NUM_26){ @@ -1770,7 +1898,7 @@ esp_err_t adc2_vref_to_gpio(gpio_num_t gpio) SENS.sar_meas_start2.sar2_en_pad_force = 1; //Pad bitmap controlled by SW //set en_pad for channels 7,8,9 (bits 0x380) SENS.sar_meas_start2.sar2_en_pad = 1<