component/bt : new coexist lib

change boot loader.ld , the 0x40098000 may set other instructions
This commit is contained in:
Tian Hao 2016-10-17 15:47:45 +08:00
parent bee1be67da
commit 28fa3c1a70
4 changed files with 3 additions and 4 deletions

View file

@ -15,7 +15,7 @@ MEMORY
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
dport0_seg (RW) : org = 0x3FF00000, len = 0x10 /* IO */
iram_seg (RWX) : org = 0x40098000, len = 0x1000
iram_seg (RWX) : org = 0x4009A000, len = 0x1000
iram_pool_1_seg (RWX) : org = 0x40078000, len = 0x8000 /* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache */
dram_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/
}

@ -1 +1 @@
Subproject commit 079b86ab34b57a6d62beb3f171af99399d45eb09
Subproject commit 0c3df46cb357b795ff217e68f7a8fb56d68c537f

@ -1 +1 @@
Subproject commit ae7d66f7edb4f30372c9a620ac07e4559f55a85a
Subproject commit 0ee9babfd9a9c95ff0395d442153df894df550f2

View file

@ -113,7 +113,6 @@ void app_main()
{
esp_err_t ret;
phy_set_wifi_mode_only(0);
nvs_flash_init();
system_init();
initialise_wifi();