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Add UART driver

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1. add uart.h and uart.c
2. add ESP_ERR_TIMEOUT in esp_err.h
3. add UART AHB FIFO address in uart_reg.h
4. modify xRingbufferSendFromISR return value in ringbuffer.c
5. add #include "soc/gpio_sig_map.h" in gpio.h
This commit is contained in:
Wangjialin 2016-10-24 09:17:10 +08:00
parent beff3aab81
commit 288f4f63f0
6 changed files with 1632 additions and 3 deletions
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1
components/driver/include/driver/gpio.h
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@ -20,6 +20,7 @@
#include "soc/gpio_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/gpio_sig_map.h"
#include "rom/gpio.h"
#include "esp_attr.h"

688
components/driver/include/driver/uart.h Normal file
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@ -0,0 +1,688 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DRIVER_UART_H_
#define _DRIVER_UART_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "esp_err.h"
#include "driver/periph_ctrl.h"
#include <esp_types.h>
extern const char* UART_TAG;
#define UART_FIFO_LEN (128) //Do Not Change it
#define UART_INTR_MASK 0x1ff
#define UART_LINE_INV_MASK (0x3f << 19)
typedef enum {
UART_DATA_5_BITS = 0x0, //word length: 5bits
UART_DATA_6_BITS = 0x1, //word length: 6bits
UART_DATA_7_BITS = 0x2, //word length: 7bits
UART_DATA_8_BITS = 0x3, //word length: 8bits
UART_DATA_MAX_BITS = 0X4,
} uart_word_length_t;
typedef enum {
UART_STOP_BITS_1 = 0x1, //stop bit: 1bit
UART_STOP_BITS_1_5 = 0x2, //stop bit: 1.5bits
UART_STOP_BITS_2 = 0x3, //stop bit: 2bits
UART_STOP_BITS_MAX = 0x4,
} uart_stop_bits_t;
typedef enum {
UART_NUM_0 = 0x0, //base address 0x3ff40000
UART_NUM_1 = 0x1, //base address 0x3ff50000
UART_NUM_2 = 0x2, //base address 0x3ff6E000
UART_NUM_MAX,
} uart_port_t;
typedef enum {
UART_PARITY_DISABLE = 0x0, //Disable UART parity
UART_PARITY_EVEN = 0x10, //Enable UART even parity
UART_PARITY_ODD = 0x11 //Enable UART odd parity
} uart_parity_t;
typedef enum {
UART_BITRATE_300 = 300,
UART_BITRATE_600 = 600,
UART_BITRATE_1200 = 1200,
UART_BITRATE_2400 = 2400,
UART_BITRATE_4800 = 4800,
UART_BITRATE_9600 = 9600,
UART_BITRATE_19200 = 19200,
UART_BITRATE_38400 = 38400,
UART_BITRATE_57600 = 57600,
UART_BITRATE_74880 = 74880,
UART_BITRATE_115200 = 115200,
UART_BITRATE_230400 = 230400,
UART_BITRATE_460800 = 460800,
UART_BITRATE_921600 = 921600,
UART_BITRATE_1843200 = 1843200,
UART_BITRATE_3686400 = 3686400,
UART_BITRATE_MAX = 5000000,
} uart_baudrate_t; //you can set any rate you need in this range
typedef enum {
UART_HW_FLOWCTRL_DISABLE = 0x0, //disable hardware flow control
UART_HW_FLOWCTRL_RTS = 0x1, //enable RX hardware flow control (rts)
UART_HW_FLOWCTRL_CTS = 0x2, //enable TX hardware flow control (cts)
UART_HW_FLOWCTRL_CTS_RTS = 0x3, //enable hardware flow control
UART_HW_FLOWCTRL_MAX = 0x4,
} uart_hw_flowcontrol_t;
typedef enum {
UART_INVERSE_DISABLE = 0x0, //Disable UART wire output inverse
UART_INVERSE_RXD = (uint32_t)UART_RXD_INV_M, //UART RXD input inverse
UART_INVERSE_CTS = (uint32_t)UART_CTS_INV_M, //UART CTS input inverse
UART_INVERSE_TXD = (uint32_t)UART_TXD_INV_M, //UART TXD output inverse
UART_INVERSE_RTS = (uint32_t)UART_RTS_INV_M, //UART RTS output inverse
} uart_inverse_t;
typedef struct {
uart_baudrate_t baud_rate; //UART baudrate
uart_word_length_t data_bits; //UART byte size
uart_parity_t parity; //UART parity mode
uart_stop_bits_t stop_bits; //UART stop bits
uart_hw_flowcontrol_t flow_ctrl; //UART hw flow control mode(cts/rts)
uint8_t rx_flow_ctrl_thresh ; //UART hw RTS threshold
} uart_config_t;
typedef struct {
uint32_t intr_enable_mask; //UART interrupt enable mask, choose from UART_XXXX_INT_ENA_M under UART_INT_ENA_REG(i), connect with bit-or operator
uint8_t rx_timeout_thresh; //UART timeout interrupt threshold(unit: time of sending one byte)
uint8_t txfifo_empty_intr_thresh; //UART TX empty interrupt threshold.
uint8_t rxfifo_full_thresh; //UART RX full interrupt threshold.
} uart_intr_config_t;
typedef enum {
UART_DATA,
UART_BREAK,
UART_BUFFER_FULL,
UART_FIFO_OVF,
UART_FRAME_ERR,
UART_PARITY_ERR,
UART_EVENT_MAX,
} uart_event_type_t;
typedef struct {
uart_event_type_t type;
union {
struct {
size_t size;
} data;
};
} uart_event_t;
/**
* @brief Set UART data bits.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uart_word_length_t data_bit : UART data bits
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit);
/**
* @brief Get UART data bits.
*
* @param uart_port_t uart_no: UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_FAIL (-1) : Parameter error
* UART_DATA_5_BITS (0): UART word length: 5 bits.
* UART_DATA_6_BITS (1): UART word length: 6 bits.
* UART_DATA_7_BITS (2): UART word length: 7 bits.
* UART_DATA_8_BITS (3): UART word length: 8 bits.
*/
int uart_get_word_length(uart_port_t uart_num);
/**
* @brief Set UART stop bits.
*
* @param uart_port_t uart_no: UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uart_stop_bits_t bit_num : UART stop bits
*
* @return ESP_OK : Success
* ESP_FAIL: Fail
*/
esp_err_t uart_set_stop_bits(uart_port_t uart_no, uart_stop_bits_t bit_num);
/**
* @brief Set UART stop bits.
*
* @param uart_port_t uart_no: UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_FAIL (-1): Parameter error
* UART_STOP_BITS_1 (1): 1 stop bit
* UART_STOP_BITS_1_5 (2): 1.5 stop bits
* UART_STOP_BITS_1 (3): 2 stop bits
*/
int uart_get_stop_bits(uart_port_t uart_num);
/**
* @brief Set UART parity.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uart_parity_t parity_mode : the enum of uart parity configuration
*
* @return null
*/
esp_err_t uart_set_parity(uart_port_t uart_no, uart_parity_t parity_mode);
/**
* @brief Get UART parity mode.
*
* @param uart_port_t uart_no: UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_FAIL (-1): Parameter error
* UART_PARITY_ODD (0x11): Odd parity check mode
* UART_PARITY_EVEN (0x10): Even parity check mode
* UART_PARITY_DISABLE(0x0) : parity check disabled
*
*/
int uart_get_parity(uart_port_t uart_num);
/**
* @brief Set UART baud rate.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uint32_t baud_rate : UART baud-rate, we can choose one from uart_baudrate_t, or set a value.
*
* @return null
*/
esp_err_t uart_set_baudrate(uart_port_t uart_no, uint32_t baud_rate);
/**
* @brief Get UART bit-rate.
*
* @param uart_port_t uart_no: UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_FAIL(-1): Parameter error
* Others (>0): UART baud-rate
*
*/
int uart_get_baudrate(uart_port_t uart_num);
/**
* @brief Set UART line inverse mode
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uint32_t inverse_mask : Choose the wires that need to be inversed
* (Should be chosen from uart_inverse_t, combine with OR-OPERATION)
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_set_line_inverse(uart_port_t uart_no, uint32_t inverse_mask) ;
/**
* @brief Set hardware flow control.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uart_hw_flowcontrol_t flow_ctrl : Hardware flow control mode
* @param uint8_t rx_thresh : Threshold of Hardware RX flow control(0 ~ UART_FIFO_LEN)
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_no, uart_hw_flowcontrol_t flow_ctrl, uint8_t rx_thresh);
/**
* @brief Get hardware flow control mode
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_FAIL (-1): Parameter error
* UART_HW_FLOWCTRL_DISABLE (0): UART hw flow control disabled
* UART_HW_FLOWCTRL_RTS (1): UART RX flow control enabled
* UART_HW_FLOWCTRL_CTS (2): UART TX flow control enabled
* UART_HW_FLOWCTRL_CTS_RTS (3): UART TX/RX flow control enabled
*/
int uart_get_hw_flow_ctrl(uart_port_t uart_num);
/**
* @brief Clear UART interrupt status
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uint32_t clr_mask : Bit mask of the status that to be cleared.
* enable_mask should be chosen from the fields of register UART_INT_CLR_REG
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_clear_intr_status(uart_port_t uart_num, uint32_t clr_mask);
/**
* @brief Set UART interrupt enable
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uint32_t enable_mask : Bit mask of the enable bits.
* enable_mask should be chosen from the fields of register UART_INT_ENA_REG
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_enable_intr_mask(uart_port_t uart_num, uint32_t enable_mask);
/**
* @brief Clear UART interrupt enable bits
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uint32_t disable_mask : Bit mask of the disable bits.
* Disable_mask should be chosen from the fields of register UART_INT_ENA_REG
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_disable_intr_mask(uart_port_t uart_num, uint32_t disable_mask);
/**
* @brief Enable UART RX interrupt(RX_FULL & RX_TIMEOUT INTERRUPT)
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_enable_rx_intr(uart_port_t uart_num);
/**
* @brief Disable UART RX interrupt(RX_FULL & RX_TIMEOUT INTERRUPT)
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_disable_rx_intr(uart_port_t uart_num);
/**
* @brief Disable UART TX interrupt(RX_FULL & RX_TIMEOUT INTERRUPT)
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_disable_tx_intr(uart_port_t uart_num);
/**
* @brief Enable UART TX interrupt(RX_FULL & RX_TIMEOUT INTERRUPT)
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param int enable : 1: enable; 0: disable
* @param int thresh : Threshold of TX interrupt, 0 ~ UART_FIFO_LEN
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh);
/**
* @brief register UART interrupt handler(ISR).
* UART ISR handler will be attached to the same CPU core that this function is running on.
* Users should know that which CPU is running and then pick a INUM that is not used by system.
* We can find the information of INUM and interrupt level in soc.h.
*
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uint8_t uart_intr_num : UART interrupt number,check the info in soc.h, and please refer to core-isa.h for more details
* @param void (* fn)(void* ) : Interrupt handler function.
* Note that the handler function MUST be defined with attribution of "IRAM_ATTR" for now.
* @param void * arg : parameter for handler function
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_isr_register(uart_port_t uart_num, uint8_t uart_intr_num, void (*fn)(void*), void * arg);
/**
* @brief Set UART pin number
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param tx_io_num : UART TX pin GPIO number
* @param rx_io_num : UART RX pin GPIO number
* @param rts_io_num : UART RTS pin GPIO number
* @param cts_io_num : UART CTS pin GPIO number
*
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num);
/**
* @brief UART set RTS level (before inverse)
* UART rx hardware flow control should not be set.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param int level : 1: RTS output low(active)
* 0: RTS output high(block)
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_set_rts(uart_port_t uart_num, int level);
/**
* @brief UART set DTR level (before inverse)
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param int level : 1: DTR output low
* 0: DTR output high
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_set_dtr(uart_port_t uart_num, int level);
/**
* @brief UART parameter configure
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uart_config_t *uart_config: UART parameter settings
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_param_config(uart_port_t uart_num, uart_config_t *uart_config);
/**
* @brief UART interrupt configure
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uart_intr_config_t *p_intr_conf: UART interrupt settings
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_intr_config(uart_port_t uart_num, uart_intr_config_t *p_intr_conf);
/**
* @brief Install UART driver.
* UART ISR handler will be attached to the same CPU core that this function is running on.
* Users should know that which CPU is running and then pick a INUM that is not used by system.
* We can find the information of INUM and interrupt level in soc.h.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param int buffer_size : UART ring buffer size
* @param int queue_size : UART event queue size/depth.
* @param int uart_intr_num : UART interrupt number,check the info in soc.h, and please refer to core-isa.h for more details
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_driver_install(uart_port_t uart_num, int buffer_size, int queue_size, int uart_intr_num, void* uart_queue);
/**
* @brief Uninstall UART driver.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_driver_delete(uart_port_t uart_num);
/**
* @brief Wait UART TX FIFO empty
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param TickType_t ticks_to_wait: Timeout, count in RTOS ticks
*
* @return ESP_OK : Success
* ESP_ERR_TIMEOUT: Timeout
*/
esp_err_t uart_wait_tx_fifo_empty(uart_port_t uart_num, TickType_t ticks_to_wait);
/**
* @brief Send data to the UART port from a given buffer and length,
* This function will not wait for the space in TX FIFO, just fill the TX FIFO and return when the FIFO is full.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param char* buffer : data buffer address
* @param uint32_t len : data length to send
*
* @return The number of data that pushed to the TX FIFO
*/
int uart_tx_chars(uart_port_t uart_no, char* buffer, uint32_t len);
/**
* @brief Send data to the UART port from a given buffer and length,
* This function will not return until all the data have been sent out, or at least pushed into TX FIFO.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param char* src : data buffer address
* @param size_t size : data length to send
*
* @return The number of data that sent out.
*/
int uart_tx_all_chars(uart_port_t uart_num, const char* src, size_t size);
/**
* @brief Send data to the UART port from a given buffer and length,
* This function will not return until all the data and the break signal have been sent out.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param char* src : data buffer address
* @param size_t size : data length to send
* @param int brk_len : break signal length (unit: one bit's time@current_baudrate)
*
* @return The number of data that sent out.
*/
int uart_tx_all_chars_with_break(uart_port_t uart_num, const char* src, size_t size, int brk_len);
/**
* @brief UART read one char
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param TickType_t ticks_to_wait : ticks to wait.
*
* @return -1 : Error
* Others : return a char data from uart fifo.
*/
int uart_read_char(uart_port_t uart_num, TickType_t ticks_to_wait);
/**
* @brief UART read bytes from UART buffer
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uint8_t* buf : pointer to the buffer.
* @param uint32_t length : data length
* @param TickType_t ticks_to_wait: timeout time( FreeRTOS ti c
*
* @return -1 : Error
* Others : return a char data from uart fifo.
*/
int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickType_t ticks_to_wait);
/**
* @brief UART ring buffer flush
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error
*/
esp_err_t uart_flush(uart_port_t uart_num);
/**
* @brief Set the serial output port for ets_printf function, not effective for ESP_LOGX macro.
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return ESP_OK : Success
* ESP_FAIL: Parameter error, or UART driver not installed.
*/
esp_err_t uart_set_print_port(uart_port_t uart_no);
/**
* @brief Get the current serial port for ets_printf function
*
*
* @param uart_port_t uart_no : UART_NUM_0, UART_NUM_1 or UART_NUM_2
*
* @return null
*/
int uart_get_print_port();
/***************************EXAMPLE**********************************
*
*
* ----------------EXAMPLE OF UART SETTING ---------------------
* //1. Setup UART
* #include "freertos/queue.h"
* #define UART_INTR_NUM 17 //choose one interrupt number from soc.h
* //a. Set UART parameter
* int uart_num = 0; //uart port number
* uart_config_t uart_config = {
* .baud_rate = UART_BITRATE_115200, //baudrate
* .data_bits = UART_DATA_8_BITS, //data bit mode
* .parity = UART_PARITY_DISABLE, //parity mode
* .stop_bits = UART_STOP_BITS_1, //stop bit mode
* .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, //hardware flow control(cts/rts)
* .rx_flow_ctrl_thresh = 120, //flow control threshold
* };
* uart_param_config(uart_num, &uart_config);
* //b1. Setup UART driver(with UART queue)
* QueueHandle_t uart_queue;
* uart_driver_install(uart_num, 1024 * 2, 10, UART_INTR_NUM, &uart_queue);//parameters here are just an example
* //b2. Setup UART driver(without UART queue)
* uart_driver_install(uart_num, 1024 * 2, 10, UART_INTR_NUM, NULL); //parameters here are just an example
*
*-----------------------------------------------------------------------------*
* //2. Set UART pin
* uart_set_pin(uart_num, -1, -1, 15, 13); //set UART pin, not needed if use default pins.
*
*-----------------------------------------------------------------------------*
* //3. Read data from UART.
* uint8_t data[128];
* int length = 0;
* length = uart_read_bytes(uart_num, data, sizeof(data), 100);
*
*-----------------------------------------------------------------------------*
* //4. Write data to UART.
* char* test_str = "This is a test string.\n"
* uart_tx_all_chars(uart_num, (const char*)test_str, strlen(test_str));
*
*-----------------------------------------------------------------------------*
* //5. Write data to UART, end with a break signal.
* uart_tx_all_chars_with_break(0, "test break\n",strlen("test break\n"), 100);
*
*-----------------------------------------------------------------------------*
*
* //6. an example of echo test with hardware flow control on UART1
* void uart_loop_back_test()
* {
* int uart_num = 1;
* uart_config_t uart_config = {
* .baud_rate = 115200,
* .data_bits = UART_DATA_8_BITS,
* .parity = UART_PARITY_DISABLE,
* .stop_bits = UART_STOP_BITS_1,
* .flow_ctrl = UART_HW_FLOWCTRL_CTS_RTS,
* .rx_flow_ctrl_thresh = 122,
* };
* uart_param_config(uart_num, &uart_config); //Config UART1 parameters
* uart_set_pin(uart_num, 16, 17, 18, 19); //Set UART1 pins(TX: IO16, RX: IO17, RTS: IO18, CTS: IO19)
* esp_log_level_set(UART_TAG, ESP_LOG_ERROR); //Set UART log level
* uart_driver_install(uart_num, 1024 * 2, 10, 17, NULL); //Install UART driver( We don't need an event queue here)
* uint8_t data[1000];
* while(1) {
* int len = uart_read_bytes(uart_num, data, sizeof(data), 10); //Read data from UART
* uart_tx_all_chars(uart_num, (const char*)data, len); //Write data back to UART
* }
* }
*
*-----------------------------------------------------------------------------*
* //7. An example of using UART event queue on UART0.
*
* #include "freertos/queue.h"
* QueueHandle_t uart0_queue; //A queue to handle UART event.
* void uart_task(void *pvParameters)
* {
* int uart_num = (int)pvParameters;
* uart_event_t event;
* uint8_t dtmp[1000];
* for(;;) {
* if(xQueueReceive(uart0_queue, (void * )&event, (portTickType)portMAX_DELAY)) { //Waiting for UART event.
* ESP_LOGI(UART_TAG, "uart[%d] event:", uart_num);
* switch(event.type) {
* case UART_DATA: //Event of UART receving data
* ESP_LOGI(UART_TAG,"data, len: %d\n", event.data.size);
* int len = uart_read_bytes(uart_num, dtmp, event.data.size, 10);
* ESP_LOGI(UART_TAG, "uart read: %d\n", len);
* break;
* case UART_FIFO_OVF: //Event of HW FIFO overflow detected
* ESP_LOGI(UART_TAG, "hw fifo overflow\n");
* while(1);
* break;
* case UART_BUFFER_FULL: //Event of UART ring buffer full
* ESP_LOGI(UART_TAG, "ring buffer full\n");
* break;
* case UART_BREAK:
* ESP_LOGI(UART_TAG, "uart rx break\n"); //Event of UART RX break detected
* break;
* case UART_PARITY_ERR: //Event of UART parity check error
* ESP_LOGI(UART_TAG, "uart parity error\n");
* break;
* case UART_FRAME_ERR: //Event of UART frame error
* ESP_LOGI(UART_TAG, "uart frame error\n");
* break;
* default: //Others
* ESP_LOGI(UART_TAG, "uart event type: %d\n", event.type);
* break;
* }
* }
* }
* vTaskDelete(NULL);
* }
*
* void uart_queue_test()
* {
* int uart_num = 0;
* uart_config_t uart_config = {
* .baud_rate = 115200,
* .data_bits = UART_DATA_8_BITS,
* .parity = UART_PARITY_DISABLE,
* .stop_bits = UART_STOP_BITS_1,
* .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
* .rx_flow_ctrl_thresh = 122,
* };
* uart_param_config(uart_num, &uart_config); //Set UART parameters
* uart_set_pin(uart_num, -1, -1, 15, 13); //Set UART pins,(-1: default pin, no change.)
* esp_log_level_set(UART_TAG, ESP_LOG_INFO); //Set UART log level
* uart_driver_install(uart_num, 1024 * 2, 10, 17, &uart0_queue); //Install UART driver, and get the queue.
* xTaskCreate(uart_task, "uTask", 2048*8, (void*)uart_num, 10, NULL); //Create a task to handler UART event from ISR
* }
*
*
***************************END OF EXAMPLE**********************************/
#ifdef __cplusplus
}
#endif
#endif /*_DRIVER_UART_H_*/

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <string.h>
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr.h"
#include "esp_log.h"
#include "malloc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"
#include "freertos/task.h"
#include "freertos/ringbuf.h"
#include "soc/dport_reg.h"
#include "rom/ets_sys.h"
#include "soc/uart_struct.h"
#include "driver/uart.h"
#include "driver/gpio.h"
#include "soc/uart_struct.h"
const char* UART_TAG = "UART";
#define UART_CHECK(a, str) if (!(a)) { \
ESP_LOGE(UART_TAG,"%s:%d (%s):%s\n", __FILE__, __LINE__, __FUNCTION__, str); \
return ESP_FAIL; \
}
#define DEFAULT_EMPTY_THRESH 10
#define DEFAULT_FULL_THRESH 120
#define DEFAULT_TOUT_THRESH 10
#define UART_ENTER_CRITICAL_ISR(mux) portENTER_CRITICAL_ISR(mux)
#define UART_EXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL_ISR(mux)
#define UART_ENTER_CRITICAL(mux) portENTER_CRITICAL(mux)
#define UART_EXIT_CRITICAL(mux) portEXIT_CRITICAL(mux)
typedef struct {
uart_port_t uart_num;
SemaphoreHandle_t tx_fifo_sem;
SemaphoreHandle_t tx_mutex;
SemaphoreHandle_t tx_done_sem;
SemaphoreHandle_t tx_brk_sem;
SemaphoreHandle_t rx_sem;
QueueHandle_t xQueueUart;
int queue_size;
int intr_num;
RingbufHandle_t ring_buffer;
bool buffer_full_flg;
bool tx_waiting;
int cur_remain;
uint8_t* rd_ptr;
uint8_t* head_ptr;
uint8_t data_buf[UART_FIFO_LEN];
uint8_t data_len;
} uart_obj_t;
static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0};
static uart_dev_t* UART[UART_NUM_MAX] = {&UART0, &UART1, &UART2};
static portMUX_TYPE uart_spinlock[UART_NUM_MAX] = {portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED};
//Fill UART tx_fifo and return a number,
//This function by itself is not thread-safe, always call from within a muxed section.
static int uart_fill_fifo(uart_port_t uart_num, char* buffer, uint32_t len)
{
uint8_t i = 0;
uint8_t tx_fifo_cnt = UART[uart_num]->status.txfifo_cnt;
uint8_t tx_remain_fifo_cnt = (UART_FIFO_LEN - tx_fifo_cnt);
uint8_t copy_cnt = (len >= tx_remain_fifo_cnt ? tx_remain_fifo_cnt : len);
for(i = 0; i < copy_cnt; i++) {
WRITE_PERI_REG(UART_FIFO_AHB_REG(uart_num), buffer[i]);
}
return copy_cnt;
}
esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((data_bit < UART_DATA_MAX_BITS), "data bit error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->conf0.bit_num = data_bit;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
int uart_get_word_length(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
return UART[uart_num]->conf0.bit_num;
}
esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((stop_bit < UART_STOP_BITS_MAX), "stop bit error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->conf0.stop_bit_num = stop_bit;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
int uart_get_stop_bits(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
return UART[uart_num]->conf0.stop_bit_num;
}
esp_err_t uart_set_parity(uart_port_t uart_num, uart_parity_t parity_mode)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->conf0.parity = parity_mode & 0x1;
UART[uart_num]->conf0.parity_en = (parity_mode >> 1) & 0x1;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
int uart_get_parity(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
int val = UART[uart_num]->conf0.val;
if(val & UART_PARITY_EN_M) {
if(val & UART_PARITY_M) {
return UART_PARITY_ODD;
} else {
return UART_PARITY_EVEN;
}
} else {
return UART_PARITY_DISABLE;
}
}
esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((baud_rate < UART_BITRATE_MAX), "baud_rate error");
uint32_t clk_div = (((UART_CLK_FREQ) << 4) / baud_rate);
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->clk_div.div_int = clk_div >> 4;
UART[uart_num]->clk_div.div_frag = clk_div & 0xf;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
int uart_get_baudrate(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
uint32_t clk_div = (UART[uart_num]->clk_div.div_int << 4) | UART[uart_num]->clk_div.div_frag;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
uint32_t baudrate = ((UART_CLK_FREQ) << 4) / clk_div;
return baudrate;
}
esp_err_t uart_set_line_inverse(uart_port_t uart_num, uint32_t inverse_mask)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((((inverse_mask & UART_LINE_INV_MASK) == 0) && (inverse_mask != 0)), "inverse_mask error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
CLEAR_PERI_REG_MASK(UART_CONF0_REG(uart_num), UART_LINE_INV_MASK);
SET_PERI_REG_MASK(UART_CONF0_REG(uart_num), inverse_mask);
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow_ctrl, uint8_t rx_thresh)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((rx_thresh < UART_FIFO_LEN), "rx flow thresh error");
UART_CHECK((flow_ctrl < UART_HW_FLOWCTRL_MAX), "hw_flowctrl mode error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
if(flow_ctrl & UART_HW_FLOWCTRL_RTS) {
UART[uart_num]->conf1.rx_flow_thrhd = rx_thresh;
UART[uart_num]->conf1.rx_flow_en = 1;
} else {
UART[uart_num]->conf1.rx_flow_en = 0;
}
if(flow_ctrl & UART_HW_FLOWCTRL_CTS) {
UART[uart_num]->conf0.tx_flow_en = 1;
} else {
UART[uart_num]->conf0.tx_flow_en = 0;
}
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
int uart_get_hw_flow_ctrl(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
uart_hw_flowcontrol_t val = UART_HW_FLOWCTRL_DISABLE;
if(UART[uart_num]->conf1.rx_flow_en) {
val |= UART_HW_FLOWCTRL_RTS;
}
if(UART[uart_num]->conf0.tx_flow_en) {
val |= UART_HW_FLOWCTRL_CTS;
}
return val;
}
static esp_err_t uart_reset_fifo(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->conf0.rxfifo_rst = 1;
UART[uart_num]->conf0.rxfifo_rst = 0;
UART[uart_num]->conf0.txfifo_rst = 1;
UART[uart_num]->conf0.txfifo_rst = 0;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
esp_err_t uart_clear_intr_status(uart_port_t uart_num, uint32_t clr_mask)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
//intr_clr register is write-only
UART[uart_num]->int_clr.val = clr_mask;
return ESP_OK;
}
esp_err_t uart_enable_intr_mask(uart_port_t uart_num, uint32_t enable_mask)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
SET_PERI_REG_MASK(UART_INT_CLR_REG(uart_num), enable_mask);
SET_PERI_REG_MASK(UART_INT_ENA_REG(uart_num), enable_mask);
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
esp_err_t uart_disable_intr_mask(uart_port_t uart_num, uint32_t disable_mask)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
CLEAR_PERI_REG_MASK(UART_INT_ENA_REG(uart_num), disable_mask);
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
esp_err_t uart_enable_rx_intr(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
SET_PERI_REG_MASK(UART_INT_ENA_REG(uart_num), UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_TOUT_INT_ENA);
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
esp_err_t uart_disable_rx_intr(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
CLEAR_PERI_REG_MASK(UART_INT_ENA_REG(uart_num), UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_TOUT_INT_ENA);
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
esp_err_t uart_disable_tx_intr(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->int_ena.txfifo_empty = 0;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((thresh < UART_FIFO_LEN), "empty intr threshold error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->int_clr.txfifo_empty = 1;
UART[uart_num]->conf1.txfifo_empty_thrhd = thresh & UART_TXFIFO_EMPTY_THRHD_V;
UART[uart_num]->int_ena.txfifo_empty = enable & 0x1;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
ESP_INTR_ENABLE(p_uart_obj[uart_num]->intr_num);
return ESP_OK;
}
esp_err_t uart_isr_register(uart_port_t uart_num, uint8_t uart_intr_num, void (*fn)(void*), void * arg)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
ESP_INTR_DISABLE(uart_intr_num);
switch(uart_num) {
case UART_NUM_1:
intr_matrix_set(xPortGetCoreID(), ETS_UART1_INTR_SOURCE, uart_intr_num);
break;
case UART_NUM_2:
intr_matrix_set(xPortGetCoreID(), ETS_UART2_INTR_SOURCE, uart_intr_num);
break;
case UART_NUM_0:
default:
intr_matrix_set(xPortGetCoreID(), ETS_UART0_INTR_SOURCE, uart_intr_num);
break;
}
xt_set_interrupt_handler(uart_intr_num, fn, arg);
ESP_INTR_ENABLE(uart_intr_num);
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
//internal signal can be output to multiple GPIO pads
//only one GPIO pad can connect with input signal
esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((tx_io_num < 0 || tx_io_num < GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[tx_io_num] != 0), "tx_io_num error");
UART_CHECK((rx_io_num < 0 || rx_io_num < GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[rx_io_num] != 0), "rx_io_num error");
UART_CHECK((rts_io_num < 0 || rts_io_num < GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[rts_io_num] != 0), "rts_io_num error");
UART_CHECK((cts_io_num < 0 || cts_io_num < GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[cts_io_num] != 0), "cts_io_num error");
int tx_sig, rx_sig, rts_sig, cts_sig;
switch(uart_num) {
case UART_NUM_0:
tx_sig = U0TXD_OUT_IDX;
rx_sig = U0RXD_IN_IDX;
rts_sig = U0RTS_OUT_IDX;
cts_sig = U0CTS_IN_IDX;
break;
case UART_NUM_1:
tx_sig = U1TXD_OUT_IDX;
rx_sig = U1RXD_IN_IDX;
rts_sig = U1RTS_OUT_IDX;
cts_sig = U1CTS_IN_IDX;
break;
case UART_NUM_2:
tx_sig = U2TXD_OUT_IDX;
rx_sig = U2RXD_IN_IDX;
rts_sig = U2RTS_OUT_IDX;
cts_sig = U2CTS_IN_IDX;
break;
case UART_NUM_MAX:
default:
tx_sig = U0TXD_OUT_IDX;
rx_sig = U0RXD_IN_IDX;
rts_sig = U0RTS_OUT_IDX;
cts_sig = U0CTS_IN_IDX;
break;
}
if(tx_io_num >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
gpio_set_direction(tx_io_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(tx_io_num, tx_sig, 0, 0);
}
if(rx_io_num >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
gpio_matrix_in(rx_io_num, rx_sig, 0);
}
if(rts_io_num >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(rts_io_num, rts_sig, 0, 0);
}
if(cts_io_num >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
gpio_matrix_in(cts_io_num, cts_sig, 0);
}
return ESP_OK;
}
esp_err_t uart_set_rts(uart_port_t uart_num, int level)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((UART[uart_num]->conf1.rx_flow_en != 1), "disable hw flowctrl before using sw control\n");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->conf0.sw_rts = level & 0x1;
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
esp_err_t uart_set_dtr(uart_port_t uart_num, int level)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->conf0.sw_dtr = level & 0x1;
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
esp_err_t uart_param_config(uart_port_t uart_num, uart_config_t *uart_config)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((uart_config), "param null\n");
if(uart_num == UART_NUM_0) {
periph_module_enable(PERIPH_UART0_MODULE);
} else if(uart_num == UART_NUM_1) {
periph_module_enable(PERIPH_UART1_MODULE);
} else if(uart_num == UART_NUM_2) {
periph_module_enable(PERIPH_UART2_MODULE);
}
uart_set_hw_flow_ctrl(uart_num, uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh);
uart_set_baudrate(uart_num, uart_config->baud_rate);
UART[uart_num]->conf0.val = (
(uart_config->parity << UART_PARITY_S)
| (uart_config->stop_bits << UART_STOP_BIT_NUM_S)
| (uart_config->data_bits << UART_BIT_NUM_S)
| ((uart_config->flow_ctrl & UART_HW_FLOWCTRL_CTS) ? UART_TX_FLOW_EN : 0x0)
| UART_TICK_REF_ALWAYS_ON_M);
return ESP_OK;
}
esp_err_t uart_intr_config(uart_port_t uart_num, uart_intr_config_t *p_intr_conf)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((p_intr_conf), "param null\n");
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->int_clr.val = UART_INTR_MASK;
if(p_intr_conf->intr_enable_mask & UART_RXFIFO_TOUT_INT_ENA_M) {
UART[uart_num]->conf1.rx_tout_thrhd = ((p_intr_conf->rx_timeout_thresh) & UART_RX_TOUT_THRHD_V);
UART[uart_num]->conf1.rx_tout_en = 1;
} else {
UART[uart_num]->conf1.rx_tout_en = 0;
}
if(p_intr_conf->intr_enable_mask & UART_RXFIFO_FULL_INT_ENA_M) {
UART[uart_num]->conf1.rxfifo_full_thrhd = p_intr_conf->rxfifo_full_thresh;
}
if(p_intr_conf->intr_enable_mask & UART_TXFIFO_EMPTY_INT_ENA_M) {
UART[uart_num]->conf1.txfifo_empty_thrhd = p_intr_conf->txfifo_empty_intr_thresh;
}
UART[uart_num]->int_ena.val = p_intr_conf->intr_enable_mask;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_FAIL;
}
//internal isr handler for default driver code.
static void IRAM_ATTR uart_rx_intr_handler_default(void *param)
{
uart_obj_t *p_uart = (uart_obj_t*) param;
uint8_t uart_num = p_uart->uart_num;
uart_dev_t* uart_reg = UART[uart_num];
uint8_t buf_idx = 0;
uint32_t uart_intr_status = UART[uart_num]->int_st.val;
static int rx_fifo_len = 0;
uart_event_t uart_event;
portBASE_TYPE HPTaskAwoken = 0;
while(uart_intr_status != 0x0) {
buf_idx = 0;
uart_event.type = UART_EVENT_MAX;
if(uart_intr_status & UART_TXFIFO_EMPTY_INT_ST_M) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_ena.txfifo_empty = 0;
uart_reg->int_clr.txfifo_empty = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
if(p_uart->tx_waiting == true) {
p_uart->tx_waiting = false;
xSemaphoreGiveFromISR(p_uart->tx_fifo_sem, NULL);
}
}
else if((uart_intr_status & UART_RXFIFO_TOUT_INT_ST_M) || (uart_intr_status & UART_RXFIFO_FULL_INT_ST_M)) {
if(p_uart->buffer_full_flg == false) {
//Get the buffer from the FIFO
rx_fifo_len = uart_reg->status.rxfifo_cnt;
p_uart->data_len = rx_fifo_len;
memset(p_uart->data_buf, 0, sizeof(p_uart->data_buf));
while(buf_idx < rx_fifo_len) {
p_uart->data_buf[buf_idx++] = uart_reg->fifo.rw_byte;
}
//After Copying the Data From FIFO ,Clear intr_status
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_clr.rxfifo_tout = 1;
uart_reg->int_clr.rxfifo_full = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_event.type = UART_DATA;
uart_event.data.size = rx_fifo_len;
if(pdFALSE == xRingbufferSendFromISR(p_uart->ring_buffer, p_uart->data_buf, p_uart->data_len, &HPTaskAwoken)) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_ena.rxfifo_full = 0;
uart_reg->int_ena.rxfifo_tout = 0;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
p_uart->buffer_full_flg = true;
uart_event.type = UART_BUFFER_FULL;
} else {
uart_event.type = UART_DATA;
}
} else {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_ena.rxfifo_full = 0;
uart_reg->int_ena.rxfifo_tout = 0;
uart_reg->int_clr.val = UART_RXFIFO_FULL_INT_CLR_M | UART_RXFIFO_TOUT_INT_CLR_M;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_event.type = UART_BUFFER_FULL;
}
} else if(uart_intr_status & UART_RXFIFO_OVF_INT_ST_M) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->conf0.rxfifo_rst = 1;
uart_reg->conf0.rxfifo_rst = 0;
uart_reg->int_clr.rxfifo_ovf = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_event.type = UART_FIFO_OVF;
} else if(uart_intr_status & UART_BRK_DET_INT_ST_M) {
uart_reg->int_clr.brk_det = 1;
uart_event.type = UART_BREAK;
} else if(uart_intr_status & UART_FRM_ERR_INT_ST_M) {
uart_reg->int_clr.parity_err = 1;
uart_event.type = UART_FRAME_ERR;
} else if(uart_intr_status & UART_PARITY_ERR_INT_ST_M) {
uart_reg->int_clr.frm_err = 1;
uart_event.type = UART_PARITY_ERR;
} else if(uart_intr_status & UART_TX_BRK_DONE_INT_ST_M) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->conf0.txd_brk = 0;
uart_reg->int_ena.tx_brk_done = 0;
uart_reg->int_clr.tx_brk_done = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
xSemaphoreGiveFromISR(p_uart->tx_brk_sem, &HPTaskAwoken);
} else if(uart_intr_status & UART_TX_BRK_IDLE_DONE_INT_ST_M) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_ena.tx_brk_idle_done = 0;
uart_reg->int_clr.tx_brk_idle_done = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
} else if(uart_intr_status & UART_TX_DONE_INT_ST_M) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reg->int_ena.tx_done = 0;
uart_reg->int_clr.tx_done = 1;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
xSemaphoreGiveFromISR(p_uart_obj[uart_num]->tx_done_sem, &HPTaskAwoken);
}
else {
uart_reg->int_clr.val = uart_intr_status; /*simply clear all other intr status*/
uart_event.type = UART_EVENT_MAX;
}
if(uart_event.type != UART_EVENT_MAX && p_uart->xQueueUart) {
xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken);
}
uart_intr_status = uart_reg->int_st.val;
}
}
/**************************************************************/
esp_err_t uart_driver_install(uart_port_t uart_num, int buffer_size, int queue_size, int uart_intr_num, void* uart_queue)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
if(p_uart_obj[uart_num] == NULL) {
ESP_INTR_DISABLE(uart_intr_num);
p_uart_obj[uart_num] = (uart_obj_t*) malloc(sizeof(uart_obj_t));
if(p_uart_obj[uart_num] == NULL) {
ESP_LOGE(UART_TAG, "UART driver malloc error\n");
return ESP_FAIL;
}
p_uart_obj[uart_num]->uart_num = uart_num;
p_uart_obj[uart_num]->tx_fifo_sem = xSemaphoreCreateBinary();
xSemaphoreGive(p_uart_obj[uart_num]->tx_fifo_sem);
p_uart_obj[uart_num]->tx_done_sem = xSemaphoreCreateBinary();
xSemaphoreGive(p_uart_obj[uart_num]->tx_done_sem);
p_uart_obj[uart_num]->tx_brk_sem = xSemaphoreCreateBinary();
p_uart_obj[uart_num]->tx_mutex = xSemaphoreCreateMutex();
p_uart_obj[uart_num]->rx_sem = xSemaphoreCreateMutex();
p_uart_obj[uart_num]->intr_num = uart_intr_num;
p_uart_obj[uart_num]->queue_size = queue_size;
if(uart_queue) {
p_uart_obj[uart_num]->xQueueUart = xQueueCreate(queue_size, sizeof(uart_event_t));
*((QueueHandle_t*) uart_queue) = p_uart_obj[uart_num]->xQueueUart;
ESP_LOGI(UART_TAG, "queue free spaces: %d\n", uxQueueSpacesAvailable(p_uart_obj[uart_num]->xQueueUart));
} else {
p_uart_obj[uart_num]->xQueueUart = NULL;
}
p_uart_obj[uart_num]->buffer_full_flg = false;
p_uart_obj[uart_num]->tx_waiting = false;
p_uart_obj[uart_num]->rd_ptr = NULL;
p_uart_obj[uart_num]->cur_remain = 0;
p_uart_obj[uart_num]->head_ptr = NULL;
p_uart_obj[uart_num]->ring_buffer = xRingbufferCreate(buffer_size, 0);
} else {
ESP_LOGE(UART_TAG, "UART driver already installed\n");
return ESP_FAIL;
}
uart_isr_register(uart_num, uart_intr_num, uart_rx_intr_handler_default, p_uart_obj[uart_num]);
uart_intr_config_t uart_intr = {
.intr_enable_mask = UART_RXFIFO_FULL_INT_ENA_M
| UART_RXFIFO_TOUT_INT_ENA_M
| UART_FRM_ERR_INT_ENA_M
| UART_RXFIFO_OVF_INT_ENA_M
| UART_BRK_DET_INT_ENA_M,
.rxfifo_full_thresh = DEFAULT_FULL_THRESH,
.rx_timeout_thresh = DEFAULT_TOUT_THRESH,
.txfifo_empty_intr_thresh = DEFAULT_EMPTY_THRESH
};
uart_intr_config(uart_num, &uart_intr);
ESP_INTR_ENABLE(uart_intr_num);
return ESP_OK;
}
//Make sure no other tasks are still using UART before you call this function
esp_err_t uart_driver_delete(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
if(p_uart_obj[uart_num] == NULL) {
ESP_LOGI(UART_TAG, "ALREADY NULL\n");
return ESP_OK;
}
ESP_INTR_DISABLE(p_uart_obj[uart_num]->intr_num);
uart_disable_rx_intr(uart_num);
uart_disable_tx_intr(uart_num);
uart_isr_register(uart_num, p_uart_obj[uart_num]->intr_num, NULL, NULL);
if(p_uart_obj[uart_num]->tx_fifo_sem) {
vSemaphoreDelete(p_uart_obj[uart_num]->tx_fifo_sem);
p_uart_obj[uart_num]->tx_fifo_sem = NULL;
}
if(p_uart_obj[uart_num]->tx_done_sem) {
vSemaphoreDelete(p_uart_obj[uart_num]->tx_done_sem);
p_uart_obj[uart_num]->tx_done_sem = NULL;
}
if(p_uart_obj[uart_num]->tx_brk_sem) {
vSemaphoreDelete(p_uart_obj[uart_num]->tx_brk_sem);
p_uart_obj[uart_num]->tx_brk_sem = NULL;
}
if(p_uart_obj[uart_num]->tx_mutex) {
vSemaphoreDelete(p_uart_obj[uart_num]->tx_mutex);
p_uart_obj[uart_num]->tx_mutex = NULL;
}
if(p_uart_obj[uart_num]->rx_sem) {
vSemaphoreDelete(p_uart_obj[uart_num]->rx_sem);
p_uart_obj[uart_num]->rx_sem = NULL;
}
if(p_uart_obj[uart_num]->xQueueUart) {
vQueueDelete(p_uart_obj[uart_num]->xQueueUart);
p_uart_obj[uart_num]->xQueueUart = NULL;
}
if(p_uart_obj[uart_num]->ring_buffer) {
vRingbufferDelete(p_uart_obj[uart_num]->ring_buffer);
p_uart_obj[uart_num]->ring_buffer = NULL;
}
free(p_uart_obj[uart_num]);
p_uart_obj[uart_num] = NULL;
return ESP_OK;
}
esp_err_t uart_wait_tx_fifo_empty(uart_port_t uart_num, TickType_t ticks_to_wait)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((p_uart_obj[uart_num]), "uart driver error");
BaseType_t res;
portTickType ticks_end = xTaskGetTickCount() + ticks_to_wait;
//Take tx_mutex
res = xSemaphoreTake(p_uart_obj[uart_num]->tx_mutex, (portTickType)ticks_to_wait);
if(res == pdFALSE) {
return ESP_ERR_TIMEOUT;
}
ticks_to_wait = ticks_end - xTaskGetTickCount();
//take 1st tx_done_sem
res = xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, (portTickType)ticks_to_wait);
if(res == pdFALSE) {
ESP_LOGE(UART_TAG, "take uart done sem error, should not get here.\n");
xSemaphoreGive(p_uart_obj[uart_num]->tx_done_sem);
xSemaphoreGive(p_uart_obj[uart_num]->tx_mutex);
return ESP_ERR_TIMEOUT;
}
ticks_to_wait = ticks_end - xTaskGetTickCount();
if(UART[uart_num]->status.txfifo_cnt == 0) {
xSemaphoreGive(p_uart_obj[uart_num]->tx_done_sem);
xSemaphoreGive(p_uart_obj[uart_num]->tx_mutex);
return ESP_OK;
}
uart_enable_intr_mask(uart_num, UART_TX_DONE_INT_ENA_M);
//take 2nd tx_done_sem, wait given from ISR
res = xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, (portTickType)ticks_to_wait);
if(res == pdFALSE) {
uart_disable_intr_mask(uart_num, UART_TX_DONE_INT_ENA_M);
xSemaphoreGive(p_uart_obj[uart_num]->tx_done_sem);
xSemaphoreGive(p_uart_obj[uart_num]->tx_mutex);
return ESP_ERR_TIMEOUT;
}
xSemaphoreGive(p_uart_obj[uart_num]->tx_done_sem);
xSemaphoreGive(p_uart_obj[uart_num]->tx_mutex);
return ESP_OK;
}
static esp_err_t uart_set_break(uart_port_t uart_num, int break_num)
{
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->idle_conf.tx_brk_num = break_num;
UART[uart_num]->conf0.txd_brk = 1;
UART[uart_num]->int_clr.tx_brk_done = 1;
UART[uart_num]->int_ena.tx_brk_done = 1;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
int uart_tx_chars(uart_port_t uart_num, char* buffer, uint32_t len)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((p_uart_obj[uart_num]), "uart driver error");
UART_CHECK(buffer, "buffer null");
if(len == 0) {
return 0;
}
xSemaphoreTake(p_uart_obj[uart_num]->tx_mutex, (portTickType)portMAX_DELAY);
int tx_len = uart_fill_fifo(uart_num, buffer, len);
xSemaphoreGive(p_uart_obj[uart_num]->tx_mutex);
return tx_len;
}
static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool brk_en, int brk_len)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((p_uart_obj[uart_num]), "uart driver error");
UART_CHECK(src, "buffer null");
if(size == 0) {
return 0;
}
//lock for uart_tx
xSemaphoreTake(p_uart_obj[uart_num]->tx_mutex, (portTickType)portMAX_DELAY);
size_t original_size = size;
while(size) {
//semaphore for tx_fifo available
if(pdTRUE == xSemaphoreTake(p_uart_obj[uart_num]->tx_fifo_sem, (portTickType)portMAX_DELAY)) {
size_t sent = uart_fill_fifo(uart_num, (char*) src, size);
if(sent < size) {
p_uart_obj[uart_num]->tx_waiting = true;
uart_enable_tx_intr(uart_num, 1, DEFAULT_EMPTY_THRESH);
}
size -= sent;
src += sent;
}
}
if(brk_en) {
uart_set_break(uart_num, brk_len);
xSemaphoreTake(p_uart_obj[uart_num]->tx_brk_sem, (portTickType)portMAX_DELAY);
}
xSemaphoreGive(p_uart_obj[uart_num]->tx_fifo_sem);
xSemaphoreGive(p_uart_obj[uart_num]->tx_mutex);
return original_size;
}
int uart_tx_all_chars(uart_port_t uart_num, const char* src, size_t size)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((p_uart_obj[uart_num]), "uart driver error");
UART_CHECK(src, "buffer null");
return uart_tx_all(uart_num, src, size, 0, 0);
}
int uart_tx_all_chars_with_break(uart_port_t uart_num, const char* src, size_t size, int brk_len)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((p_uart_obj[uart_num]), "uart driver error");
UART_CHECK((size > 0), "uart size error");
UART_CHECK((src), "uart data null");
UART_CHECK((brk_len > 0 && brk_len < 256), "break_num error");
return uart_tx_all(uart_num, src, size, 1, brk_len);
}
int uart_read_char(uart_port_t uart_num, TickType_t ticks_to_wait)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((p_uart_obj[uart_num]), "uart driver error");
uint8_t* data;
size_t size;
int val;
portTickType ticks_end = xTaskGetTickCount() + ticks_to_wait;
if(xSemaphoreTake(p_uart_obj[uart_num]->rx_sem,(portTickType)ticks_to_wait) != pdTRUE) {
return -1;
}
if(p_uart_obj[uart_num]->cur_remain == 0) {
ticks_to_wait = ticks_end - xTaskGetTickCount();
data = (uint8_t*) xRingbufferReceive(p_uart_obj[uart_num]->ring_buffer, &size, (portTickType) ticks_to_wait);
if(data) {
p_uart_obj[uart_num]->head_ptr = data;
p_uart_obj[uart_num]->rd_ptr = data;
p_uart_obj[uart_num]->cur_remain = size;
} else {
xSemaphoreGive(p_uart_obj[uart_num]->rx_sem);
return -1;
}
}
val = *(p_uart_obj[uart_num]->rd_ptr);
p_uart_obj[uart_num]->rd_ptr++;
p_uart_obj[uart_num]->cur_remain--;
if(p_uart_obj[uart_num]->cur_remain == 0) {
vRingbufferReturnItem(p_uart_obj[uart_num]->ring_buffer, p_uart_obj[uart_num]->head_ptr);
p_uart_obj[uart_num]->head_ptr = NULL;
p_uart_obj[uart_num]->rd_ptr = NULL;
if(p_uart_obj[uart_num]->buffer_full_flg) {
BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->ring_buffer, p_uart_obj[uart_num]->data_buf, p_uart_obj[uart_num]->data_len, 1);
if(res == pdTRUE) {
p_uart_obj[uart_num]->buffer_full_flg = false;
uart_enable_rx_intr(p_uart_obj[uart_num]->uart_num);
}
}
}
xSemaphoreGive(p_uart_obj[uart_num]->rx_sem);
return val;
}
int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickType_t ticks_to_wait)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((buf), "uart_num error");
UART_CHECK((p_uart_obj[uart_num]), "uart driver error");
uint8_t* data = NULL;
size_t size;
size_t copy_len = 0;
int len_tmp;
if(xSemaphoreTake(p_uart_obj[uart_num]->rx_sem,(portTickType)ticks_to_wait) != pdTRUE) {
return -1;
}
while(length) {
if(p_uart_obj[uart_num]->cur_remain == 0) {
data = (uint8_t*) xRingbufferReceive(p_uart_obj[uart_num]->ring_buffer, &size, (portTickType) ticks_to_wait);
if(data) {
p_uart_obj[uart_num]->head_ptr = data;
p_uart_obj[uart_num]->rd_ptr = data;
p_uart_obj[uart_num]->cur_remain = size;
} else {
xSemaphoreGive(p_uart_obj[uart_num]->rx_sem);
return copy_len;
}
}
if(p_uart_obj[uart_num]->cur_remain > length) {
len_tmp = length;
} else {
len_tmp = p_uart_obj[uart_num]->cur_remain;
}
memcpy(buf + copy_len, p_uart_obj[uart_num]->rd_ptr, len_tmp);
p_uart_obj[uart_num]->rd_ptr += len_tmp;
p_uart_obj[uart_num]->cur_remain -= len_tmp;
copy_len += len_tmp;
length -= len_tmp;
if(p_uart_obj[uart_num]->cur_remain == 0) {
vRingbufferReturnItem(p_uart_obj[uart_num]->ring_buffer, p_uart_obj[uart_num]->head_ptr);
p_uart_obj[uart_num]->head_ptr = NULL;
p_uart_obj[uart_num]->rd_ptr = NULL;
if(p_uart_obj[uart_num]->buffer_full_flg) {
BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->ring_buffer, p_uart_obj[uart_num]->data_buf, p_uart_obj[uart_num]->data_len, 1);
if(res == pdTRUE) {
p_uart_obj[uart_num]->buffer_full_flg = false;
uart_enable_rx_intr(p_uart_obj[uart_num]->uart_num);
}
}
}
}
xSemaphoreGive(p_uart_obj[uart_num]->rx_sem);
return copy_len;
}
esp_err_t uart_flush(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((p_uart_obj[uart_num]), "uart driver error");
uart_obj_t* p_uart = p_uart_obj[uart_num];
uint8_t* data;
size_t size;
//rx sem protect the ring buffer read related functions
xSemaphoreTake(p_uart->rx_sem, (portTickType)portMAX_DELAY);
while(true) {
if(p_uart->head_ptr) {
vRingbufferReturnItem(p_uart->ring_buffer, p_uart->head_ptr);
p_uart->rd_ptr = NULL;
p_uart->cur_remain = 0;
p_uart->head_ptr = NULL;
}
data = (uint8_t*) xRingbufferReceive(p_uart->ring_buffer, &size, (portTickType) 0);
if(data == NULL) {
break;
}
vRingbufferReturnItem(p_uart->ring_buffer, data);
}
p_uart->rd_ptr = NULL;
p_uart->cur_remain = 0;
p_uart->head_ptr = NULL;
xSemaphoreGive(p_uart->rx_sem);
uart_wait_tx_fifo_empty(uart_num, portMAX_DELAY);
uart_reset_fifo(uart_num);
return ESP_OK;
}
//-----------------------------------
//Should not enable hw flow control the debug print port.
//Use uart_tx_all_chars() as a thread-safe function to send data.
static int s_uart_print_nport = UART_NUM_0;
static void uart2_write_char(char chr)
{
uart_tx_all_chars(UART_NUM_2, (const char*)&chr, 1);
}
static void uart1_write_char(char chr)
{
uart_tx_all_chars(UART_NUM_1, (const char*)&chr, 1);
}
static void uart0_write_char(char chr)
{
uart_tx_all_chars(UART_NUM_0, (const char*)&chr, 1);
}
static void uart_ignore_char(char chr)
{
}
//Only effective to ets_printf function, not ESP_LOGX macro.
esp_err_t uart_set_print_port(uart_port_t uart_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error");
UART_CHECK((p_uart_obj[uart_num]), "UART driver error");
s_uart_print_nport = uart_num;
switch(s_uart_print_nport) {
case UART_NUM_0:
ets_install_putc1(uart0_write_char);
break;
case UART_NUM_1:
ets_install_putc1(uart1_write_char);
break;
case UART_NUM_2:
ets_install_putc1(uart2_write_char);
break;
case UART_NUM_MAX:
default:
ets_install_putc1(uart_ignore_char);
break;
}
return ESP_OK;
}
int uart_get_print_port()
{
return s_uart_print_nport;
}

1
components/esp32/include/esp_err.h
View file

@ -31,6 +31,7 @@ typedef int32_t esp_err_t;
#define ESP_ERR_NO_MEM 0x101
#define ESP_ERR_INVALID_ARG 0x102
#define ESP_ERR_INVALID_STATE 0x103
#define ESP_ERR_TIMEOUT 0x104
/**
* Macro which can be used to check the error code,

4
components/esp32/include/soc/uart_reg.h
View file

@ -18,8 +18,10 @@
#include "soc.h"
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: This register stores one byte data read by rx fifo.*/
#define UART_RXFIFO_RD_BYTE 0x000000FF

3
components/freertos/ringbuf.c
View file

@ -371,8 +371,7 @@ BaseType_t xRingbufferSendFromISR(RingbufHandle_t ringbuf, void *data, size_t da
//Does not fit in the remaining space in the ringbuffer.
write_succeeded=pdFALSE;
} else {
copyItemToRingbuf(rb, data, dataSize);
write_succeeded=pdTRUE;
write_succeeded = copyItemToRingbuf(rb, data, dataSize);
}
portEXIT_CRITICAL_ISR(&rb->mux);
if (write_succeeded) {