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Merge branch 'feature/esp32s2beta' into feature/esp32s2beta_update

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Angus Gratton 2019-08-13 17:16:44 +10:00 committed by Angus Gratton
commit 278c2f1aea
1 changed files with 10 additions and 27 deletions
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33
components/esp32s2beta/crosscore_int.c
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@ -38,9 +38,7 @@
#define REASON_FREQ_SWITCH BIT(1) #define REASON_FREQ_SWITCH BIT(1)
static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED; static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
static volatile uint32_t reason[ portNUM_PROCESSORS ]; static volatile uint32_t reason;
// TODO: crosscore_int: simplify for esp32s2beta - IDF-754
/* /*
ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
@ -53,15 +51,11 @@ static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
static void IRAM_ATTR esp_crosscore_isr(void *arg) { static void IRAM_ATTR esp_crosscore_isr(void *arg) {
uint32_t my_reason_val; uint32_t my_reason_val;
//A pointer to the correct reason array item is passed to this ISR. //A pointer to the correct reason item is passed to this ISR.
volatile uint32_t *my_reason=arg; volatile uint32_t *my_reason=arg;
//Clear the interrupt first. //Clear the interrupt first.
if (xPortGetCoreID()==0) {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0); DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
} else {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
}
//Grab the reason and clear it. //Grab the reason and clear it.
portENTER_CRITICAL_ISR(&reason_spinlock); portENTER_CRITICAL_ISR(&reason_spinlock);
my_reason_val=*my_reason; my_reason_val=*my_reason;
@ -80,33 +74,22 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
} }
} }
//Initialize the crosscore interrupt on this core. Call this once //Initialize the crosscore interrupt on this core.
//on each active core.
void esp_crosscore_int_init(void) { void esp_crosscore_int_init(void) {
portENTER_CRITICAL(&reason_spinlock); portENTER_CRITICAL(&reason_spinlock);
reason[xPortGetCoreID()]=0; reason = 0;
portEXIT_CRITICAL(&reason_spinlock); portEXIT_CRITICAL(&reason_spinlock);
esp_err_t err; ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason, NULL));
if (xPortGetCoreID()==0) {
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
} else {
err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
}
assert(err == ESP_OK);
} }
static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) { static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
assert(core_id<portNUM_PROCESSORS); assert(core_id<portNUM_PROCESSORS);
//Mark the reason we interrupt the other CPU //Mark the reason we interrupt the current CPU
portENTER_CRITICAL(&reason_spinlock); portENTER_CRITICAL(&reason_spinlock);
reason[core_id] |= reason_mask; reason |= reason_mask;
portEXIT_CRITICAL(&reason_spinlock); portEXIT_CRITICAL(&reason_spinlock);
//Poke the other CPU. //Poke the current CPU.
if (core_id==0) {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0); DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
} else {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
}
} }
void IRAM_ATTR esp_crosscore_int_send_yield(int core_id) void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)