From 2260c714e7b8c2fddbc1eeed27e85c33c67a4c0c Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 2 Mar 2017 20:51:37 +0800 Subject: [PATCH] add esp_chip_info API --- components/esp32/include/esp_system.h | 32 +++++++++++++++ components/esp32/system_api.c | 28 +++++++++++++ components/soc/esp32/include/soc/efuse_reg.h | 43 ++++++++++++++++---- 3 files changed, 95 insertions(+), 8 deletions(-) diff --git a/components/esp32/include/esp_system.h b/components/esp32/include/esp_system.h index 24eebb8b0..16f2a3234 100644 --- a/components/esp32/include/esp_system.h +++ b/components/esp32/include/esp_system.h @@ -209,6 +209,38 @@ const char* system_get_sdk_version(void) __attribute__ ((deprecated)); */ const char* esp_get_idf_version(void); + +/** + * @brief Chip models + */ +typedef enum { + CHIP_ESP32 = 1, //!< ESP32 +} esp_chip_model_t; + +/** + * Chip feature flags, used in esp_chip_info_t + */ +#define CHIP_FEATURE_EMB_FLASH BIT(0) +#define CHIP_FEATURE_WIFI_BGN BIT(1) +#define CHIP_FEATURE_BLE BIT(4) +#define CHIP_FEATURE_BT BIT(5) + +/** + * @brief The structure represents information about the chip + */ +typedef struct { + esp_chip_model_t model; //!< chip model, one of esp_chip_model_t + uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags + uint8_t cores; //!< number of CPU cores + uint8_t revision; //!< chip revision number +} esp_chip_info_t; + +/** + * @brief Fill an esp_chip_info_t structure with information about the chip + * @param[out] out_info structure to be filled + */ +void esp_chip_info(esp_chip_info_t* out_info); + #ifdef __cplusplus } #endif diff --git a/components/esp32/system_api.c b/components/esp32/system_api.c index ab271063e..13038f447 100644 --- a/components/esp32/system_api.c +++ b/components/esp32/system_api.c @@ -326,3 +326,31 @@ const char* esp_get_idf_version(void) return IDF_VER; } +static void get_chip_info_esp32(esp_chip_info_t* out_info) +{ + uint32_t reg = REG_READ(EFUSE_BLK0_RDATA3_REG); + memset(out_info, 0, sizeof(*out_info)); + if ((reg & EFUSE_RD_CHIP_VER_REV1_M) != 0) { + out_info->revision = 1; + } + if ((reg & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) { + out_info->cores = 2; + } else { + out_info->cores = 1; + } + out_info->features = CHIP_FEATURE_WIFI_BGN; + if ((reg & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) { + out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE; + } + if (((reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S) == + EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) { + out_info->features |= CHIP_FEATURE_EMB_FLASH; + } +} + +void esp_chip_info(esp_chip_info_t* out_info) +{ + // Only ESP32 is supported now, in the future call one of the + // chip-specific functions based on sdkconfig choice + return get_chip_info_esp32(out_info); +} diff --git a/components/soc/esp32/include/soc/efuse_reg.h b/components/soc/esp32/include/soc/efuse_reg.h index 291e3984e..b9ad20ee6 100644 --- a/components/soc/esp32/include/soc/efuse_reg.h +++ b/components/soc/esp32/include/soc/efuse_reg.h @@ -79,12 +79,27 @@ #define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 #define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) -/* EFUSE_RD_CHIP_VER_RESERVE : RO ;bitpos:[16:9] ;default: 8'b0 ; */ +/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: bit is set to 1 for rev1 silicon*/ +#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S)) +#define EFUSE_RD_CHIP_VER_REV1_V 0x1 +#define EFUSE_RD_CHIP_VER_REV1_S 15 +/* EFUSE_RD_CHIP_VER_RESERVE : R/W ;bitpos:[15:12] ;default: 3'b0 ; */ /*description: */ -#define EFUSE_RD_CHIP_VER_RESERVE 0x000000FF +#define EFUSE_RD_CHIP_VER_RESERVE 0x00000007 #define EFUSE_RD_CHIP_VER_RESERVE_M ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S)) -#define EFUSE_RD_CHIP_VER_RESERVE_V 0xFF -#define EFUSE_RD_CHIP_VER_RESERVE_S 9 +#define EFUSE_RD_CHIP_VER_RESERVE_V 0x7 +#define EFUSE_RD_CHIP_VER_RESERVE_S 12 +/* EFUSE_RD_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ +/*description: chip package */ +#define EFUSE_RD_CHIP_VER 0x00000007 +#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S)) +#define EFUSE_RD_CHIP_VER_PKG_V 0x7 +#define EFUSE_RD_CHIP_VER_PKG_S 9 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ /*description: read for SPI_pad_config_hd*/ #define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F @@ -297,12 +312,24 @@ #define EFUSE_WIFI_MAC_CRC_HIGH_S 0 #define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) -/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[16:9] ;default: 8'b0 ; */ +/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ /*description: */ -#define EFUSE_CHIP_VER_RESERVE 0x000000FF +#define EFUSE_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S)) +#define EFUSE_CHIP_VER_REV1_V 0x1 +#define EFUSE_CHIP_VER_REV1_S 15 +/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[15:12] ;default: 3'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_RESERVE 0x00000007 #define EFUSE_CHIP_VER_RESERVE_M ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S)) -#define EFUSE_CHIP_VER_RESERVE_V 0xFF -#define EFUSE_CHIP_VER_RESERVE_S 9 +#define EFUSE_CHIP_VER_RESERVE_V 0x7 +#define EFUSE_CHIP_VER_RESERVE_S 12 +/* EFUSE_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_PKG 0x00000007 +#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S)) +#define EFUSE_CHIP_VER_PKG_V 0x7 +#define EFUSE_CHIP_VER_PKG_S 9 /* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */ /*description: program for SPI_pad_config_hd*/ #define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F