From 208d993de12a73ab1e2fa088a39f098a15baa76b Mon Sep 17 00:00:00 2001 From: michael Date: Thu, 19 Apr 2018 12:47:29 +0800 Subject: [PATCH] test(spi_master): slightly modify the test --- components/driver/test/test_spi_master.c | 254 +++++++++++++---------- 1 file changed, 142 insertions(+), 112 deletions(-) diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c index da6d5a596..2871523fd 100644 --- a/components/driver/test/test_spi_master.c +++ b/components/driver/test/test_spi_master.c @@ -25,6 +25,35 @@ const static char TAG[] = "test_spi"; +#define SPI_BUS_TEST_DEFAULT_CONFIG() {\ + .miso_io_num=PIN_NUM_MISO, \ + .mosi_io_num=PIN_NUM_MOSI,\ + .sclk_io_num=PIN_NUM_CLK,\ + .quadwp_io_num=-1,\ + .quadhd_io_num=-1\ +} + +#define SPI_DEVICE_TEST_DEFAULT_CONFIG() {\ + .clock_speed_hz=10*1000*1000,\ + .mode=0,\ + .spics_io_num=PIN_NUM_CS,\ + .queue_size=16,\ + .pre_cb=NULL, \ + .cs_ena_pretrans = 0,\ + .cs_ena_posttrans = 0,\ +} + +//steal register definition from gpio.c +const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT]; +#define FUNC_SPI 1 +#define FUNC_GPIO 2 + +void gpio_output_sel(uint32_t gpio_num, int func, uint32_t signal_idx) +{ + PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); + GPIO.func_out_sel_cfg[gpio_num].func_sel=signal_idx; +} + static void check_spi_pre_n_for(int clk, int pre, int n) { esp_err_t ret; @@ -231,7 +260,7 @@ TEST_CASE("SPI Master test, interaction of multiple devs", "[spi][ignore]") { .clock_speed_hz=1000000, .duty_cycle_pos=128, .mode=0, - .spics_io_num=23, + .spics_io_num=23, .queue_size=3, }; spi_device_handle_t handle1=setup_spi_bus(80000, true); @@ -274,7 +303,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") spi_bus_config_t cfg; uint32_t flags_o; uint32_t flags_expected; - + ESP_LOGI(TAG, "test 6 native output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_NATIVE_PINS | SPICOMMON_BUSFLAG_QUAD; cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP, @@ -323,7 +352,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD; cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP, - .max_transfer_sz = 8, .flags = flags_expected}; + .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -338,7 +367,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO; cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = -1, .quadwp_io_num = -1, - .max_transfer_sz = 8, .flags = flags_expected}; + .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -386,14 +415,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - + ESP_LOGI(TAG, "check mosi flag..."); flags_expected = SPICOMMON_BUSFLAG_MOSI; cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - + ESP_LOGI(TAG, "check miso flag..."); flags_expected = SPICOMMON_BUSFLAG_MISO; cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = -1, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP, @@ -474,14 +503,32 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" } IRAM_ATTR static uint32_t data_iram[320]; -DRAM_ATTR static uint32_t data_dram[320]; +DRAM_ATTR static uint32_t data_dram[320]={0}; //force to place in code area. static const uint32_t data_drom[320] = {0}; -#define PIN_NUM_MISO 25 -#define PIN_NUM_MOSI 23 -#define PIN_NUM_CLK 19 -#define PIN_NUM_CS 22 + +#define HSPI_NATIVE_PIN_NUM_MISO 12 +#define HSPI_NATIVE_PIN_NUM_MOSI 13 +#define HSPI_NATIVE_PIN_NUM_CLK 14 +#define HSPI_NATIVE_PIN_NUM_CS 15 + +#define VSPI_NATIVE_PIN_NUM_MISO 19 +#define VSPI_NATIVE_PIN_NUM_MOSI 23 +#define VSPI_NATIVE_PIN_NUM_CLK 18 +#define VSPI_NATIVE_PIN_NUM_CS 5 + +#if 1 //HSPI +#define PIN_NUM_MISO HSPI_NATIVE_PIN_NUM_MISO +#define PIN_NUM_MOSI HSPI_NATIVE_PIN_NUM_MOSI +#define PIN_NUM_CLK HSPI_NATIVE_PIN_NUM_CLK +#define PIN_NUM_CS HSPI_NATIVE_PIN_NUM_CS +#elif 1 //VSPI +#define PIN_NUM_MISO VSPI_NATIVE_PIN_NUM_MISO +#define PIN_NUM_MOSI VSPI_NATIVE_PIN_NUM_MOSI +#define PIN_NUM_CLK VSPI_NATIVE_PIN_NUM_CLK +#define PIN_NUM_CS VSPI_NATIVE_PIN_NUM_CS +#endif #define PIN_NUM_DC 21 #define PIN_NUM_RST 18 @@ -541,7 +588,7 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") trans[4].rxlength = 8*4; trans[4].tx_buffer = data_drom; trans[4].flags = SPI_TRANS_USE_RXDATA; - + trans[5].length = 8*4; trans[5].flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA; @@ -562,13 +609,6 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") TEST_ASSERT(spi_bus_free(HSPI_HOST) == ESP_OK); } - -static inline void int_connect( uint32_t gpio, uint32_t sigo, uint32_t sigi ) -{ - gpio_matrix_out( gpio, sigo, false, false ); - gpio_matrix_in( gpio, sigi, false ); -} - //this part tests 3 DMA issues in master mode, full-duplex in IDF2.1 // 1. RX buffer not aligned (start and end) // 2. not setting rx_buffer @@ -581,7 +621,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") esp_err_t ret; spi_device_handle_t spi; spi_bus_config_t buscfg={ - .miso_io_num=PIN_NUM_MISO, + .miso_io_num=PIN_NUM_MOSI, .mosi_io_num=PIN_NUM_MOSI, .sclk_io_num=PIN_NUM_CLK, .quadwp_io_num=-1, @@ -592,7 +632,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") .mode=0, //SPI mode 0 .spics_io_num=PIN_NUM_CS, //CS pin .queue_size=7, //We want to be able to queue 7 transactions at a time - .pre_cb=NULL, + .pre_cb=NULL, }; //Initialize the SPI bus ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1); @@ -601,18 +641,18 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") ret=spi_bus_add_device(HSPI_HOST, &devcfg, &spi); TEST_ASSERT(ret==ESP_OK); - //do internal connection - int_connect( PIN_NUM_MOSI, HSPID_OUT_IDX, HSPIQ_IN_IDX ); + //connect MOSI to two devices breaks the output, fix it. + gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX); memset(rx_buf, 0x66, 320); - + for ( int i = 0; i < 8; i ++ ) { memset( rx_buf, 0x66, sizeof(rx_buf)); spi_transaction_t t = {}; t.length = 8*(i+1); t.rxlength = 0; - t.tx_buffer = tx_buf+2*i; + t.tx_buffer = tx_buf+2*i; t.rx_buffer = rx_buf + i; if ( i == 1 ) { @@ -621,7 +661,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") } else if ( i == 2 ) { //test rx length != tx_length t.rxlength = t.length - 8; - } + } spi_device_transmit( spi, &t ); for( int i = 0; i < 16; i ++ ) { @@ -633,11 +673,11 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") // no rx, skip check } else if ( i == 2 ) { //test rx length = tx length-1 - TEST_ASSERT( memcmp(t.tx_buffer, t.rx_buffer, t.length/8-1)==0 ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, t.rx_buffer, t.length/8-1 ); } else { //normal check - TEST_ASSERT( memcmp(t.tx_buffer, t.rx_buffer, t.length/8)==0 ); - } + TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, t.rx_buffer, t.length/8 ); + } } TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK); @@ -649,53 +689,25 @@ static const char SLAVE_TAG[] = "test_slave"; DRAM_ATTR static uint8_t master_send[] = {0x93, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43}; DRAM_ATTR static uint8_t slave_send[] = { 0xaa, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, 0x13, 0x57, 0x9b, 0xdf, 0x24, 0x68, 0xac, 0xe0 }; -static void master_init( spi_device_handle_t* spi, int mode, uint32_t speed) + +static void master_deinit(spi_device_handle_t spi) { - esp_err_t ret; - spi_bus_config_t buscfg={ - .miso_io_num=PIN_NUM_MISO, - .mosi_io_num=PIN_NUM_MOSI, - .sclk_io_num=PIN_NUM_CLK, - .quadwp_io_num=-1, - .quadhd_io_num=-1 - }; - spi_device_interface_config_t devcfg={ - .clock_speed_hz=speed, //currently only up to 4MHz for internel connect - .mode=mode, //SPI mode 0 - .spics_io_num=PIN_NUM_CS, //CS pin - .queue_size=16, //We want to be able to queue 7 transactions at a time - .pre_cb=NULL, - .cs_ena_pretrans = 0, - }; - //Initialize the SPI bus - ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1); - TEST_ASSERT(ret==ESP_OK); - //Attach the LCD to the SPI bus - ret=spi_bus_add_device(HSPI_HOST, &devcfg, spi); - TEST_ASSERT(ret==ESP_OK); + TEST_ESP_OK( spi_bus_remove_device(spi) ); + TEST_ESP_OK( spi_bus_free(HSPI_HOST) ); } -static void slave_init(int mode, int dma_chan) +#define SPI_SLAVE_TEST_DEFAULT_CONFIG() {\ + .mode=0,\ + .spics_io_num=PIN_NUM_CS,\ + .queue_size=3,\ + .flags=0,\ +} + +static void slave_pull_up(const spi_bus_config_t* cfg, int spics_io_num) { - //Configuration for the SPI bus - spi_bus_config_t buscfg={ - .mosi_io_num=PIN_NUM_MOSI, - .miso_io_num=PIN_NUM_MISO, - .sclk_io_num=PIN_NUM_CLK - }; - //Configuration for the SPI slave interface - spi_slave_interface_config_t slvcfg={ - .mode=mode, - .spics_io_num=PIN_NUM_CS, - .queue_size=3, - .flags=0, - }; - //Enable pull-ups on SPI lines so we don't detect rogue pulses when no master is connected. - gpio_set_pull_mode(PIN_NUM_MOSI, GPIO_PULLUP_ONLY); - gpio_set_pull_mode(PIN_NUM_CLK, GPIO_PULLUP_ONLY); - gpio_set_pull_mode(PIN_NUM_CS, GPIO_PULLUP_ONLY); - //Initialize SPI slave interface - TEST_ESP_OK( spi_slave_initialize(VSPI_HOST, &buscfg, &slvcfg, dma_chan) ); + gpio_set_pull_mode(cfg->mosi_io_num, GPIO_PULLUP_ENABLE); + gpio_set_pull_mode(cfg->sclk_io_num, GPIO_PULLUP_ENABLE); + gpio_set_pull_mode(spics_io_num, GPIO_PULLUP_ENABLE); } typedef struct { @@ -705,10 +717,12 @@ typedef struct { typedef struct { uint32_t len; + uint8_t* tx_start; uint8_t data[1]; } slave_rxdata_t; typedef struct { + spi_host_device_t spi; RingbufHandle_t data_received; QueueHandle_t data_to_send; } spi_slave_task_context_t; @@ -723,6 +737,7 @@ esp_err_t init_slave_context(spi_slave_task_context_t *context) if ( context->data_received == NULL ) { return ESP_ERR_NO_MEM; } + context->spi=VSPI_HOST; return ESP_OK; } @@ -736,12 +751,16 @@ void deinit_slave_context(spi_slave_task_context_t *context) context->data_received = NULL; } +/* The task requires a queue and a ringbuf, which should be initialized before task starts. + Send ``slave_txdata_t`` to the queue to make the task send data; + the task returns data got to the ringbuf, which should have sufficient size. +*/ static void task_slave(void* arg) { spi_slave_task_context_t* context = (spi_slave_task_context_t*) arg; QueueHandle_t queue = context->data_to_send; RingbufHandle_t ringbuf = context->data_received; - uint8_t recvbuf[320+4]; + uint8_t recvbuf[320+8]; slave_txdata_t txdata; ESP_LOGI( SLAVE_TAG, "slave up" ); @@ -749,18 +768,19 @@ static void task_slave(void* arg) while( 1 ) { xQueueReceive( queue, &txdata, portMAX_DELAY ); - ESP_LOGI( "test", "received: %p", txdata.start ); + ESP_LOGI( "test", "to send: %p", txdata.start ); spi_slave_transaction_t t = {}; t.length = txdata.len; t.tx_buffer = txdata.start; - t.rx_buffer = recvbuf+4; + t.rx_buffer = recvbuf+8; //loop until trans_len != 0 to skip glitches do { - TEST_ESP_OK( spi_slave_transmit( VSPI_HOST, &t, portMAX_DELAY ) ); + TEST_ESP_OK( spi_slave_transmit( context->spi, &t, portMAX_DELAY ) ); } while ( t.trans_len == 0 ); *(uint32_t*)recvbuf = t.trans_len; + *(uint8_t**)(recvbuf+4) = txdata.start; ESP_LOGI( SLAVE_TAG, "received: %d", t.trans_len ); - xRingbufferSend( ringbuf, recvbuf, 4+(t.trans_len+7)/8, portMAX_DELAY ); + xRingbufferSend( ringbuf, recvbuf, 8+(t.trans_len+7)/8, portMAX_DELAY ); } } @@ -775,16 +795,33 @@ TEST_CASE("SPI master variable cmd & addr test","[spi]") TEST_ASSERT( err == ESP_OK ); spi_device_handle_t spi; - //initial master, mode 0, 1MHz - master_init( &spi, 0, 1*1000*1000 ); - //initial slave, mode 0, no dma - slave_init(0, 0); - //do internal connection - int_connect( PIN_NUM_MOSI, HSPID_OUT_IDX, VSPIQ_IN_IDX ); - int_connect( PIN_NUM_MISO, VSPIQ_OUT_IDX, HSPID_IN_IDX ); - int_connect( PIN_NUM_CS, HSPICS0_OUT_IDX, VSPICS0_IN_IDX ); - int_connect( PIN_NUM_CLK, HSPICLK_OUT_IDX, VSPICLK_IN_IDX ); + //initial master, mode 0, 1MHz + spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); + TEST_ESP_OK(spi_bus_initialize(HSPI_HOST, &buscfg, 1)); + spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); + devcfg.clock_speed_hz = 1*1000*1000; //currently only up to 4MHz for internel connect + devcfg.mode = 0; + devcfg.cs_ena_posttrans = 2; + TEST_ESP_OK(spi_bus_add_device(HSPI_HOST, &devcfg, &spi)); + + //initial slave, mode 0, no dma + int dma_chan = 0; + int slave_mode = 0; + spi_bus_config_t slv_buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); + spi_slave_interface_config_t slvcfg=SPI_SLAVE_TEST_DEFAULT_CONFIG(); + slvcfg.mode = slave_mode; + //Enable pull-ups on SPI lines so we don't detect rogue pulses when no master is connected. + slave_pull_up(&buscfg, slvcfg.spics_io_num); + //Initialize SPI slave interface + TEST_ESP_OK( spi_slave_initialize(VSPI_HOST, &slv_buscfg, &slvcfg, dma_chan) ); + + + //connecting pins to two peripherals breaks the output, fix it. + gpio_output_sel(PIN_NUM_MOSI, FUNC_GPIO, HSPID_OUT_IDX); + gpio_output_sel(PIN_NUM_MISO, FUNC_GPIO, VSPIQ_OUT_IDX); + gpio_output_sel(PIN_NUM_CS, FUNC_GPIO, HSPICS0_OUT_IDX); + gpio_output_sel(PIN_NUM_CLK, FUNC_GPIO, HSPICLK_OUT_IDX); TaskHandle_t handle_slave; xTaskCreate( task_slave, "spi_slave", 4096, &slave_context, 0, &handle_slave); @@ -871,7 +908,7 @@ TEST_CASE("SPI master variable cmd & addr test","[spi]") handle_slave = 0; deinit_slave_context(&slave_context); - + TEST_ASSERT(spi_slave_free(VSPI_HOST) == ESP_OK); TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK); @@ -880,6 +917,9 @@ TEST_CASE("SPI master variable cmd & addr test","[spi]") ESP_LOGI(MASTER_TAG, "test passed."); } +/******************************************************************************** + * Test SPI transaction interval + ********************************************************************************/ #define RECORD_TIME_PREPARE() uint32_t __t1, __t2 #define RECORD_TIME_START() do {__t1 = xthal_get_ccount();}while(0) #define RECORD_TIME_END(p_time) do{__t2 = xthal_get_ccount(); *p_time = (__t2-__t1)/240;}while(0) @@ -887,21 +927,10 @@ TEST_CASE("SPI master variable cmd & addr test","[spi]") static void speed_setup(spi_device_handle_t* spi, bool use_dma) { esp_err_t ret; - spi_bus_config_t buscfg={ - .miso_io_num=PIN_NUM_MISO, - .mosi_io_num=PIN_NUM_MOSI, - .sclk_io_num=PIN_NUM_CLK, - .quadwp_io_num=-1, - .quadhd_io_num=-1 - }; - spi_device_interface_config_t devcfg={ - .clock_speed_hz=10*1000*1000, //currently only up to 4MHz for internel connect - .mode=0, //SPI mode 0 - .spics_io_num=PIN_NUM_CS, //CS pin - .queue_size=8, //We want to be able to queue 7 transactions at a time - .pre_cb=NULL, - .cs_ena_pretrans = 0, - }; + spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); + spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); + devcfg.queue_size=8; //We want to be able to queue 7 transactions at a time + //Initialize the SPI bus and the device to test ret=spi_bus_initialize(HSPI_HOST, &buscfg, (use_dma?1:0)); TEST_ASSERT(ret==ESP_OK); @@ -930,12 +959,12 @@ static void sorted_array_insert(uint32_t* array, int* size, uint32_t item) TEST_CASE("spi_speed","[spi]") { - RECORD_TIME_PREPARE(); + RECORD_TIME_PREPARE(); uint32_t t_flight; //to get rid of the influence of randomly interrupts, we measured the performance by median value uint32_t t_flight_sorted[TEST_TIMES]; int t_flight_num = 0; - + spi_device_handle_t spi; const bool use_dma = true; WORD_ALIGNED_ATTR spi_transaction_t trans = { @@ -948,37 +977,38 @@ TEST_CASE("spi_speed","[spi]") //first time introduces a device switch, which costs more time. we skip this spi_device_transmit(spi, &trans); - + //record flight time by isr, with DMA t_flight_num = 0; for (int i = 0; i < TEST_TIMES; i++) { RECORD_TIME_START(); spi_device_transmit(spi, &trans); - RECORD_TIME_END(&t_flight); + RECORD_TIME_END(&t_flight); sorted_array_insert(t_flight_sorted, &t_flight_num, t_flight); } TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING, "%d us", t_flight_sorted[(TEST_TIMES+1)/2]); for (int i = 0; i < TEST_TIMES; i++) { ESP_LOGI(TAG, "%d", t_flight_sorted[i]); } - + speed_deinit(spi); speed_setup(&spi, !use_dma); - + //first time introduces a device switch, which costs more time. we skip this spi_device_transmit(spi, &trans); - + //record flight time by isr, without DMA t_flight_num = 0; for (int i = 0; i < TEST_TIMES; i++) { RECORD_TIME_START(); spi_device_transmit(spi, &trans); - RECORD_TIME_END(&t_flight); + RECORD_TIME_END(&t_flight); sorted_array_insert(t_flight_sorted, &t_flight_num, t_flight); } TEST_PERFORMANCE_LESS_THAN( SPI_PER_TRANS_NO_POLLING_NO_DMA, "%d us", t_flight_sorted[(TEST_TIMES+1)/2]); for (int i = 0; i < TEST_TIMES; i++) { ESP_LOGI(TAG, "%d", t_flight_sorted[i]); - } - speed_deinit(spi); + } + speed_deinit(spi); } +