diff --git a/components/driver/include/driver/mcpwm.h b/components/driver/include/driver/mcpwm.h
new file mode 100644
index 000000000..2a4433fce
--- /dev/null
+++ b/components/driver/include/driver/mcpwm.h
@@ -0,0 +1,709 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_MCPWM_H_
+#define _DRIVER_MCPWM_H_
+
+#include "esp_err.h"
+#include "soc/soc.h"
+#include "driver/gpio.h"
+#include "driver/periph_ctrl.h"
+#include "esp_intr.h"
+#include "esp_intr_alloc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief IO signals for MCPWM
+ *        6 MCPWM output pins that generate PWM signals
+ *        3 MCPWM fault input pins to detect faults like overcurrent, overvoltage, etc
+ *        3 MCPWM sync input pins to synchronize MCPWM outputs signals
+ *        3 MCPWM capture input pin to capture hall sell signal to measure time
+ */
+typedef enum {
+    MCPWM0A = 0,        /*!<PWM0A output pin*/
+    MCPWM0B,            /*!<PWM0B output pin*/
+    MCPWM1A,            /*!<PWM1A output pin*/
+    MCPWM1B,            /*!<PWM1B output pin*/
+    MCPWM2A,            /*!<PWM2A output pin*/
+    MCPWM2B,            /*!<PWM2B output pin*/
+    MCPWM_SYNC_0,       /*!<SYNC0  input pin*/
+    MCPWM_SYNC_1,       /*!<SYNC1  input pin*/
+    MCPWM_SYNC_2,       /*!<SYNC2  input pin*/
+    MCPWM_FAULT_0,      /*!<FAULT0 input pin*/
+    MCPWM_FAULT_1,      /*!<FAULT1 input pin*/
+    MCPWM_FAULT_2,      /*!<FAULT2 input pin*/
+    MCPWM_CAP_0 = 84,   /*!<CAP0   input pin*/
+    MCPWM_CAP_1,        /*!<CAP1   input pin*/
+    MCPWM_CAP_2,        /*!<CAP2   input pin*/
+} mcpwm_io_signals_t;
+
+/**
+ * @brief MCPWM pin number for
+ *
+ */
+typedef struct {
+    int mcpwm0a_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm0b_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm1a_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm1b_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm2a_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm2b_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm_sync0_in_num;    /*!<SYNC0  in pin*/
+    int mcpwm_sync1_in_num;    /*!<SYNC1  in pin*/
+    int mcpwm_sync2_in_num;    /*!<SYNC2  in pin*/
+    int mcpwm_fault0_in_num;   /*!<FAULT0 in pin*/
+    int mcpwm_fault1_in_num;   /*!<FAULT1 in pin*/
+    int mcpwm_fault2_in_num;   /*!<FAULT2 in pin*/
+    int mcpwm_cap0_in_num;     /*!<CAP0   in pin*/
+    int mcpwm_cap1_in_num;     /*!<CAP1   in pin*/
+    int mcpwm_cap2_in_num;     /*!<CAP2   in pin*/
+} mcpwm_pin_config_t;
+
+/**
+ * @brief Select MCPWM unit
+ */
+typedef enum {
+    MCPWM_UNIT_0 = 0,  /*!<MCPWM unit0 selected*/
+    MCPWM_UNIT_1,      /*!<MCPWM unit1 selected*/
+    MCPWM_UNIT_MAX,    /*!<Num of MCPWM units on ESP32*/
+} mcpwm_unit_t;
+
+/**
+ * @brief Select MCPWM timer
+ */
+typedef enum {
+    MCPWM_TIMER_0 = 0,  /*!<Select MCPWM timer0*/
+    MCPWM_TIMER_1,      /*!<Select MCPWM timer1*/
+    MCPWM_TIMER_2,      /*!<Select MCPWM timer2*/
+    MCPWM_TIMER_MAX,    /*!<Num of MCPWM timers on ESP32*/
+} mcpwm_timer_t;
+
+/**
+ * @brief Select MCPWM operator
+ */
+typedef enum {
+    MCPWM_OPR_A = 0,  /*!<Select MCPWMXA, where 'X' is timer number*/
+    MCPWM_OPR_B,      /*!<Select MCPWMXB, where 'X' is timer number*/
+    MCPWM_OPR_MAX,    /*!<Num of operators to each timer of MCPWM*/
+} mcpwm_operator_t;
+
+/**
+ * @brief Select type of MCPWM counter
+ */
+typedef enum {
+    MCPWM_UP_COUNTER = 1,   /*!<For asymmetric MCPWM*/
+    MCPWM_DOWN_COUNTER,     /*!<For asymmetric MCPWM*/
+    MCPWM_UP_DOWN_COUNTER,  /*!<For symmetric MCPWM, frequency is half of MCPWM frequency set*/
+    MCPWM_COUNTER_MAX,      /*!<Maximum counter mode*/
+} mcpwm_counter_type_t;
+
+/**
+ * @brief Select type of MCPWM duty cycle mode
+ */
+typedef enum {
+    MCPWM_DUTY_MODE_0 = 0, /*!<Active high duty, i.e. duty cycle proportional to high time for asymmetric MCPWM*/
+    MCPWM_DUTY_MODE_1,     /*!<Active low duty,  i.e. duty cycle proportional to low  time for asymmetric MCPWM, out of phase(inverted) MCPWM*/
+    MCPWM_DUTY_MODE_MAX,   /*!<Num of duty cycle modes*/
+} mcpwm_duty_type_t;
+
+/**
+ * @brief MCPWM carrier oneshot mode, in this mode the width of the first pulse of carrier can be programmed
+ */
+typedef enum {
+    MCPWM_ONESHOT_MODE_DIS = 0,  /*!<Enable oneshot mode*/
+    MCPWM_ONESHOT_MODE_EN,       /*!<Disable oneshot mode*/
+} mcpwm_carrier_os_t;
+
+/**
+ * @brief MCPWM carrier output inversion, high frequency carrier signal active with MCPWM signal is high
+ */
+typedef enum {
+    MCPWM_CARRIER_OUT_IVT_DIS = 0,  /*!<Enable  carrier output inversion*/
+    MCPWM_CARRIER_OUT_IVT_EN,       /*!<Disable carrier output inversion*/
+} mcpwm_carrier_out_ivt_t;
+
+/**
+ * @brief MCPWM select sync signal input
+ */
+typedef enum {
+    MCPWM_SELECT_SYNC0 = 4,  /*!<Select SYNC0 as input*/
+    MCPWM_SELECT_SYNC1,      /*!<Select SYNC1 as input*/
+    MCPWM_SELECT_SYNC2,      /*!<Select SYNC2 as input*/
+} mcpwm_sync_signal_t;
+
+/**
+ * @brief MCPWM select fault signal input
+ */
+typedef enum {
+    MCPWM_SELECT_F0 = 0,  /*!<Select F0 as input*/
+    MCPWM_SELECT_F1,      /*!<Select F1 as input*/
+    MCPWM_SELECT_F2,      /*!<Select F2 as input*/
+} mcpwm_fault_signal_t;
+
+/**
+ * @brief MCPWM select triggering level of fault signal
+ */
+typedef enum {
+    MCPWM_LOW_LEVEL_TGR = 0,  /*!<Fault condition occurs when fault input signal goes from high to low, currently not supported*/
+    MCPWM_HIGH_LEVEL_TGR,     /*!<Fault condition occurs when fault input signal goes low to high*/
+} mcpwm_fault_input_level_t;
+
+/**
+ * @brief MCPWM select action to be taken on MCPWMXA when fault occurs
+ */
+typedef enum {
+    MCPWM_NO_CHANGE_IN_MCPWMXA = 0,  /*!<No change in MCPWMXA output*/
+    MCPWM_FORCE_MCPWMXA_LOW,         /*!<Make MCPWMXA output low*/
+    MCPWM_FORCE_MCPWMXA_HIGH,        /*!<Make MCPWMXA output high*/
+    MCPWM_TOG_MCPWMXA,               /*!<Make MCPWMXA output toggle*/
+} mcpwm_action_on_pwmxa_t;
+
+/**
+ * @brief MCPWM select action to be taken on MCPWMxB when fault occurs
+ */
+typedef enum {
+    MCPWM_NO_CHANGE_IN_MCPWMXB = 0,  /*!<No change in MCPWMXB output*/
+    MCPWM_FORCE_MCPWMXB_LOW,         /*!<Make MCPWMXB output low*/
+    MCPWM_FORCE_MCPWMXB_HIGH,        /*!<Make MCPWMXB output high*/
+    MCPWM_TOG_MCPWMXB,               /*!<Make MCPWMXB output toggle*/
+} mcpwm_action_on_pwmxb_t;
+
+/**
+ * @brief MCPWM select capture signal input
+ */
+typedef enum {
+    MCPWM_SELECT_CAP0 = 0, /*!<Select CAP0 as input*/
+    MCPWM_SELECT_CAP1,     /*!<Select CAP1 as input*/
+    MCPWM_SELECT_CAP2,     /*!<Select CAP2 as input*/
+} mcpwm_capture_signal_t;
+
+/**
+ * @brief MCPWM select capture starts from which edge
+ */
+typedef enum {
+    MCPWM_NEG_EDGE = 0,  /*!<Capture starts from negative edge*/
+    MCPWM_POS_EDGE,      /*!<Capture starts from positive edge*/
+} mcpwm_capture_on_edge_t;
+
+/**
+ * @brief MCPWM deadtime types, used to generate deadtime, RED refers to rising edge delay and FED refers to falling edge delay
+ */
+typedef enum {
+    MCPWM_BYPASS_RED = 0,               /*!<MCPWMXA = no change, MCPWMXB = falling edge delay*/
+    MCPWM_BYPASS_FED,                   /*!<MCPWMXA = rising edge delay, MCPWMXB = no change*/
+    MCPWM_ACTIVE_HIGH_MODE,             /*!<MCPWMXA = rising edge delay,  MCPWMXB = falling edge delay*/
+    MCPWM_ACTIVE_LOW_MODE,              /*!<MCPWMXA = compliment of rising edge delay,  MCPWMXB = compliment of falling edge delay*/
+    MCPWM_ACTIVE_HIGH_COMPLIMENT_MODE,  /*!<MCPWMXA = rising edge delay,  MCPWMXB = compliment of falling edge delay*/
+    MCPWM_ACTIVE_LOW_COMPLIMENT_MODE,   /*!<MCPWMXA = compliment of rising edge delay,  MCPWMXB = falling edge delay*/
+    MCPWM_ACTIVE_RED_FED_FROM_PWMXA,    /*!<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXA*/
+    MCPWM_ACTIVE_RED_FED_FROM_PWMXB,    /*!<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXB*/
+    MCPWM_DEADTIME_TYPE_MAX,
+} mcpwm_deadtime_type_t;
+
+/**
+ * @brief MCPWM config structure
+ */
+typedef struct {
+    uint32_t frequency;              /*!<Set frequency of MCPWM in Hz*/
+    float cmpr_a;                    /*!<Set % duty cycle for operator a(MCPWMXA), i.e for 62.3% duty cycle, duty_a = 62.3*/
+    float cmpr_b;                    /*!<Set % duty cycle for operator b(MCPWMXB), i.e for 48% duty cycle, duty_b = 48.0*/
+    mcpwm_duty_type_t duty_mode;     /*!<Set type of duty cycle*/
+    mcpwm_counter_type_t counter_mode;  /*!<Set  type of MCPWM counter*/
+} mcpwm_config_t;
+
+/**
+ * @brief MCPWM config carrier structure
+ */
+typedef struct {
+    uint8_t carrier_period;                 /*!<Set carrier period = (carrier_period + 1)*800ns, carrier_period should be < 16*/
+    uint8_t carrier_duty;                   /*!<Set carrier duty cycle, carrier_duty should be less then 8(increment every 12.5%)*/
+    uint8_t pulse_width_in_os;              /*!<Set pulse width of first pulse in one shot mode = (carrier period)*(pulse_width_in_os + 1), should be less then 16*/
+    mcpwm_carrier_os_t carrier_os_mode;        /*!<Enable or disable carrier oneshot mode*/
+    mcpwm_carrier_out_ivt_t carrier_ivt_mode;  /*!<Invert output of carrier*/
+} mcpwm_carrier_config_t;
+
+
+/**
+ * @brief This function initializes each gpio signal for MCPWM
+ *        @note
+ *        This function initializes one gpio at a time.
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param io_signal set MCPWM signals, each MCPWM unit has 6 output(MCPWMXA, MCPWMXB) and 9 input(SYNC_X, FAULT_X, CAP_X)
+ *                  'X' is timer_num(0-2)
+ * @param gpio_num set this to configure gpio for MCPWM, if you want to use gpio16, gpio_num = 16
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal, int gpio_num);
+
+/**
+ * @brief Initialize MCPWM gpio structure
+ *        @note
+ *        This function can be used to initialize more then one gpio at a time.
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param mcpwm_pin MCPWM pin structure
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_pin);
+
+/**
+ * @brief Initialize MCPWM parameters
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param mcpwm_conf configure structure mcpwm_config_t
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_init( mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_config_t  *mcpwm_conf);
+
+/**
+ * @brief Set frequency(in Hz) of MCPWM timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param frequency set the frequency in Hz of each timer
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint32_t frequency);
+
+/**
+ * @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB)
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'X' is timer number selected
+ * @param duty set duty cycle in %(i.e for 62.3% duty cycle, duty = 62.3) of each operator
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, float duty);
+
+/**
+ * @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB) in us
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+ * @param duty set duty value in microseconds of each operator
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_duty_in_us(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, uint32_t duty);
+
+/**
+ * @brief Set duty either active high or active low(out of phase/inverted)
+ *        @note
+ *        Call this function every time after mcpwm_set_signal_high or mcpwm_set_signal_low to resume with previously set duty cycle
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+ * @param duty_num set active low or active high duty type
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_duty_type(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, mcpwm_duty_type_t duty_num);
+
+/**
+* @brief Get frequency of timer
+*
+* @param mcpwm_num set MCPWM unit(0-1)
+* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+*
+* @return
+*     - frequency of timer
+*/
+uint32_t mcpwm_get_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Get duty cycle of each operator
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+ *
+ * @return
+ *     - duty cycle in % of each operator(56.7 means duty is 56.7%)
+ */
+float mcpwm_get_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
+
+/**
+ * @brief Use this function to set MCPWM signal high
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_signal_high(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
+
+/**
+ * @brief Use this function to set MCPWM signal low
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_signal_low(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
+/**
+ * @brief Start MCPWM signal on timer 'x'
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_start(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Start MCPWM signal on timer 'x'
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_stop(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief  Initialize carrier configuration
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_conf configure structure mcpwm_carrier_config_t
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_carrier_config_t *carrier_conf);
+
+/**
+* @brief Enable MCPWM carrier submodule, for respective timer
+*
+* @param mcpwm_num set MCPWM unit(0-1)
+* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+*
+* @return
+*     - ESP_OK Success
+*     - ESP_ERR_INVALID_ARG Parameter error
+*/
+esp_err_t mcpwm_carrier_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Disable MCPWM carrier submodule, for respective timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Set period of carrier
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_period set the carrier period of each timer, carrier period = (carrier_period + 1)*800ns
+ *                    (carrier_period <= 15)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_set_period(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t carrier_period);
+
+/**
+ * @brief Set duty_cycle of carrier
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_duty set duty_cycle of carrier , carrier duty cycle = carrier_duty*12.5%
+ *                  (chop_duty <= 7)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_set_duty_cycle(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t carrier_duty);
+
+/**
+ * @brief Enable and set width of first pulse in carrier oneshot mode
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param pulse_width set pulse width of first pulse in oneshot mode, width = (carrier period)*(pulse_width +1)
+ *                    (pulse_width <= 15)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_oneshot_mode_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t pulse_width);
+
+/**
+ * @brief Disable oneshot mode, width of first pulse = carrier period
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_oneshot_mode_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Enable or disable carrier output inversion
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_ivt_mode enable or disable carrier output inversion
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_output_invert(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
+                                      mcpwm_carrier_out_ivt_t carrier_ivt_mode);
+
+/**
+ * @brief Enable and initialize deadtime for each MCPWM timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param dt_mode set deadtime mode
+ * @param red set rising edge delay = red*100ns
+ * @param fed set rising edge delay = fed*100ns
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_deadtime_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_deadtime_type_t dt_mode,
+                                uint32_t red, uint32_t fed);
+
+/**
+ * @brief Disable deadtime on MCPWM timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_deadtime_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Initialize fault submodule, currently low level triggering not supported
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param intput_level set fault signal level, which will cause fault to occur
+ * @param fault_sig set the fault Pin, which needs to be enabled
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t intput_level, mcpwm_fault_signal_t fault_sig);
+
+/**
+ * @brief Set oneshot mode on fault detection, once fault occur in oneshot mode reset is required to resume MCPWM signals
+ *        @note
+ *        currently low level triggering not supported
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param fault_sig set the fault Pin, which needs to be enabled for oneshot mode
+ * @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle
+ * @param action_on_pwmxb action to be taken on MCPWMXB when fault occurs, either no change or high or low or toggle
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_set_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_fault_signal_t fault_sig,
+                                       mcpwm_action_on_pwmxa_t action_on_pwmxa, mcpwm_action_on_pwmxb_t action_on_pwmxb);
+
+/**
+ * @brief Set cycle-by-cycle mode on fault detection, once fault occur in cyc mode MCPWM signal resumes as soon as fault signal becomes inactive
+ *        @note
+ *        currently low level triggering not supported
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param fault_sig set the fault Pin, which needs to be enabled for cyc mode
+ * @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle
+ * @param action_on_pwmxb action to be taken on MCPWMXB when fault occurs, either no change or high or low or toggle
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_set_cyc_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_fault_signal_t fault_sig,
+                                   mcpwm_action_on_pwmxa_t action_on_pwmxa, mcpwm_action_on_pwmxb_t action_on_pwmxb);
+
+/**
+ * @brief Disable fault signal
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param fault_sig fault pin, which needs to be disabled
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_sig);
+
+/**
+ * @brief Initialize capture submodule
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param cap_edge set capture edge, BIT(0) - negative edge, BIT(1) - positive edge
+ * @param cap_sig capture Pin, which needs to be enabled
+ * @param num_of_pulse count time between rising/falling edge between 2 *(pulses mentioned), counter uses APB_CLK
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+
+esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig, mcpwm_capture_on_edge_t cap_edge,
+                               uint32_t num_of_pulse);
+
+/**
+ * @brief Disable capture signal
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param cap_sig capture Pin, which needs to be disabled
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
+
+/**
+ * @brief Get capture value
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param cap_sig capture pin on which value is to be measured
+ *
+ * @return
+ *     Captured value
+ */
+uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
+
+/**
+ * @brief Get edge of capture signal
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param cap_sig capture pin of whose edge is to be determined
+ *
+ * @return
+ *     Capture signal edge: 1 - positive edge, 2 - negtive edge
+ */
+uint32_t mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
+
+/**
+ * @brief Initialize sync submodule
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param sync_sig set the fault Pin, which needs to be enabled
+ * @param phase_val phase value in 1/1000(for 86.7%, phase_val = 867) which timer moves to on sync signal
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_sync_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_sync_signal_t sync_sig,
+                            uint32_t phase_val);
+
+/**
+ * @brief Disable sync submodule on given timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_sync_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Register MCPWM interrupt handler, the handler is an ISR.
+ *        the handler will be attached to the same CPU core that this function is running on.
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param fn interrupt handler function.
+ * @param arg user-supplied argument passed to the handler function.
+ * @param intr_alloc_flags flags used to allocate the interrupt. One or multiple (ORred)
+ *        ESP_INTR_FLAG_* values. see esp_intr_alloc.h for more info.
+ * @param arg parameter for handler function
+ * @param handle pointer to return handle. If non-NULL, a handle for the interrupt will
+ *        be returned here.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Function pointer error.
+ */
+esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *arg, int intr_alloc_flags, intr_handle_t *handle);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*_DRIVER_MCPWM_H_*/
diff --git a/components/driver/mcpwm.c b/components/driver/mcpwm.c
new file mode 100644
index 000000000..109b07bea
--- /dev/null
+++ b/components/driver/mcpwm.c
@@ -0,0 +1,733 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdio.h>
+#include "esp_log.h"
+#include "esp_err.h"
+#include "esp_intr.h"
+#include "esp_intr_alloc.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+#include "freertos/xtensa_api.h"
+#include "freertos/task.h"
+#include "soc/mcpwm_reg.h"
+#include "soc/mcpwm_struct.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+#include "driver/mcpwm.h"
+#include "driver/periph_ctrl.h"
+
+static mcpwm_dev_t *MCPWM[2] = {&MCPWM0, &MCPWM1};
+static const char *MCPWM_TAG = "MCPWM";
+static portMUX_TYPE mcpwm_spinlock = portMUX_INITIALIZER_UNLOCKED;
+#define MCPWM_CHECK(a, str, ret_val) if (!(a)) {                       \
+    ESP_LOGE(MCPWM_TAG,"%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, str);    \
+    return (ret_val);                                  \
+    }
+
+#define MCPWM_UNIT_NUM_ERROR    "MCPWM UNIT NUM ERROR"
+#define MCPWM_TIMER_ERROR       "MCPWM TIMER NUM ERROR"
+#define MCPWM_PARAM_ADDR_ERROR  "MCPWM PARAM ADDR ERROR"
+#define MCPWM_DUTY_TYPE_ERROR   "MCPWM DUTY TYPE ERROR"
+#define MCPWM_GPIO_ERROR        "MCPWM GPIO NUM ERROR"
+#define MCPWM_OP_ERROR          "MCPWM OPERATOR ERROR"
+#define MCPWM_DB_ERROR          "MCPWM DEADTIME TYPE ERROR"
+
+#define MCPWM_BASE_CLK (2 * APB_CLK_FREQ)   //2*APB_CLK_FREQ 160Mhz
+#define MCPWM_CLK_PRESCL 15       //MCPWM clock prescale 
+#define TIMER_CLK_PRESCALE 9      //MCPWM timer prescales
+#define MCPWM_CLK (MCPWM_BASE_CLK/(MCPWM_CLK_PRESCL +1))
+#define MCPWM_PIN_IGNORE    (-1)
+#define OFFSET_FOR_GPIO_IDX_1  6
+#define OFFSET_FOR_GPIO_IDX_2 75
+
+esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal, int gpio_num)
+{
+    if (gpio_num == MCPWM_PIN_IGNORE) {
+        //IGNORE
+        return ESP_OK;
+    }
+
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK((GPIO_IS_VALID_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG);
+
+    periph_module_enable(PERIPH_PWM0_MODULE + mcpwm_num);
+    PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
+    bool mcpwm_gpio_sig = (io_signal <= MCPWM2B);
+    if (mcpwm_num == MCPWM_UNIT_0) {
+        if (mcpwm_gpio_sig) {
+            MCPWM_CHECK((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG);
+            gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
+            gpio_matrix_out(gpio_num, PWM0_OUT0A_IDX + io_signal, 0, 0);
+        } else {
+            gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
+            gpio_matrix_in(gpio_num, PWM0_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_1, 0);
+        }
+    } else { //MCPWM_UNIT_1
+        if (mcpwm_gpio_sig) {
+            MCPWM_CHECK((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG);
+            gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
+            gpio_matrix_out(gpio_num, PWM1_OUT0A_IDX + io_signal, 0, 0);
+        } else if (io_signal >= MCPWM_SYNC_0 && io_signal < MCPWM_FAULT_2) {
+            gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
+            gpio_matrix_in(gpio_num, PWM1_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_1, 0);
+        } else {
+            gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
+            gpio_matrix_in(gpio_num, PWM1_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_2, 0);
+        }
+    }
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_pin)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    mcpwm_gpio_init(mcpwm_num, MCPWM0A, mcpwm_pin->mcpwm0a_out_num);    //MCPWM0A
+    mcpwm_gpio_init(mcpwm_num, MCPWM0B, mcpwm_pin->mcpwm0b_out_num);    //MCPWM0B
+    mcpwm_gpio_init(mcpwm_num, MCPWM1A, mcpwm_pin->mcpwm1a_out_num);    //MCPWM1A
+    mcpwm_gpio_init(mcpwm_num, MCPWM1B, mcpwm_pin->mcpwm1b_out_num);    //MCPWM1B
+    mcpwm_gpio_init(mcpwm_num, MCPWM2A, mcpwm_pin->mcpwm2a_out_num);    //MCPWM2A
+    mcpwm_gpio_init(mcpwm_num, MCPWM2B, mcpwm_pin->mcpwm2b_out_num);    //MCPWM2B
+    mcpwm_gpio_init(mcpwm_num, MCPWM_SYNC_0,  mcpwm_pin->mcpwm_sync0_in_num);   //SYNC0
+    mcpwm_gpio_init(mcpwm_num, MCPWM_SYNC_1,  mcpwm_pin->mcpwm_sync1_in_num);   //SYNC1
+    mcpwm_gpio_init(mcpwm_num, MCPWM_SYNC_2,  mcpwm_pin->mcpwm_sync2_in_num);   //SYNC2
+    mcpwm_gpio_init(mcpwm_num, MCPWM_FAULT_0, mcpwm_pin->mcpwm_fault0_in_num);  //FAULT0
+    mcpwm_gpio_init(mcpwm_num, MCPWM_FAULT_0, mcpwm_pin->mcpwm_fault1_in_num);  //FAULT1
+    mcpwm_gpio_init(mcpwm_num, MCPWM_FAULT_0, mcpwm_pin->mcpwm_fault2_in_num);  //FAULT2
+    mcpwm_gpio_init(mcpwm_num, MCPWM_CAP_0,   mcpwm_pin->mcpwm_cap0_in_num);    //CAP0
+    mcpwm_gpio_init(mcpwm_num, MCPWM_CAP_1,   mcpwm_pin->mcpwm_cap1_in_num);    //CAP1
+    mcpwm_gpio_init(mcpwm_num, MCPWM_CAP_2,   mcpwm_pin->mcpwm_cap2_in_num);    //CAP2
+    return ESP_OK;
+}
+
+
+esp_err_t mcpwm_start(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->timer[timer_num].mode.start = 2;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_stop(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->timer[timer_num].mode.start = 0;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_set_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint32_t frequency)
+{
+    uint32_t mcpwm_num_of_pulse;
+    uint32_t previous_period;
+    uint32_t set_duty_a, set_duty_b;
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    mcpwm_num_of_pulse = MCPWM_CLK / (frequency * (TIMER_CLK_PRESCALE + 1));
+    previous_period = MCPWM[mcpwm_num]->timer[timer_num].period.period;
+    MCPWM[mcpwm_num]->timer[timer_num].period.prescale = TIMER_CLK_PRESCALE;
+    MCPWM[mcpwm_num]->timer[timer_num].period.period = mcpwm_num_of_pulse;
+    MCPWM[mcpwm_num]->timer[timer_num].period.upmethod = 0;
+    set_duty_a = (((MCPWM[mcpwm_num]->channel[timer_num].cmpr_value[0].cmpr_val) * mcpwm_num_of_pulse) / previous_period);
+    set_duty_b = (((MCPWM[mcpwm_num]->channel[timer_num].cmpr_value[1].cmpr_val) * mcpwm_num_of_pulse) / previous_period);
+    MCPWM[mcpwm_num]->channel[timer_num].cmpr_value[0].cmpr_val = set_duty_a;
+    MCPWM[mcpwm_num]->channel[timer_num].cmpr_value[1].cmpr_val = set_duty_b;
+    MCPWM[mcpwm_num]->channel[timer_num].cmpr_cfg.a_upmethod = 0;
+    MCPWM[mcpwm_num]->channel[timer_num].cmpr_cfg.b_upmethod = 0;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_set_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, float duty)
+{
+    uint32_t set_duty;
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(op_num < MCPWM_OPR_MAX, MCPWM_OP_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    set_duty = (MCPWM[mcpwm_num]->timer[timer_num].period.period) * (duty) / 100;
+    MCPWM[mcpwm_num]->channel[timer_num].cmpr_value[op_num].cmpr_val = set_duty;
+    MCPWM[mcpwm_num]->channel[timer_num].cmpr_cfg.a_upmethod = BIT(0);
+    MCPWM[mcpwm_num]->channel[timer_num].cmpr_cfg.b_upmethod = BIT(0);
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+esp_err_t mcpwm_set_duty_in_us(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, uint32_t duty)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(op_num < MCPWM_OPR_MAX, MCPWM_OP_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].cmpr_value[op_num].cmpr_val = duty;
+    MCPWM[mcpwm_num]->channel[timer_num].cmpr_cfg.a_upmethod = BIT(0);
+    MCPWM[mcpwm_num]->channel[timer_num].cmpr_cfg.b_upmethod = BIT(0);
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+esp_err_t mcpwm_set_duty_type(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num,
+                              mcpwm_duty_type_t duty_num)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(op_num < MCPWM_OPR_MAX, MCPWM_OP_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(duty_num < MCPWM_DUTY_MODE_MAX, MCPWM_DUTY_TYPE_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    if (op_num == MCPWM_OPR_A) {
+        if (MCPWM[mcpwm_num]->timer[timer_num].mode.mode == MCPWM_UP_COUNTER) {
+            if (duty_num == MCPWM_DUTY_MODE_1) {
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utea = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utep = 0;
+            } else {   //MCPWM_DUTY_MODE_0
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utea = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utep = 0;
+            }
+        } else if (MCPWM[mcpwm_num]->timer[timer_num].mode.mode == MCPWM_DOWN_COUNTER) {
+            if (duty_num == MCPWM_DUTY_MODE_1) {
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtep = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtea = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtez = 0;
+            } else {   //MCPWM_DUTY_MODE_0
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtep = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtea = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtez = 0;
+            }
+        } else {   //Timer count up-down
+            if (duty_num == MCPWM_DUTY_MODE_1) {
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utea = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtea = 1;
+            } else {   //MCPWM_DUTY_MODE_0
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utea = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtea = 2;
+            }
+        }
+    }
+    if (op_num == MCPWM_OPR_B) {
+        if (MCPWM[mcpwm_num]->timer[timer_num].mode.mode == MCPWM_UP_COUNTER) {
+            if (duty_num == MCPWM_DUTY_MODE_1) {
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].uteb = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utep = 0;
+            } else {   //MCPWM_DUTY_MODE_0
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].uteb = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utep = 0;
+            }
+        } else if (MCPWM[mcpwm_num]->timer[timer_num].mode.mode == MCPWM_DOWN_COUNTER) {
+            if (duty_num == MCPWM_DUTY_MODE_1) {
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtep = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dteb = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtez = 0;
+            } else {    //MCPWM_DUTY_MODE_0
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtep = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dteb = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtez = 0;
+            }
+        } else {    //Timer count up-down
+            if (duty_num == MCPWM_DUTY_MODE_1) {
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].uteb = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dteb = 1;
+            } else {    //MCPWM_DUTY_MODE_0
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 2;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].uteb = 1;
+                MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dteb = 2;
+            }
+        }
+    }
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_config_t *mcpwm_conf)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    periph_module_enable(PERIPH_PWM0_MODULE + mcpwm_num);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->clk_cfg.prescale = MCPWM_CLK_PRESCL;
+    mcpwm_set_frequency(mcpwm_num, timer_num, mcpwm_conf->frequency);
+    MCPWM[mcpwm_num]->timer[timer_num].mode.mode = mcpwm_conf ->counter_mode;
+    mcpwm_set_duty(mcpwm_num, timer_num, 0, mcpwm_conf->cmpr_a);
+    mcpwm_set_duty(mcpwm_num, timer_num, 1, mcpwm_conf->cmpr_b);
+    mcpwm_set_duty_type(mcpwm_num, timer_num, 0, mcpwm_conf->duty_mode);
+    mcpwm_set_duty_type(mcpwm_num, timer_num, 1, mcpwm_conf->duty_mode);
+    mcpwm_start(mcpwm_num, timer_num);
+    MCPWM[mcpwm_num]->timer_sel.operator0_sel = 0;
+    MCPWM[mcpwm_num]->timer_sel.operator1_sel = 1;
+    MCPWM[mcpwm_num]->timer_sel.operator2_sel = 2;
+    MCPWM[mcpwm_num]->update_cfg.global_up_en = 1;
+    MCPWM[mcpwm_num]->update_cfg.global_force_up = 1;
+    MCPWM[mcpwm_num]->update_cfg.global_force_up = 0;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+uint32_t mcpwm_get_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
+{
+    uint32_t frequency;
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    frequency = MCPWM_CLK / ((MCPWM[mcpwm_num]->timer[timer_num].period.period) * (TIMER_CLK_PRESCALE + 1));
+    return frequency;
+}
+
+float mcpwm_get_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num)
+{
+    float duty;
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(op_num < MCPWM_OPR_MAX, MCPWM_OP_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    duty = (MCPWM[mcpwm_num]->channel[timer_num].cmpr_value[op_num].cmpr_val) * 100 / (MCPWM[mcpwm_num]->timer[timer_num].period.period);
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return duty;
+}
+
+esp_err_t mcpwm_set_signal_high(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(op_num < MCPWM_OPR_MAX, MCPWM_OP_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    if (op_num == MCPWM_OPR_A) {
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 2;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utea = 2;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utep = 2;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtez = 2;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtea = 2;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtep = 2;
+    } else {    //MCPWM_OPR_B
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 2;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].uteb = 2;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utep = 2;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtez = 2;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dteb = 2;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtep = 2;
+    }
+
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_set_signal_low(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(op_num < MCPWM_OPR_MAX, MCPWM_OP_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    if (op_num == 0) {
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utea = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utep = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtez = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtea = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtep = 1;
+    } if (op_num == 1) {
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utez = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].uteb = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].utep = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtez = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dteb = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].generator[op_num].dtep = 1;
+    }
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_carrier_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].carrier_cfg.en = 1;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_carrier_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].carrier_cfg.en = 0;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_carrier_set_period(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t carrier_period)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].carrier_cfg.prescale = carrier_period;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+esp_err_t mcpwm_carrier_set_duty_cycle(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t carrier_duty)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].carrier_cfg.duty = carrier_duty;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_carrier_enable_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t pulse_width)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].carrier_cfg.oshtwth = pulse_width;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_carrier_disable_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].carrier_cfg.oshtwth = 0;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_carrier_output_invert(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
+                                      mcpwm_carrier_out_ivt_t carrier_ivt_mode)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].carrier_cfg.out_invert = carrier_ivt_mode;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_carrier_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_carrier_config_t *carrier_conf)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    mcpwm_carrier_enable(mcpwm_num, timer_num);
+    mcpwm_carrier_set_period(mcpwm_num, timer_num, carrier_conf->carrier_period);
+    mcpwm_carrier_set_duty_cycle(mcpwm_num, timer_num, carrier_conf->carrier_duty);
+    if (carrier_conf->carrier_os_mode == MCPWM_ONESHOT_MODE_EN) {
+        mcpwm_carrier_enable_oneshot_mode(mcpwm_num, timer_num, carrier_conf->pulse_width_in_os);
+    } else {
+        mcpwm_carrier_disable_oneshot_mode(mcpwm_num, timer_num);
+    }
+    mcpwm_carrier_output_invert(mcpwm_num, timer_num, carrier_conf->carrier_ivt_mode);
+    MCPWM[mcpwm_num]->channel[timer_num].carrier_cfg.in_invert = 0;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_deadtime_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_deadtime_type_t dt_mode,
+                                uint32_t red, uint32_t fed)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(dt_mode < MCPWM_DEADTIME_TYPE_MAX, MCPWM_DB_ERROR, ESP_ERR_INVALID_ARG );
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_upmethod = BIT(0);
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_upmethod = BIT(0);
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.clk_sel = 0;
+    MCPWM[mcpwm_num]->channel[timer_num].db_red_cfg.red = red;
+    MCPWM[mcpwm_num]->channel[timer_num].db_fed_cfg.fed = fed;
+    switch (dt_mode) {
+    case MCPWM_BYPASS_RED:
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outbypass = 0;      //S0
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.a_outbypass = 1;      //S1
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_outinvert = 0;    //S2
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_outinvert = 0;    //S3
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_insel = 0;        //S4
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_insel = 1;        //S5
+        break;
+    case MCPWM_BYPASS_FED:
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outbypass = 1;      //S0
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.a_outbypass = 0;      //S1
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_outinvert = 0;    //S2
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_outinvert = 0;    //S3
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_insel = 0;        //S4
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_insel = 0;        //S5
+        break;
+    case MCPWM_ACTIVE_HIGH_MODE:
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outbypass = 0;      //S0
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.a_outbypass = 0;      //S1
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_outinvert = 0;    //S2
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_outinvert = 0;    //S3
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_insel = 0;        //S4
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_insel = 1;        //S5
+        break;
+    case MCPWM_ACTIVE_LOW_MODE:
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outbypass = 0;      //S0
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.a_outbypass = 0;      //S1
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_outinvert = 1;    //S2
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_outinvert = 1;    //S3
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_insel = 0;        //S4
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_insel = 1;        //S5
+        break;
+    case MCPWM_ACTIVE_HIGH_COMPLIMENT_MODE:
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outbypass = 0;      //S0
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.a_outbypass = 0;      //S1
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_outinvert = 0;    //S2
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_outinvert = 1;    //S3
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_insel = 0;        //S4
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_insel = 1;        //S5
+        break;
+    case MCPWM_ACTIVE_LOW_COMPLIMENT_MODE:
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outbypass = 0;      //S0
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.a_outbypass = 0;      //S1
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_outinvert = 1;    //S2
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_outinvert = 0;    //S3
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_insel = 1;        //S4
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_insel = 0;        //S5
+        break;
+    case MCPWM_ACTIVE_RED_FED_FROM_PWMXA:
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outbypass = 0;      //S0
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_outinvert = 0;    //S3
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_insel = 1;        //S4
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.a_outswap = 1;        //S6
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outswap = 0;        //S7
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.deb_mode = 1;         //S8
+        break;
+    case MCPWM_ACTIVE_RED_FED_FROM_PWMXB:
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outbypass = 0;      //S0
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_outinvert = 0;    //S3
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_insel = 0;        //S4
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.a_outswap = 1;        //S6
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outswap = 0;        //S7
+        MCPWM[mcpwm_num]->channel[timer_num].db_cfg.deb_mode = 1;         //S8
+        break;
+    default :
+        break;
+    }
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_deadtime_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outbypass = 1;      //S0
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.a_outbypass = 1;      //S1
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_outinvert = 0;    //S2
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_outinvert = 0;    //S3
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.red_insel = 0;        //S4
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.fed_insel = 0;        //S5
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.a_outswap = 0;        //S6
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.b_outswap = 0;        //S7
+    MCPWM[mcpwm_num]->channel[timer_num].db_cfg.deb_mode = 0;         //S8
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t intput_level, mcpwm_fault_signal_t fault_sig)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    switch (fault_sig) {
+    case MCPWM_SELECT_F0:
+        MCPWM[mcpwm_num]->fault_detect.f0_en = 1;
+        MCPWM[mcpwm_num]->fault_detect.f0_pole = intput_level;
+        break;
+    case MCPWM_SELECT_F1:
+        MCPWM[mcpwm_num]->fault_detect.f1_en = 1;
+        MCPWM[mcpwm_num]->fault_detect.f1_pole = intput_level;
+        break;
+    case MCPWM_SELECT_F2:
+        MCPWM[mcpwm_num]->fault_detect.f2_en = 1;
+        MCPWM[mcpwm_num]->fault_detect.f2_pole = intput_level;
+
+        break;
+    default :
+        break;
+    }
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_sig)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    if (fault_sig == MCPWM_SELECT_F0) {
+        MCPWM[mcpwm_num]->fault_detect.f0_en = 0;
+    } else if (fault_sig == MCPWM_SELECT_F1) {
+        MCPWM[mcpwm_num]->fault_detect.f1_en = 0;
+    } else {   //MCPWM_SELECT_F2
+        MCPWM[mcpwm_num]->fault_detect.f2_en = 0;
+    }
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_fault_set_cyc_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_fault_signal_t fault_sig,
+                                   mcpwm_action_on_pwmxa_t action_on_pwmxa, mcpwm_action_on_pwmxb_t action_on_pwmxb)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->channel[timer_num].tz_cfg1.cbcpulse = BIT(0);
+    if (fault_sig == MCPWM_SELECT_F0) {
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f0_cbc = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f0_ost = 0;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_cbc_d = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_cbc_u = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_cbc_d = action_on_pwmxb;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_cbc_u = action_on_pwmxb;
+    } else if (fault_sig == MCPWM_SELECT_F1) {
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f1_cbc = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f1_ost = 0;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_cbc_d = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_cbc_u = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_cbc_d = action_on_pwmxb;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_cbc_u = action_on_pwmxb;
+    } else {  //MCPWM_SELECT_F2
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f2_cbc = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f2_ost = 0;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_cbc_d = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_cbc_u = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_cbc_d = action_on_pwmxb;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_cbc_u = action_on_pwmxb;
+    }
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_fault_set_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_fault_signal_t fault_sig,
+                                       mcpwm_action_on_pwmxa_t action_on_pwmxa, mcpwm_action_on_pwmxb_t action_on_pwmxb)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    if (fault_sig == MCPWM_SELECT_F0) {
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f0_ost = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f0_cbc = 0;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_ost_d = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_ost_u = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_ost_d = action_on_pwmxb;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_ost_u = action_on_pwmxb;
+    } else if (fault_sig == MCPWM_SELECT_F1) {
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f1_ost = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f1_cbc = 0;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_ost_d = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_ost_u = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_ost_d = action_on_pwmxb;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_ost_u = action_on_pwmxb;
+    } else {   //MCPWM_SELECT_F2
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f2_ost = 1;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.f2_cbc = 0;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_ost_d = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.a_ost_u = action_on_pwmxa;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_ost_d = action_on_pwmxb;
+        MCPWM[mcpwm_num]->channel[timer_num].tz_cfg0.b_ost_u = action_on_pwmxb;
+    }
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig, mcpwm_capture_on_edge_t cap_edge,
+                               uint32_t num_of_pulse)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->cap_timer_cfg.timer_en = 1;
+    MCPWM[mcpwm_num]->cap_cfg_ch[cap_sig].en = 1;
+    MCPWM[mcpwm_num]->cap_cfg_ch[cap_sig].mode = (1 << cap_edge);
+    MCPWM[mcpwm_num]->cap_cfg_ch[cap_sig].prescale = num_of_pulse;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->cap_cfg_ch[cap_sig].en = 0;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    return MCPWM[mcpwm_num]->cap_val_ch[cap_sig];
+}
+
+uint32_t mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    if (cap_sig == MCPWM_SELECT_CAP0) {
+        return ( MCPWM[mcpwm_num]->cap_status.cap0_edge + 1);
+    } else if (cap_sig == MCPWM_SELECT_CAP1) {
+        return (MCPWM[mcpwm_num]->cap_status.cap1_edge + 1);
+    } else {   //MCPWM_SELECT_CAP2
+        return (MCPWM[mcpwm_num]->cap_status.cap2_edge + 1);
+    }
+    return 0;
+}
+
+esp_err_t mcpwm_sync_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_sync_signal_t sync_sig,
+                            uint32_t phase_val)
+{
+    uint32_t set_phase;
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    set_phase = (MCPWM[mcpwm_num]->timer[timer_num].period.period) * (phase_val) / 1000;
+    MCPWM[mcpwm_num]->timer[timer_num].sync.timer_phase = set_phase;
+    if (timer_num == MCPWM_TIMER_0) {
+        MCPWM[mcpwm_num]->timer_synci_cfg.t0_in_sel = sync_sig;
+    } else if (timer_num == MCPWM_TIMER_1) {
+        MCPWM[mcpwm_num]->timer_synci_cfg.t1_in_sel = sync_sig;
+    } else {   //MCPWM_TIMER_2
+        MCPWM[mcpwm_num]->timer_synci_cfg.t2_in_sel = sync_sig;
+    }
+    MCPWM[mcpwm_num]->timer[timer_num].sync.out_sel = 0;
+    MCPWM[mcpwm_num]->timer[timer_num].sync.in_en = 1;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t mcpwm_sync_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
+{
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(timer_num < MCPWM_TIMER_MAX, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&mcpwm_spinlock);
+    MCPWM[mcpwm_num]->timer[timer_num].sync.in_en = 0;
+    portEXIT_CRITICAL(&mcpwm_spinlock);
+    return ESP_OK;
+}
+esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *arg, int intr_alloc_flags, intr_handle_t *handle)
+{
+    esp_err_t ret;
+    MCPWM_CHECK(mcpwm_num < MCPWM_UNIT_MAX, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
+    MCPWM_CHECK(fn != NULL, MCPWM_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
+    ret = esp_intr_alloc((ETS_PWM0_INTR_SOURCE + mcpwm_num), intr_alloc_flags, fn, arg, handle);
+    return ret;
+}
diff --git a/components/esp32/ld/esp32.peripherals.ld b/components/esp32/ld/esp32.peripherals.ld
index 8d8d4e8b1..79becfc92 100644
--- a/components/esp32/ld/esp32.peripherals.ld
+++ b/components/esp32/ld/esp32.peripherals.ld
@@ -12,11 +12,13 @@ PROVIDE ( RMT = 0x3ff56000 );
 PROVIDE ( RMTMEM = 0x3ff56800 );
 PROVIDE ( PCNT = 0x3ff57000 );
 PROVIDE ( LEDC = 0x3ff59000 );
+PROVIDE ( MCPWM0 = 0x3ff5E000 );
 PROVIDE ( TIMERG0 = 0x3ff5F000 );
 PROVIDE ( TIMERG1 = 0x3ff60000 );
 PROVIDE ( SPI2 = 0x3ff64000 );
 PROVIDE ( SPI3 = 0x3ff65000 );
 PROVIDE ( I2C1 = 0x3ff67000 );
+PROVIDE ( MCPWM1 = 0x3ff6C000 );
 PROVIDE ( I2S1 = 0x3ff6D000 );
 PROVIDE ( UART2 = 0x3ff6E000 );
 PROVIDE ( SDMMC = 0x3ff68000 );
diff --git a/components/soc/esp32/include/soc/mcpwm_reg.h b/components/soc/esp32/include/soc/mcpwm_reg.h
new file mode 100644
index 000000000..1dce94d46
--- /dev/null
+++ b/components/soc/esp32/include/soc/mcpwm_reg.h
@@ -0,0 +1,3028 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_MCPWM_REG_H_
+#define _SOC_MCPWM_REG_H_
+#include "soc.h"
+
+#define REG_MCPWM_BASE(i)               (DR_REG_PWM_BASE + i * (0xE000))
+#define MCPWM_CLK_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0000)
+/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
+#define MCPWM_CLK_PRESCALE  0x000000FF
+#define MCPWM_CLK_PRESCALE_M  ((MCPWM_CLK_PRESCALE_V)<<(MCPWM_CLK_PRESCALE_S))
+#define MCPWM_CLK_PRESCALE_V  0xFF
+#define MCPWM_CLK_PRESCALE_S  0
+
+#define MCPWM_TIMER0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0004)
+/* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: Update method for active reg of PWM timer0 period  0: immediate
+  1: TEZ  2: sync  3: TEZ or sync. TEZ here and below means timer equal zero event*/
+#define MCPWM_TIMER0_PERIOD_UPMETHOD  0x00000003
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  ((MCPWM_TIMER0_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER0_PERIOD_UPMETHOD_S))
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x3
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+/* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
+/*description: Period shadow reg of PWM timer0*/
+#define MCPWM_TIMER0_PERIOD  0x0000FFFF
+#define MCPWM_TIMER0_PERIOD_M  ((MCPWM_TIMER0_PERIOD_V)<<(MCPWM_TIMER0_PERIOD_S))
+#define MCPWM_TIMER0_PERIOD_V  0xFFFF
+#define MCPWM_TIMER0_PERIOD_S  8
+/* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
+#define MCPWM_TIMER0_PRESCALE  0x000000FF
+#define MCPWM_TIMER0_PRESCALE_M  ((MCPWM_TIMER0_PRESCALE_V)<<(MCPWM_TIMER0_PRESCALE_S))
+#define MCPWM_TIMER0_PRESCALE_V  0xFF
+#define MCPWM_TIMER0_PRESCALE_S  0
+
+#define MCPWM_TIMER0_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0008)
+/* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: PWM timer0 working mode  0: freeze  1: increase mod  2: decrease
+ mod  3: up-down mod*/
+#define MCPWM_TIMER0_MOD  0x00000003
+#define MCPWM_TIMER0_MOD_M  ((MCPWM_TIMER0_MOD_V)<<(MCPWM_TIMER0_MOD_S))
+#define MCPWM_TIMER0_MOD_V  0x3
+#define MCPWM_TIMER0_MOD_S  3
+/* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: PWM timer0 start and stop control. 0: stop @ TEZ  1: stop @ TEP
+  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP. TEP here and below means timer equal period event*/
+#define MCPWM_TIMER0_START  0x00000007
+#define MCPWM_TIMER0_START_M  ((MCPWM_TIMER0_START_V)<<(MCPWM_TIMER0_START_S))
+#define MCPWM_TIMER0_START_V  0x7
+#define MCPWM_TIMER0_START_S  0
+
+#define MCPWM_TIMER0_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x000c)
+/* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
+/*description: Phase for timer reload on sync event*/
+#define MCPWM_TIMER0_PHASE  0x0001FFFF
+#define MCPWM_TIMER0_PHASE_M  ((MCPWM_TIMER0_PHASE_V)<<(MCPWM_TIMER0_PHASE_S))
+#define MCPWM_TIMER0_PHASE_V  0x1FFFF
+#define MCPWM_TIMER0_PHASE_S  4
+/* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: PWM timer0 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+#define MCPWM_TIMER0_SYNCO_SEL  0x00000003
+#define MCPWM_TIMER0_SYNCO_SEL_M  ((MCPWM_TIMER0_SYNCO_SEL_V)<<(MCPWM_TIMER0_SYNCO_SEL_S))
+#define MCPWM_TIMER0_SYNCO_SEL_V  0x3
+#define MCPWM_TIMER0_SYNCO_SEL_S  2
+/* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Toggling this bit will trigger a software sync*/
+#define MCPWM_TIMER0_SYNC_SW  (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_M  (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_V  0x1
+#define MCPWM_TIMER0_SYNC_SW_S  1
+/* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: When set   timer reload with phase on sync input event is enabled*/
+#define MCPWM_TIMER0_SYNCI_EN  (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_M  (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_V  0x1
+#define MCPWM_TIMER0_SYNCI_EN_S  0
+
+#define MCPWM_TIMER0_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0010)
+/* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Current PWM timer0 counter direction  0: increment 1: decrement*/
+#define MCPWM_TIMER0_DIRECTION  (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_M  (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_V  0x1
+#define MCPWM_TIMER0_DIRECTION_S  16
+/* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Current PWM timer0 counter value*/
+#define MCPWM_TIMER0_VALUE  0x0000FFFF
+#define MCPWM_TIMER0_VALUE_M  ((MCPWM_TIMER0_VALUE_V)<<(MCPWM_TIMER0_VALUE_S))
+#define MCPWM_TIMER0_VALUE_V  0xFFFF
+#define MCPWM_TIMER0_VALUE_S  0
+
+#define MCPWM_TIMER1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0014)
+/* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: Update method for active reg of PWM timer1 period  0: immediate
+  1: TEZ  2: sync  3: TEZ or sync*/
+#define MCPWM_TIMER1_PERIOD_UPMETHOD  0x00000003
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  ((MCPWM_TIMER1_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER1_PERIOD_UPMETHOD_S))
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x3
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
+/* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
+/*description: Period shadow reg of PWM timer1*/
+#define MCPWM_TIMER1_PERIOD  0x0000FFFF
+#define MCPWM_TIMER1_PERIOD_M  ((MCPWM_TIMER1_PERIOD_V)<<(MCPWM_TIMER1_PERIOD_S))
+#define MCPWM_TIMER1_PERIOD_V  0xFFFF
+#define MCPWM_TIMER1_PERIOD_S  8
+/* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1)*/
+#define MCPWM_TIMER1_PRESCALE  0x000000FF
+#define MCPWM_TIMER1_PRESCALE_M  ((MCPWM_TIMER1_PRESCALE_V)<<(MCPWM_TIMER1_PRESCALE_S))
+#define MCPWM_TIMER1_PRESCALE_V  0xFF
+#define MCPWM_TIMER1_PRESCALE_S  0
+
+#define MCPWM_TIMER1_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0018)
+/* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: PWM timer1 working mode  0: freeze  1: increase mod  2: decrease
+ mod  3: up-down mod*/
+#define MCPWM_TIMER1_MOD  0x00000003
+#define MCPWM_TIMER1_MOD_M  ((MCPWM_TIMER1_MOD_V)<<(MCPWM_TIMER1_MOD_S))
+#define MCPWM_TIMER1_MOD_V  0x3
+#define MCPWM_TIMER1_MOD_S  3
+/* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: PWM timer1 start and stop control. 0: stop @ TEZ  1: stop @ TEP
+  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP.*/
+#define MCPWM_TIMER1_START  0x00000007
+#define MCPWM_TIMER1_START_M  ((MCPWM_TIMER1_START_V)<<(MCPWM_TIMER1_START_S))
+#define MCPWM_TIMER1_START_V  0x7
+#define MCPWM_TIMER1_START_S  0
+
+#define MCPWM_TIMER1_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x001c)
+/* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
+/*description: Phase for timer reload on sync event*/
+#define MCPWM_TIMER1_PHASE  0x0001FFFF
+#define MCPWM_TIMER1_PHASE_M  ((MCPWM_TIMER1_PHASE_V)<<(MCPWM_TIMER1_PHASE_S))
+#define MCPWM_TIMER1_PHASE_V  0x1FFFF
+#define MCPWM_TIMER1_PHASE_S  4
+/* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: PWM timer1 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+#define MCPWM_TIMER1_SYNCO_SEL  0x00000003
+#define MCPWM_TIMER1_SYNCO_SEL_M  ((MCPWM_TIMER1_SYNCO_SEL_V)<<(MCPWM_TIMER1_SYNCO_SEL_S))
+#define MCPWM_TIMER1_SYNCO_SEL_V  0x3
+#define MCPWM_TIMER1_SYNCO_SEL_S  2
+/* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Toggling this bit will trigger a software sync*/
+#define MCPWM_TIMER1_SYNC_SW  (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_M  (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_V  0x1
+#define MCPWM_TIMER1_SYNC_SW_S  1
+/* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: When set   timer reload with phase on sync input event is enabled*/
+#define MCPWM_TIMER1_SYNCI_EN  (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_M  (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_V  0x1
+#define MCPWM_TIMER1_SYNCI_EN_S  0
+
+#define MCPWM_TIMER1_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0020)
+/* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Current PWM timer1 counter direction  0: increment 1: decrement*/
+#define MCPWM_TIMER1_DIRECTION  (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_M  (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_V  0x1
+#define MCPWM_TIMER1_DIRECTION_S  16
+/* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Current PWM timer1 counter value*/
+#define MCPWM_TIMER1_VALUE  0x0000FFFF
+#define MCPWM_TIMER1_VALUE_M  ((MCPWM_TIMER1_VALUE_V)<<(MCPWM_TIMER1_VALUE_S))
+#define MCPWM_TIMER1_VALUE_V  0xFFFF
+#define MCPWM_TIMER1_VALUE_S  0
+
+#define MCPWM_TIMER2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0024)
+/* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: Update method for active reg of PWM timer2 period  0: immediate
+  1: TEZ  2: sync  3: TEZ or sync*/
+#define MCPWM_TIMER2_PERIOD_UPMETHOD  0x00000003
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  ((MCPWM_TIMER2_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER2_PERIOD_UPMETHOD_S))
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x3
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
+/* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
+/*description: Period shadow reg of PWM timer2*/
+#define MCPWM_TIMER2_PERIOD  0x0000FFFF
+#define MCPWM_TIMER2_PERIOD_M  ((MCPWM_TIMER2_PERIOD_V)<<(MCPWM_TIMER2_PERIOD_S))
+#define MCPWM_TIMER2_PERIOD_V  0xFFFF
+#define MCPWM_TIMER2_PERIOD_S  8
+/* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1)*/
+#define MCPWM_TIMER2_PRESCALE  0x000000FF
+#define MCPWM_TIMER2_PRESCALE_M  ((MCPWM_TIMER2_PRESCALE_V)<<(MCPWM_TIMER2_PRESCALE_S))
+#define MCPWM_TIMER2_PRESCALE_V  0xFF
+#define MCPWM_TIMER2_PRESCALE_S  0
+
+#define MCPWM_TIMER2_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0028)
+/* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: PWM timer2 working mode  0: freeze  1: increase mod  2: decrease
+ mod  3: up-down mod*/
+#define MCPWM_TIMER2_MOD  0x00000003
+#define MCPWM_TIMER2_MOD_M  ((MCPWM_TIMER2_MOD_V)<<(MCPWM_TIMER2_MOD_S))
+#define MCPWM_TIMER2_MOD_V  0x3
+#define MCPWM_TIMER2_MOD_S  3
+/* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: PWM timer2 start and stop control. 0: stop @ TEZ  1: stop @ TEP
+  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP.*/
+#define MCPWM_TIMER2_START  0x00000007
+#define MCPWM_TIMER2_START_M  ((MCPWM_TIMER2_START_V)<<(MCPWM_TIMER2_START_S))
+#define MCPWM_TIMER2_START_V  0x7
+#define MCPWM_TIMER2_START_S  0
+
+#define MCPWM_TIMER2_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x002c)
+/* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
+/*description: Phase for timer reload on sync event*/
+#define MCPWM_TIMER2_PHASE  0x0001FFFF
+#define MCPWM_TIMER2_PHASE_M  ((MCPWM_TIMER2_PHASE_V)<<(MCPWM_TIMER2_PHASE_S))
+#define MCPWM_TIMER2_PHASE_V  0x1FFFF
+#define MCPWM_TIMER2_PHASE_S  4
+/* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: PWM timer2 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+#define MCPWM_TIMER2_SYNCO_SEL  0x00000003
+#define MCPWM_TIMER2_SYNCO_SEL_M  ((MCPWM_TIMER2_SYNCO_SEL_V)<<(MCPWM_TIMER2_SYNCO_SEL_S))
+#define MCPWM_TIMER2_SYNCO_SEL_V  0x3
+#define MCPWM_TIMER2_SYNCO_SEL_S  2
+/* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Toggling this bit will trigger a software sync*/
+#define MCPWM_TIMER2_SYNC_SW  (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_M  (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_V  0x1
+#define MCPWM_TIMER2_SYNC_SW_S  1
+/* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: When set   timer reload with phase on sync input event is enabled*/
+#define MCPWM_TIMER2_SYNCI_EN  (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_M  (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_V  0x1
+#define MCPWM_TIMER2_SYNCI_EN_S  0
+
+#define MCPWM_TIMER2_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0030)
+/* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Current PWM timer2 counter direction  0: increment 1: decrement*/
+#define MCPWM_TIMER2_DIRECTION  (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_M  (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_V  0x1
+#define MCPWM_TIMER2_DIRECTION_S  16
+/* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Current PWM timer2 counter value*/
+#define MCPWM_TIMER2_VALUE  0x0000FFFF
+#define MCPWM_TIMER2_VALUE_M  ((MCPWM_TIMER2_VALUE_V)<<(MCPWM_TIMER2_VALUE_S))
+#define MCPWM_TIMER2_VALUE_V  0xFFFF
+#define MCPWM_TIMER2_VALUE_S  0
+
+#define MCPWM_TIMER_SYNCI_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0034)
+/* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: Onvert SYNC2 from GPIO matrix*/
+#define MCPWM_EXTERNAL_SYNCI2_INVERT  (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x1
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
+/* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Invert SYNC1 from GPIO matrix*/
+#define MCPWM_EXTERNAL_SYNCI1_INVERT  (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x1
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
+/* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Invert SYNC0 from GPIO matrix*/
+#define MCPWM_EXTERNAL_SYNCI0_INVERT  (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x1
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
+/* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */
+/*description: Select sync input for PWM timer2  1: PWM timer0 synco  2: PWM
+ timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
+#define MCPWM_TIMER2_SYNCISEL  0x00000007
+#define MCPWM_TIMER2_SYNCISEL_M  ((MCPWM_TIMER2_SYNCISEL_V)<<(MCPWM_TIMER2_SYNCISEL_S))
+#define MCPWM_TIMER2_SYNCISEL_V  0x7
+#define MCPWM_TIMER2_SYNCISEL_S  6
+/* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */
+/*description: Select sync input for PWM timer1  1: PWM timer0 synco  2: PWM
+ timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
+#define MCPWM_TIMER1_SYNCISEL  0x00000007
+#define MCPWM_TIMER1_SYNCISEL_M  ((MCPWM_TIMER1_SYNCISEL_V)<<(MCPWM_TIMER1_SYNCISEL_S))
+#define MCPWM_TIMER1_SYNCISEL_V  0x7
+#define MCPWM_TIMER1_SYNCISEL_S  3
+/* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */
+/*description: Select sync input for PWM timer0  1: PWM timer0 synco  2: PWM
+ timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
+#define MCPWM_TIMER0_SYNCISEL  0x00000007
+#define MCPWM_TIMER0_SYNCISEL_M  ((MCPWM_TIMER0_SYNCISEL_V)<<(MCPWM_TIMER0_SYNCISEL_S))
+#define MCPWM_TIMER0_SYNCISEL_V  0x7
+#define MCPWM_TIMER0_SYNCISEL_S  0
+
+#define MCPWM_OPERATOR_TIMERSEL_REG(i)          (REG_MCPWM_BASE(i) + 0x0038)
+/* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Select which PWM timer's is the timing reference for PWM operator2
+  0: timer0  1: timer1  2: timer2*/
+#define MCPWM_OPERATOR2_TIMERSEL  0x00000003
+#define MCPWM_OPERATOR2_TIMERSEL_M  ((MCPWM_OPERATOR2_TIMERSEL_V)<<(MCPWM_OPERATOR2_TIMERSEL_S))
+#define MCPWM_OPERATOR2_TIMERSEL_V  0x3
+#define MCPWM_OPERATOR2_TIMERSEL_S  4
+/* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Select which PWM timer's is the timing reference for PWM operator1
+  0: timer0  1: timer1  2: timer2*/
+#define MCPWM_OPERATOR1_TIMERSEL  0x00000003
+#define MCPWM_OPERATOR1_TIMERSEL_M  ((MCPWM_OPERATOR1_TIMERSEL_V)<<(MCPWM_OPERATOR1_TIMERSEL_S))
+#define MCPWM_OPERATOR1_TIMERSEL_V  0x3
+#define MCPWM_OPERATOR1_TIMERSEL_S  2
+/* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Select which PWM timer's is the timing reference for PWM operator0
+  0: timer0  1: timer1  2: timer2*/
+#define MCPWM_OPERATOR0_TIMERSEL  0x00000003
+#define MCPWM_OPERATOR0_TIMERSEL_M  ((MCPWM_OPERATOR0_TIMERSEL_V)<<(MCPWM_OPERATOR0_TIMERSEL_S))
+#define MCPWM_OPERATOR0_TIMERSEL_V  0x3
+#define MCPWM_OPERATOR0_TIMERSEL_S  0
+
+#define MCPWM_GEN0_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x003c)
+/* MCPWM_GEN0_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 0 time stamp
+ B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN0_B_SHDW_FULL  (BIT(9))
+#define MCPWM_GEN0_B_SHDW_FULL_M  (BIT(9))
+#define MCPWM_GEN0_B_SHDW_FULL_V  0x1
+#define MCPWM_GEN0_B_SHDW_FULL_S  9
+/* MCPWM_GEN0_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 0 time stamp
+ A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN0_A_SHDW_FULL  (BIT(8))
+#define MCPWM_GEN0_A_SHDW_FULL_M  (BIT(8))
+#define MCPWM_GEN0_A_SHDW_FULL_V  0x1
+#define MCPWM_GEN0_A_SHDW_FULL_S  8
+/* MCPWM_GEN0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 0 time stamp B's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN0_B_UPMETHOD  0x0000000F
+#define MCPWM_GEN0_B_UPMETHOD_M  ((MCPWM_GEN0_B_UPMETHOD_V)<<(MCPWM_GEN0_B_UPMETHOD_S))
+#define MCPWM_GEN0_B_UPMETHOD_V  0xF
+#define MCPWM_GEN0_B_UPMETHOD_S  4
+/* MCPWM_GEN0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 0 time stamp A's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN0_A_UPMETHOD  0x0000000F
+#define MCPWM_GEN0_A_UPMETHOD_M  ((MCPWM_GEN0_A_UPMETHOD_V)<<(MCPWM_GEN0_A_UPMETHOD_S))
+#define MCPWM_GEN0_A_UPMETHOD_V  0xF
+#define MCPWM_GEN0_A_UPMETHOD_S  0
+
+#define MCPWM_GEN0_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0040)
+/* MCPWM_GEN0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 0 time stamp A's shadow reg*/
+#define MCPWM_GEN0_A  0x0000FFFF
+#define MCPWM_GEN0_A_M  ((MCPWM_GEN0_A_V)<<(MCPWM_GEN0_A_S))
+#define MCPWM_GEN0_A_V  0xFFFF
+#define MCPWM_GEN0_A_S  0
+
+#define MCPWM_GEN0_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x0044)
+/* MCPWM_GEN0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 0 time stamp B's shadow reg*/
+#define MCPWM_GEN0_B  0x0000FFFF
+#define MCPWM_GEN0_B_M  ((MCPWM_GEN0_B_V)<<(MCPWM_GEN0_B_S))
+#define MCPWM_GEN0_B_V  0xFFFF
+#define MCPWM_GEN0_B_S  0
+
+#define MCPWM_GEN0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0048)
+/* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
+/*description: Source selection for PWM generator 0 event_t1  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN0_T1_SEL  0x00000007
+#define MCPWM_GEN0_T1_SEL_M  ((MCPWM_GEN0_T1_SEL_V)<<(MCPWM_GEN0_T1_SEL_S))
+#define MCPWM_GEN0_T1_SEL_V  0x7
+#define MCPWM_GEN0_T1_SEL_S  7
+/* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
+/*description: Source selection for PWM generator 0 event_t0  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN0_T0_SEL  0x00000007
+#define MCPWM_GEN0_T0_SEL_M  ((MCPWM_GEN0_T0_SEL_V)<<(MCPWM_GEN0_T0_SEL_S))
+#define MCPWM_GEN0_T0_SEL_V  0x7
+#define MCPWM_GEN0_T0_SEL_S  4
+/* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 0's active reg of configuration.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
+#define MCPWM_GEN0_CFG_UPMETHOD  0x0000000F
+#define MCPWM_GEN0_CFG_UPMETHOD_M  ((MCPWM_GEN0_CFG_UPMETHOD_V)<<(MCPWM_GEN0_CFG_UPMETHOD_S))
+#define MCPWM_GEN0_CFG_UPMETHOD_V  0xF
+#define MCPWM_GEN0_CFG_UPMETHOD_S  0
+
+#define MCPWM_GEN0_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x004c)
+/* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM0B  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN0_B_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN0_B_NCIFORCE_MODE_M  ((MCPWM_GEN0_B_NCIFORCE_MODE_V)<<(MCPWM_GEN0_B_NCIFORCE_MODE_S))
+#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
+/* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM0B  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN0_B_NCIFORCE  (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_M  (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_V  0x1
+#define MCPWM_GEN0_B_NCIFORCE_S  13
+/* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM0A  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN0_A_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN0_A_NCIFORCE_MODE_M  ((MCPWM_GEN0_A_NCIFORCE_MODE_V)<<(MCPWM_GEN0_A_NCIFORCE_MODE_S))
+#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
+/* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM0A  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN0_A_NCIFORCE  (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_M  (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_V  0x1
+#define MCPWM_GEN0_A_NCIFORCE_S  10
+/* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM0B. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN0_B_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  ((MCPWM_GEN0_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_B_CNTUFORCE_MODE_S))
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
+/* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM0A. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN0_A_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  ((MCPWM_GEN0_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_A_CNTUFORCE_MODE_S))
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
+/* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: Update method for continuous software force of PWM generator0.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD  0x0000003F
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN0_CNTUFORCE_UPMETHOD_S))
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x3F
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
+
+#define MCPWM_GEN0_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0050)
+/* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN0_A_DT1  0x00000003
+#define MCPWM_GEN0_A_DT1_M  ((MCPWM_GEN0_A_DT1_V)<<(MCPWM_GEN0_A_DT1_S))
+#define MCPWM_GEN0_A_DT1_V  0x3
+#define MCPWM_GEN0_A_DT1_S  22
+/* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN0_A_DT0  0x00000003
+#define MCPWM_GEN0_A_DT0_M  ((MCPWM_GEN0_A_DT0_V)<<(MCPWM_GEN0_A_DT0_S))
+#define MCPWM_GEN0_A_DT0_V  0x3
+#define MCPWM_GEN0_A_DT0_S  20
+/* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN0_A_DTEB  0x00000003
+#define MCPWM_GEN0_A_DTEB_M  ((MCPWM_GEN0_A_DTEB_V)<<(MCPWM_GEN0_A_DTEB_S))
+#define MCPWM_GEN0_A_DTEB_V  0x3
+#define MCPWM_GEN0_A_DTEB_S  18
+/* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN0_A_DTEA  0x00000003
+#define MCPWM_GEN0_A_DTEA_M  ((MCPWM_GEN0_A_DTEA_V)<<(MCPWM_GEN0_A_DTEA_S))
+#define MCPWM_GEN0_A_DTEA_V  0x3
+#define MCPWM_GEN0_A_DTEA_S  16
+/* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN0_A_DTEP  0x00000003
+#define MCPWM_GEN0_A_DTEP_M  ((MCPWM_GEN0_A_DTEP_V)<<(MCPWM_GEN0_A_DTEP_S))
+#define MCPWM_GEN0_A_DTEP_V  0x3
+#define MCPWM_GEN0_A_DTEP_S  14
+/* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN0_A_DTEZ  0x00000003
+#define MCPWM_GEN0_A_DTEZ_M  ((MCPWM_GEN0_A_DTEZ_V)<<(MCPWM_GEN0_A_DTEZ_S))
+#define MCPWM_GEN0_A_DTEZ_V  0x3
+#define MCPWM_GEN0_A_DTEZ_S  12
+/* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN0_A_UT1  0x00000003
+#define MCPWM_GEN0_A_UT1_M  ((MCPWM_GEN0_A_UT1_V)<<(MCPWM_GEN0_A_UT1_S))
+#define MCPWM_GEN0_A_UT1_V  0x3
+#define MCPWM_GEN0_A_UT1_S  10
+/* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN0_A_UT0  0x00000003
+#define MCPWM_GEN0_A_UT0_M  ((MCPWM_GEN0_A_UT0_V)<<(MCPWM_GEN0_A_UT0_S))
+#define MCPWM_GEN0_A_UT0_V  0x3
+#define MCPWM_GEN0_A_UT0_S  8
+/* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEB when timer increasing*/
+#define MCPWM_GEN0_A_UTEB  0x00000003
+#define MCPWM_GEN0_A_UTEB_M  ((MCPWM_GEN0_A_UTEB_V)<<(MCPWM_GEN0_A_UTEB_S))
+#define MCPWM_GEN0_A_UTEB_V  0x3
+#define MCPWM_GEN0_A_UTEB_S  6
+/* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEA when timer increasing*/
+#define MCPWM_GEN0_A_UTEA  0x00000003
+#define MCPWM_GEN0_A_UTEA_M  ((MCPWM_GEN0_A_UTEA_V)<<(MCPWM_GEN0_A_UTEA_S))
+#define MCPWM_GEN0_A_UTEA_V  0x3
+#define MCPWM_GEN0_A_UTEA_S  4
+/* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEP when timer increasing*/
+#define MCPWM_GEN0_A_UTEP  0x00000003
+#define MCPWM_GEN0_A_UTEP_M  ((MCPWM_GEN0_A_UTEP_V)<<(MCPWM_GEN0_A_UTEP_S))
+#define MCPWM_GEN0_A_UTEP_V  0x3
+#define MCPWM_GEN0_A_UTEP_S  2
+/* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN0_A_UTEZ  0x00000003
+#define MCPWM_GEN0_A_UTEZ_M  ((MCPWM_GEN0_A_UTEZ_V)<<(MCPWM_GEN0_A_UTEZ_S))
+#define MCPWM_GEN0_A_UTEZ_V  0x3
+#define MCPWM_GEN0_A_UTEZ_S  0
+
+#define MCPWM_GEN0_B_REG(i)          (REG_MCPWM_BASE(i) + 0x0054)
+/* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN0_B_DT1  0x00000003
+#define MCPWM_GEN0_B_DT1_M  ((MCPWM_GEN0_B_DT1_V)<<(MCPWM_GEN0_B_DT1_S))
+#define MCPWM_GEN0_B_DT1_V  0x3
+#define MCPWM_GEN0_B_DT1_S  22
+/* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN0_B_DT0  0x00000003
+#define MCPWM_GEN0_B_DT0_M  ((MCPWM_GEN0_B_DT0_V)<<(MCPWM_GEN0_B_DT0_S))
+#define MCPWM_GEN0_B_DT0_V  0x3
+#define MCPWM_GEN0_B_DT0_S  20
+/* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN0_B_DTEB  0x00000003
+#define MCPWM_GEN0_B_DTEB_M  ((MCPWM_GEN0_B_DTEB_V)<<(MCPWM_GEN0_B_DTEB_S))
+#define MCPWM_GEN0_B_DTEB_V  0x3
+#define MCPWM_GEN0_B_DTEB_S  18
+/* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN0_B_DTEA  0x00000003
+#define MCPWM_GEN0_B_DTEA_M  ((MCPWM_GEN0_B_DTEA_V)<<(MCPWM_GEN0_B_DTEA_S))
+#define MCPWM_GEN0_B_DTEA_V  0x3
+#define MCPWM_GEN0_B_DTEA_S  16
+/* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN0_B_DTEP  0x00000003
+#define MCPWM_GEN0_B_DTEP_M  ((MCPWM_GEN0_B_DTEP_V)<<(MCPWM_GEN0_B_DTEP_S))
+#define MCPWM_GEN0_B_DTEP_V  0x3
+#define MCPWM_GEN0_B_DTEP_S  14
+/* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN0_B_DTEZ  0x00000003
+#define MCPWM_GEN0_B_DTEZ_M  ((MCPWM_GEN0_B_DTEZ_V)<<(MCPWM_GEN0_B_DTEZ_S))
+#define MCPWM_GEN0_B_DTEZ_V  0x3
+#define MCPWM_GEN0_B_DTEZ_S  12
+/* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN0_B_UT1  0x00000003
+#define MCPWM_GEN0_B_UT1_M  ((MCPWM_GEN0_B_UT1_V)<<(MCPWM_GEN0_B_UT1_S))
+#define MCPWM_GEN0_B_UT1_V  0x3
+#define MCPWM_GEN0_B_UT1_S  10
+/* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN0_B_UT0  0x00000003
+#define MCPWM_GEN0_B_UT0_M  ((MCPWM_GEN0_B_UT0_V)<<(MCPWM_GEN0_B_UT0_S))
+#define MCPWM_GEN0_B_UT0_V  0x3
+#define MCPWM_GEN0_B_UT0_S  8
+/* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEB when timer increasing*/
+#define MCPWM_GEN0_B_UTEB  0x00000003
+#define MCPWM_GEN0_B_UTEB_M  ((MCPWM_GEN0_B_UTEB_V)<<(MCPWM_GEN0_B_UTEB_S))
+#define MCPWM_GEN0_B_UTEB_V  0x3
+#define MCPWM_GEN0_B_UTEB_S  6
+/* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEA when timer increasing*/
+#define MCPWM_GEN0_B_UTEA  0x00000003
+#define MCPWM_GEN0_B_UTEA_M  ((MCPWM_GEN0_B_UTEA_V)<<(MCPWM_GEN0_B_UTEA_S))
+#define MCPWM_GEN0_B_UTEA_V  0x3
+#define MCPWM_GEN0_B_UTEA_S  4
+/* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEP when timer increasing*/
+#define MCPWM_GEN0_B_UTEP  0x00000003
+#define MCPWM_GEN0_B_UTEP_M  ((MCPWM_GEN0_B_UTEP_V)<<(MCPWM_GEN0_B_UTEP_S))
+#define MCPWM_GEN0_B_UTEP_V  0x3
+#define MCPWM_GEN0_B_UTEP_S  2
+/* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN0_B_UTEZ  0x00000003
+#define MCPWM_GEN0_B_UTEZ_M  ((MCPWM_GEN0_B_UTEZ_V)<<(MCPWM_GEN0_B_UTEZ_S))
+#define MCPWM_GEN0_B_UTEZ_V  0x3
+#define MCPWM_GEN0_B_UTEZ_S  0
+
+#define MCPWM_DT0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0058)
+/* MCPWM_DT0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Dead time generator 0 clock selection. 0: PWM_clk  1: PT_clk*/
+#define MCPWM_DT0_CLK_SEL  (BIT(17))
+#define MCPWM_DT0_CLK_SEL_M  (BIT(17))
+#define MCPWM_DT0_CLK_SEL_V  0x1
+#define MCPWM_DT0_CLK_SEL_S  17
+/* MCPWM_DT0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: S0 in documentation*/
+#define MCPWM_DT0_B_OUTBYPASS  (BIT(16))
+#define MCPWM_DT0_B_OUTBYPASS_M  (BIT(16))
+#define MCPWM_DT0_B_OUTBYPASS_V  0x1
+#define MCPWM_DT0_B_OUTBYPASS_S  16
+/* MCPWM_DT0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: S1 in documentation*/
+#define MCPWM_DT0_A_OUTBYPASS  (BIT(15))
+#define MCPWM_DT0_A_OUTBYPASS_M  (BIT(15))
+#define MCPWM_DT0_A_OUTBYPASS_V  0x1
+#define MCPWM_DT0_A_OUTBYPASS_S  15
+/* MCPWM_DT0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: S3 in documentation*/
+#define MCPWM_DT0_FED_OUTINVERT  (BIT(14))
+#define MCPWM_DT0_FED_OUTINVERT_M  (BIT(14))
+#define MCPWM_DT0_FED_OUTINVERT_V  0x1
+#define MCPWM_DT0_FED_OUTINVERT_S  14
+/* MCPWM_DT0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: S2 in documentation*/
+#define MCPWM_DT0_RED_OUTINVERT  (BIT(13))
+#define MCPWM_DT0_RED_OUTINVERT_M  (BIT(13))
+#define MCPWM_DT0_RED_OUTINVERT_V  0x1
+#define MCPWM_DT0_RED_OUTINVERT_S  13
+/* MCPWM_DT0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: S5 in documentation*/
+#define MCPWM_DT0_FED_INSEL  (BIT(12))
+#define MCPWM_DT0_FED_INSEL_M  (BIT(12))
+#define MCPWM_DT0_FED_INSEL_V  0x1
+#define MCPWM_DT0_FED_INSEL_S  12
+/* MCPWM_DT0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: S4 in documentation*/
+#define MCPWM_DT0_RED_INSEL  (BIT(11))
+#define MCPWM_DT0_RED_INSEL_M  (BIT(11))
+#define MCPWM_DT0_RED_INSEL_V  0x1
+#define MCPWM_DT0_RED_INSEL_S  11
+/* MCPWM_DT0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: S7 in documentation*/
+#define MCPWM_DT0_B_OUTSWAP  (BIT(10))
+#define MCPWM_DT0_B_OUTSWAP_M  (BIT(10))
+#define MCPWM_DT0_B_OUTSWAP_V  0x1
+#define MCPWM_DT0_B_OUTSWAP_S  10
+/* MCPWM_DT0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: S6 in documentation*/
+#define MCPWM_DT0_A_OUTSWAP  (BIT(9))
+#define MCPWM_DT0_A_OUTSWAP_M  (BIT(9))
+#define MCPWM_DT0_A_OUTSWAP_V  0x1
+#define MCPWM_DT0_A_OUTSWAP_S  9
+/* MCPWM_DT0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
+ on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
+#define MCPWM_DT0_DEB_MODE  (BIT(8))
+#define MCPWM_DT0_DEB_MODE_M  (BIT(8))
+#define MCPWM_DT0_DEB_MODE_V  0x1
+#define MCPWM_DT0_DEB_MODE_S  8
+/* MCPWM_DT0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for RED (rising edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT0_RED_UPMETHOD  0x0000000F
+#define MCPWM_DT0_RED_UPMETHOD_M  ((MCPWM_DT0_RED_UPMETHOD_V)<<(MCPWM_DT0_RED_UPMETHOD_S))
+#define MCPWM_DT0_RED_UPMETHOD_V  0xF
+#define MCPWM_DT0_RED_UPMETHOD_S  4
+/* MCPWM_DT0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for FED (falling edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT0_FED_UPMETHOD  0x0000000F
+#define MCPWM_DT0_FED_UPMETHOD_M  ((MCPWM_DT0_FED_UPMETHOD_V)<<(MCPWM_DT0_FED_UPMETHOD_S))
+#define MCPWM_DT0_FED_UPMETHOD_V  0xF
+#define MCPWM_DT0_FED_UPMETHOD_S  0
+
+#define MCPWM_DT0_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x005c)
+/* MCPWM_DT0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for FED*/
+#define MCPWM_DT0_FED  0x0000FFFF
+#define MCPWM_DT0_FED_M  ((MCPWM_DT0_FED_V)<<(MCPWM_DT0_FED_S))
+#define MCPWM_DT0_FED_V  0xFFFF
+#define MCPWM_DT0_FED_S  0
+
+#define MCPWM_DT0_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0060)
+/* MCPWM_DT0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for RED*/
+#define MCPWM_DT0_RED  0x0000FFFF
+#define MCPWM_DT0_RED_M  ((MCPWM_DT0_RED_V)<<(MCPWM_DT0_RED_S))
+#define MCPWM_DT0_RED_V  0xFFFF
+#define MCPWM_DT0_RED_S  0
+
+#define MCPWM_CARRIER0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0064)
+/* MCPWM_CARRIER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: When set  invert the input of PWM0A and PWM0B for this submodule*/
+#define MCPWM_CARRIER0_IN_INVERT  (BIT(13))
+#define MCPWM_CARRIER0_IN_INVERT_M  (BIT(13))
+#define MCPWM_CARRIER0_IN_INVERT_V  0x1
+#define MCPWM_CARRIER0_IN_INVERT_S  13
+/* MCPWM_CARRIER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: When set  invert the output of PWM0A and PWM0B for this submodule*/
+#define MCPWM_CARRIER0_OUT_INVERT  (BIT(12))
+#define MCPWM_CARRIER0_OUT_INVERT_M  (BIT(12))
+#define MCPWM_CARRIER0_OUT_INVERT_V  0x1
+#define MCPWM_CARRIER0_OUT_INVERT_S  12
+/* MCPWM_CARRIER0_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Width of the fist pulse in number of periods of the carrier*/
+#define MCPWM_CARRIER0_OSHWTH  0x0000000F
+#define MCPWM_CARRIER0_OSHWTH_M  ((MCPWM_CARRIER0_OSHWTH_V)<<(MCPWM_CARRIER0_OSHWTH_S))
+#define MCPWM_CARRIER0_OSHWTH_V  0xF
+#define MCPWM_CARRIER0_OSHWTH_S  8
+/* MCPWM_CARRIER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
+/*description: Carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
+#define MCPWM_CARRIER0_DUTY  0x00000007
+#define MCPWM_CARRIER0_DUTY_M  ((MCPWM_CARRIER0_DUTY_V)<<(MCPWM_CARRIER0_DUTY_S))
+#define MCPWM_CARRIER0_DUTY_V  0x7
+#define MCPWM_CARRIER0_DUTY_S  5
+/* MCPWM_CARRIER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk
+ = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
+#define MCPWM_CARRIER0_PRESCALE  0x0000000F
+#define MCPWM_CARRIER0_PRESCALE_M  ((MCPWM_CARRIER0_PRESCALE_V)<<(MCPWM_CARRIER0_PRESCALE_S))
+#define MCPWM_CARRIER0_PRESCALE_V  0xF
+#define MCPWM_CARRIER0_PRESCALE_S  1
+/* MCPWM_CARRIER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  carrier0 function is enabled. When cleared  carrier0 is bypassed*/
+#define MCPWM_CARRIER0_EN  (BIT(0))
+#define MCPWM_CARRIER0_EN_M  (BIT(0))
+#define MCPWM_CARRIER0_EN_V  0x1
+#define MCPWM_CARRIER0_EN_S  0
+
+#define MCPWM_FH0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0068)
+/* MCPWM_FH0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0B when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_OST_U  0x00000003
+#define MCPWM_FH0_B_OST_U_M  ((MCPWM_FH0_B_OST_U_V)<<(MCPWM_FH0_B_OST_U_S))
+#define MCPWM_FH0_B_OST_U_V  0x3
+#define MCPWM_FH0_B_OST_U_S  22
+/* MCPWM_FH0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0B when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_OST_D  0x00000003
+#define MCPWM_FH0_B_OST_D_M  ((MCPWM_FH0_B_OST_D_V)<<(MCPWM_FH0_B_OST_D_S))
+#define MCPWM_FH0_B_OST_D_V  0x3
+#define MCPWM_FH0_B_OST_D_S  20
+/* MCPWM_FH0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_CBC_U  0x00000003
+#define MCPWM_FH0_B_CBC_U_M  ((MCPWM_FH0_B_CBC_U_V)<<(MCPWM_FH0_B_CBC_U_S))
+#define MCPWM_FH0_B_CBC_U_V  0x3
+#define MCPWM_FH0_B_CBC_U_S  18
+/* MCPWM_FH0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_CBC_D  0x00000003
+#define MCPWM_FH0_B_CBC_D_M  ((MCPWM_FH0_B_CBC_D_V)<<(MCPWM_FH0_B_CBC_D_S))
+#define MCPWM_FH0_B_CBC_D_V  0x3
+#define MCPWM_FH0_B_CBC_D_S  16
+/* MCPWM_FH0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0A when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_OST_U  0x00000003
+#define MCPWM_FH0_A_OST_U_M  ((MCPWM_FH0_A_OST_U_V)<<(MCPWM_FH0_A_OST_U_S))
+#define MCPWM_FH0_A_OST_U_V  0x3
+#define MCPWM_FH0_A_OST_U_S  14
+/* MCPWM_FH0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0A when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_OST_D  0x00000003
+#define MCPWM_FH0_A_OST_D_M  ((MCPWM_FH0_A_OST_D_V)<<(MCPWM_FH0_A_OST_D_S))
+#define MCPWM_FH0_A_OST_D_V  0x3
+#define MCPWM_FH0_A_OST_D_S  12
+/* MCPWM_FH0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_CBC_U  0x00000003
+#define MCPWM_FH0_A_CBC_U_M  ((MCPWM_FH0_A_CBC_U_V)<<(MCPWM_FH0_A_CBC_U_S))
+#define MCPWM_FH0_A_CBC_U_V  0x3
+#define MCPWM_FH0_A_CBC_U_S  10
+/* MCPWM_FH0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_CBC_D  0x00000003
+#define MCPWM_FH0_A_CBC_D_M  ((MCPWM_FH0_A_CBC_D_V)<<(MCPWM_FH0_A_CBC_D_S))
+#define MCPWM_FH0_A_CBC_D_V  0x3
+#define MCPWM_FH0_A_CBC_D_S  8
+/* MCPWM_FH0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F0_OST  (BIT(7))
+#define MCPWM_FH0_F0_OST_M  (BIT(7))
+#define MCPWM_FH0_F0_OST_V  0x1
+#define MCPWM_FH0_F0_OST_S  7
+/* MCPWM_FH0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F1_OST  (BIT(6))
+#define MCPWM_FH0_F1_OST_M  (BIT(6))
+#define MCPWM_FH0_F1_OST_V  0x1
+#define MCPWM_FH0_F1_OST_S  6
+/* MCPWM_FH0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F2_OST  (BIT(5))
+#define MCPWM_FH0_F2_OST_M  (BIT(5))
+#define MCPWM_FH0_F2_OST_V  0x1
+#define MCPWM_FH0_F2_OST_S  5
+/* MCPWM_FH0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_SW_OST  (BIT(4))
+#define MCPWM_FH0_SW_OST_M  (BIT(4))
+#define MCPWM_FH0_SW_OST_V  0x1
+#define MCPWM_FH0_SW_OST_S  4
+/* MCPWM_FH0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F0_CBC  (BIT(3))
+#define MCPWM_FH0_F0_CBC_M  (BIT(3))
+#define MCPWM_FH0_F0_CBC_V  0x1
+#define MCPWM_FH0_F0_CBC_S  3
+/* MCPWM_FH0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F1_CBC  (BIT(2))
+#define MCPWM_FH0_F1_CBC_M  (BIT(2))
+#define MCPWM_FH0_F1_CBC_V  0x1
+#define MCPWM_FH0_F1_CBC_S  2
+/* MCPWM_FH0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F2_CBC  (BIT(1))
+#define MCPWM_FH0_F2_CBC_M  (BIT(1))
+#define MCPWM_FH0_F2_CBC_V  0x1
+#define MCPWM_FH0_F2_CBC_S  1
+/* MCPWM_FH0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Enable register for software force cycle-by-cycle mode action.
+ 0: disable  1: enable*/
+#define MCPWM_FH0_SW_CBC  (BIT(0))
+#define MCPWM_FH0_SW_CBC_M  (BIT(0))
+#define MCPWM_FH0_SW_CBC_V  0x1
+#define MCPWM_FH0_SW_CBC_S  0
+
+#define MCPWM_FH0_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x006c)
+/* MCPWM_FH0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) triggers a
+ one-shot mode action*/
+#define MCPWM_FH0_FORCE_OST  (BIT(4))
+#define MCPWM_FH0_FORCE_OST_M  (BIT(4))
+#define MCPWM_FH0_FORCE_OST_V  0x1
+#define MCPWM_FH0_FORCE_OST_S  4
+/* MCPWM_FH0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle triggers a cycle-by-cycle mode action*/
+#define MCPWM_FH0_FORCE_CBC  (BIT(3))
+#define MCPWM_FH0_FORCE_CBC_M  (BIT(3))
+#define MCPWM_FH0_FORCE_CBC_V  0x1
+#define MCPWM_FH0_FORCE_CBC_S  3
+/* MCPWM_FH0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
+#define MCPWM_FH0_CBCPULSE  0x00000003
+#define MCPWM_FH0_CBCPULSE_M  ((MCPWM_FH0_CBCPULSE_V)<<(MCPWM_FH0_CBCPULSE_S))
+#define MCPWM_FH0_CBCPULSE_V  0x3
+#define MCPWM_FH0_CBCPULSE_S  1
+/* MCPWM_FH0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: A toggle will clear on going one-shot mode action*/
+#define MCPWM_FH0_CLR_OST  (BIT(0))
+#define MCPWM_FH0_CLR_OST_M  (BIT(0))
+#define MCPWM_FH0_CLR_OST_V  0x1
+#define MCPWM_FH0_CLR_OST_S  0
+
+#define MCPWM_FH0_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0070)
+/* MCPWM_FH0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
+#define MCPWM_FH0_OST_ON  (BIT(1))
+#define MCPWM_FH0_OST_ON_M  (BIT(1))
+#define MCPWM_FH0_OST_ON_V  0x1
+#define MCPWM_FH0_OST_ON_S  1
+/* MCPWM_FH0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
+#define MCPWM_FH0_CBC_ON  (BIT(0))
+#define MCPWM_FH0_CBC_ON_M  (BIT(0))
+#define MCPWM_FH0_CBC_ON_V  0x1
+#define MCPWM_FH0_CBC_ON_S  0
+
+#define MCPWM_GEN1_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0074)
+/* MCPWM_GEN1_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 1 time stamp
+ B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN1_B_SHDW_FULL  (BIT(9))
+#define MCPWM_GEN1_B_SHDW_FULL_M  (BIT(9))
+#define MCPWM_GEN1_B_SHDW_FULL_V  0x1
+#define MCPWM_GEN1_B_SHDW_FULL_S  9
+/* MCPWM_GEN1_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 1 time stamp
+ A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN1_A_SHDW_FULL  (BIT(8))
+#define MCPWM_GEN1_A_SHDW_FULL_M  (BIT(8))
+#define MCPWM_GEN1_A_SHDW_FULL_V  0x1
+#define MCPWM_GEN1_A_SHDW_FULL_S  8
+/* MCPWM_GEN1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 1 time stamp B's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN1_B_UPMETHOD  0x0000000F
+#define MCPWM_GEN1_B_UPMETHOD_M  ((MCPWM_GEN1_B_UPMETHOD_V)<<(MCPWM_GEN1_B_UPMETHOD_S))
+#define MCPWM_GEN1_B_UPMETHOD_V  0xF
+#define MCPWM_GEN1_B_UPMETHOD_S  4
+/* MCPWM_GEN1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 1 time stamp A's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN1_A_UPMETHOD  0x0000000F
+#define MCPWM_GEN1_A_UPMETHOD_M  ((MCPWM_GEN1_A_UPMETHOD_V)<<(MCPWM_GEN1_A_UPMETHOD_S))
+#define MCPWM_GEN1_A_UPMETHOD_V  0xF
+#define MCPWM_GEN1_A_UPMETHOD_S  0
+
+#define MCPWM_GEN1_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0078)
+/* MCPWM_GEN1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 1 time stamp A's shadow reg*/
+#define MCPWM_GEN1_A  0x0000FFFF
+#define MCPWM_GEN1_A_M  ((MCPWM_GEN1_A_V)<<(MCPWM_GEN1_A_S))
+#define MCPWM_GEN1_A_V  0xFFFF
+#define MCPWM_GEN1_A_S  0
+
+#define MCPWM_GEN1_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x007c)
+/* MCPWM_GEN1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 1 time stamp B's shadow reg*/
+#define MCPWM_GEN1_B  0x0000FFFF
+#define MCPWM_GEN1_B_M  ((MCPWM_GEN1_B_V)<<(MCPWM_GEN1_B_S))
+#define MCPWM_GEN1_B_V  0xFFFF
+#define MCPWM_GEN1_B_S  0
+
+#define MCPWM_GEN1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0080)
+/* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate1 event_t1  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN1_T1_SEL  0x00000007
+#define MCPWM_GEN1_T1_SEL_M  ((MCPWM_GEN1_T1_SEL_V)<<(MCPWM_GEN1_T1_SEL_S))
+#define MCPWM_GEN1_T1_SEL_V  0x7
+#define MCPWM_GEN1_T1_SEL_S  7
+/* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate1 event_t0  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN1_T0_SEL  0x00000007
+#define MCPWM_GEN1_T0_SEL_M  ((MCPWM_GEN1_T0_SEL_V)<<(MCPWM_GEN1_T0_SEL_S))
+#define MCPWM_GEN1_T0_SEL_V  0x7
+#define MCPWM_GEN1_T0_SEL_S  4
+/* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generate1's active reg of configuration.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
+#define MCPWM_GEN1_CFG_UPMETHOD  0x0000000F
+#define MCPWM_GEN1_CFG_UPMETHOD_M  ((MCPWM_GEN1_CFG_UPMETHOD_V)<<(MCPWM_GEN1_CFG_UPMETHOD_S))
+#define MCPWM_GEN1_CFG_UPMETHOD_V  0xF
+#define MCPWM_GEN1_CFG_UPMETHOD_S  0
+
+#define MCPWM_GEN1_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x0084)
+/* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM1B  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN1_B_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN1_B_NCIFORCE_MODE_M  ((MCPWM_GEN1_B_NCIFORCE_MODE_V)<<(MCPWM_GEN1_B_NCIFORCE_MODE_S))
+#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
+/* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM1B  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN1_B_NCIFORCE  (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_M  (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_V  0x1
+#define MCPWM_GEN1_B_NCIFORCE_S  13
+/* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM1A  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN1_A_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN1_A_NCIFORCE_MODE_M  ((MCPWM_GEN1_A_NCIFORCE_MODE_V)<<(MCPWM_GEN1_A_NCIFORCE_MODE_S))
+#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
+/* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM1A  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN1_A_NCIFORCE  (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_M  (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_V  0x1
+#define MCPWM_GEN1_A_NCIFORCE_S  10
+/* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM1B. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN1_B_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  ((MCPWM_GEN1_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_B_CNTUFORCE_MODE_S))
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
+/* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM1A. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN1_A_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  ((MCPWM_GEN1_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_A_CNTUFORCE_MODE_S))
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
+/* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: Update method for continuous software force of PWM generator1.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD  0x0000003F
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN1_CNTUFORCE_UPMETHOD_S))
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x3F
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
+
+#define MCPWM_GEN1_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0088)
+/* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN1_A_DT1  0x00000003
+#define MCPWM_GEN1_A_DT1_M  ((MCPWM_GEN1_A_DT1_V)<<(MCPWM_GEN1_A_DT1_S))
+#define MCPWM_GEN1_A_DT1_V  0x3
+#define MCPWM_GEN1_A_DT1_S  22
+/* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN1_A_DT0  0x00000003
+#define MCPWM_GEN1_A_DT0_M  ((MCPWM_GEN1_A_DT0_V)<<(MCPWM_GEN1_A_DT0_S))
+#define MCPWM_GEN1_A_DT0_V  0x3
+#define MCPWM_GEN1_A_DT0_S  20
+/* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN1_A_DTEB  0x00000003
+#define MCPWM_GEN1_A_DTEB_M  ((MCPWM_GEN1_A_DTEB_V)<<(MCPWM_GEN1_A_DTEB_S))
+#define MCPWM_GEN1_A_DTEB_V  0x3
+#define MCPWM_GEN1_A_DTEB_S  18
+/* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN1_A_DTEA  0x00000003
+#define MCPWM_GEN1_A_DTEA_M  ((MCPWM_GEN1_A_DTEA_V)<<(MCPWM_GEN1_A_DTEA_S))
+#define MCPWM_GEN1_A_DTEA_V  0x3
+#define MCPWM_GEN1_A_DTEA_S  16
+/* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN1_A_DTEP  0x00000003
+#define MCPWM_GEN1_A_DTEP_M  ((MCPWM_GEN1_A_DTEP_V)<<(MCPWM_GEN1_A_DTEP_S))
+#define MCPWM_GEN1_A_DTEP_V  0x3
+#define MCPWM_GEN1_A_DTEP_S  14
+/* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN1_A_DTEZ  0x00000003
+#define MCPWM_GEN1_A_DTEZ_M  ((MCPWM_GEN1_A_DTEZ_V)<<(MCPWM_GEN1_A_DTEZ_S))
+#define MCPWM_GEN1_A_DTEZ_V  0x3
+#define MCPWM_GEN1_A_DTEZ_S  12
+/* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN1_A_UT1  0x00000003
+#define MCPWM_GEN1_A_UT1_M  ((MCPWM_GEN1_A_UT1_V)<<(MCPWM_GEN1_A_UT1_S))
+#define MCPWM_GEN1_A_UT1_V  0x3
+#define MCPWM_GEN1_A_UT1_S  10
+/* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN1_A_UT0  0x00000003
+#define MCPWM_GEN1_A_UT0_M  ((MCPWM_GEN1_A_UT0_V)<<(MCPWM_GEN1_A_UT0_S))
+#define MCPWM_GEN1_A_UT0_V  0x3
+#define MCPWM_GEN1_A_UT0_S  8
+/* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEB when timer increasing*/
+#define MCPWM_GEN1_A_UTEB  0x00000003
+#define MCPWM_GEN1_A_UTEB_M  ((MCPWM_GEN1_A_UTEB_V)<<(MCPWM_GEN1_A_UTEB_S))
+#define MCPWM_GEN1_A_UTEB_V  0x3
+#define MCPWM_GEN1_A_UTEB_S  6
+/* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEA when timer increasing*/
+#define MCPWM_GEN1_A_UTEA  0x00000003
+#define MCPWM_GEN1_A_UTEA_M  ((MCPWM_GEN1_A_UTEA_V)<<(MCPWM_GEN1_A_UTEA_S))
+#define MCPWM_GEN1_A_UTEA_V  0x3
+#define MCPWM_GEN1_A_UTEA_S  4
+/* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEP when timer increasing*/
+#define MCPWM_GEN1_A_UTEP  0x00000003
+#define MCPWM_GEN1_A_UTEP_M  ((MCPWM_GEN1_A_UTEP_V)<<(MCPWM_GEN1_A_UTEP_S))
+#define MCPWM_GEN1_A_UTEP_V  0x3
+#define MCPWM_GEN1_A_UTEP_S  2
+/* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN1_A_UTEZ  0x00000003
+#define MCPWM_GEN1_A_UTEZ_M  ((MCPWM_GEN1_A_UTEZ_V)<<(MCPWM_GEN1_A_UTEZ_S))
+#define MCPWM_GEN1_A_UTEZ_V  0x3
+#define MCPWM_GEN1_A_UTEZ_S  0
+
+#define MCPWM_GEN1_B_REG(i)          (REG_MCPWM_BASE(i) + 0x008c)
+/* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN1_B_DT1  0x00000003
+#define MCPWM_GEN1_B_DT1_M  ((MCPWM_GEN1_B_DT1_V)<<(MCPWM_GEN1_B_DT1_S))
+#define MCPWM_GEN1_B_DT1_V  0x3
+#define MCPWM_GEN1_B_DT1_S  22
+/* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN1_B_DT0  0x00000003
+#define MCPWM_GEN1_B_DT0_M  ((MCPWM_GEN1_B_DT0_V)<<(MCPWM_GEN1_B_DT0_S))
+#define MCPWM_GEN1_B_DT0_V  0x3
+#define MCPWM_GEN1_B_DT0_S  20
+/* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN1_B_DTEB  0x00000003
+#define MCPWM_GEN1_B_DTEB_M  ((MCPWM_GEN1_B_DTEB_V)<<(MCPWM_GEN1_B_DTEB_S))
+#define MCPWM_GEN1_B_DTEB_V  0x3
+#define MCPWM_GEN1_B_DTEB_S  18
+/* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN1_B_DTEA  0x00000003
+#define MCPWM_GEN1_B_DTEA_M  ((MCPWM_GEN1_B_DTEA_V)<<(MCPWM_GEN1_B_DTEA_S))
+#define MCPWM_GEN1_B_DTEA_V  0x3
+#define MCPWM_GEN1_B_DTEA_S  16
+/* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN1_B_DTEP  0x00000003
+#define MCPWM_GEN1_B_DTEP_M  ((MCPWM_GEN1_B_DTEP_V)<<(MCPWM_GEN1_B_DTEP_S))
+#define MCPWM_GEN1_B_DTEP_V  0x3
+#define MCPWM_GEN1_B_DTEP_S  14
+/* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN1_B_DTEZ  0x00000003
+#define MCPWM_GEN1_B_DTEZ_M  ((MCPWM_GEN1_B_DTEZ_V)<<(MCPWM_GEN1_B_DTEZ_S))
+#define MCPWM_GEN1_B_DTEZ_V  0x3
+#define MCPWM_GEN1_B_DTEZ_S  12
+/* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN1_B_UT1  0x00000003
+#define MCPWM_GEN1_B_UT1_M  ((MCPWM_GEN1_B_UT1_V)<<(MCPWM_GEN1_B_UT1_S))
+#define MCPWM_GEN1_B_UT1_V  0x3
+#define MCPWM_GEN1_B_UT1_S  10
+/* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN1_B_UT0  0x00000003
+#define MCPWM_GEN1_B_UT0_M  ((MCPWM_GEN1_B_UT0_V)<<(MCPWM_GEN1_B_UT0_S))
+#define MCPWM_GEN1_B_UT0_V  0x3
+#define MCPWM_GEN1_B_UT0_S  8
+/* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEB when timer increasing*/
+#define MCPWM_GEN1_B_UTEB  0x00000003
+#define MCPWM_GEN1_B_UTEB_M  ((MCPWM_GEN1_B_UTEB_V)<<(MCPWM_GEN1_B_UTEB_S))
+#define MCPWM_GEN1_B_UTEB_V  0x3
+#define MCPWM_GEN1_B_UTEB_S  6
+/* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEA when timer increasing*/
+#define MCPWM_GEN1_B_UTEA  0x00000003
+#define MCPWM_GEN1_B_UTEA_M  ((MCPWM_GEN1_B_UTEA_V)<<(MCPWM_GEN1_B_UTEA_S))
+#define MCPWM_GEN1_B_UTEA_V  0x3
+#define MCPWM_GEN1_B_UTEA_S  4
+/* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEP when timer increasing*/
+#define MCPWM_GEN1_B_UTEP  0x00000003
+#define MCPWM_GEN1_B_UTEP_M  ((MCPWM_GEN1_B_UTEP_V)<<(MCPWM_GEN1_B_UTEP_S))
+#define MCPWM_GEN1_B_UTEP_V  0x3
+#define MCPWM_GEN1_B_UTEP_S  2
+/* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN1_B_UTEZ  0x00000003
+#define MCPWM_GEN1_B_UTEZ_M  ((MCPWM_GEN1_B_UTEZ_V)<<(MCPWM_GEN1_B_UTEZ_S))
+#define MCPWM_GEN1_B_UTEZ_V  0x3
+#define MCPWM_GEN1_B_UTEZ_S  0
+
+#define MCPWM_DT1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0090)
+/* MCPWM_DT1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Dead time generator 1 clock selection. 0: PWM_clk  1: PT_clk*/
+#define MCPWM_DT1_CLK_SEL  (BIT(17))
+#define MCPWM_DT1_CLK_SEL_M  (BIT(17))
+#define MCPWM_DT1_CLK_SEL_V  0x1
+#define MCPWM_DT1_CLK_SEL_S  17
+/* MCPWM_DT1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: S0 in documentation*/
+#define MCPWM_DT1_B_OUTBYPASS  (BIT(16))
+#define MCPWM_DT1_B_OUTBYPASS_M  (BIT(16))
+#define MCPWM_DT1_B_OUTBYPASS_V  0x1
+#define MCPWM_DT1_B_OUTBYPASS_S  16
+/* MCPWM_DT1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: S1 in documentation*/
+#define MCPWM_DT1_A_OUTBYPASS  (BIT(15))
+#define MCPWM_DT1_A_OUTBYPASS_M  (BIT(15))
+#define MCPWM_DT1_A_OUTBYPASS_V  0x1
+#define MCPWM_DT1_A_OUTBYPASS_S  15
+/* MCPWM_DT1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: S3 in documentation*/
+#define MCPWM_DT1_FED_OUTINVERT  (BIT(14))
+#define MCPWM_DT1_FED_OUTINVERT_M  (BIT(14))
+#define MCPWM_DT1_FED_OUTINVERT_V  0x1
+#define MCPWM_DT1_FED_OUTINVERT_S  14
+/* MCPWM_DT1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: S2 in documentation*/
+#define MCPWM_DT1_RED_OUTINVERT  (BIT(13))
+#define MCPWM_DT1_RED_OUTINVERT_M  (BIT(13))
+#define MCPWM_DT1_RED_OUTINVERT_V  0x1
+#define MCPWM_DT1_RED_OUTINVERT_S  13
+/* MCPWM_DT1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: S5 in documentation*/
+#define MCPWM_DT1_FED_INSEL  (BIT(12))
+#define MCPWM_DT1_FED_INSEL_M  (BIT(12))
+#define MCPWM_DT1_FED_INSEL_V  0x1
+#define MCPWM_DT1_FED_INSEL_S  12
+/* MCPWM_DT1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: S4 in documentation*/
+#define MCPWM_DT1_RED_INSEL  (BIT(11))
+#define MCPWM_DT1_RED_INSEL_M  (BIT(11))
+#define MCPWM_DT1_RED_INSEL_V  0x1
+#define MCPWM_DT1_RED_INSEL_S  11
+/* MCPWM_DT1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: S7 in documentation*/
+#define MCPWM_DT1_B_OUTSWAP  (BIT(10))
+#define MCPWM_DT1_B_OUTSWAP_M  (BIT(10))
+#define MCPWM_DT1_B_OUTSWAP_V  0x1
+#define MCPWM_DT1_B_OUTSWAP_S  10
+/* MCPWM_DT1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: S6 in documentation*/
+#define MCPWM_DT1_A_OUTSWAP  (BIT(9))
+#define MCPWM_DT1_A_OUTSWAP_M  (BIT(9))
+#define MCPWM_DT1_A_OUTSWAP_V  0x1
+#define MCPWM_DT1_A_OUTSWAP_S  9
+/* MCPWM_DT1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
+ on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
+#define MCPWM_DT1_DEB_MODE  (BIT(8))
+#define MCPWM_DT1_DEB_MODE_M  (BIT(8))
+#define MCPWM_DT1_DEB_MODE_V  0x1
+#define MCPWM_DT1_DEB_MODE_S  8
+/* MCPWM_DT1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for RED (rising edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT1_RED_UPMETHOD  0x0000000F
+#define MCPWM_DT1_RED_UPMETHOD_M  ((MCPWM_DT1_RED_UPMETHOD_V)<<(MCPWM_DT1_RED_UPMETHOD_S))
+#define MCPWM_DT1_RED_UPMETHOD_V  0xF
+#define MCPWM_DT1_RED_UPMETHOD_S  4
+/* MCPWM_DT1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for FED (falling edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT1_FED_UPMETHOD  0x0000000F
+#define MCPWM_DT1_FED_UPMETHOD_M  ((MCPWM_DT1_FED_UPMETHOD_V)<<(MCPWM_DT1_FED_UPMETHOD_S))
+#define MCPWM_DT1_FED_UPMETHOD_V  0xF
+#define MCPWM_DT1_FED_UPMETHOD_S  0
+
+#define MCPWM_DT1_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0094)
+/* MCPWM_DT1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for FED*/
+#define MCPWM_DT1_FED  0x0000FFFF
+#define MCPWM_DT1_FED_M  ((MCPWM_DT1_FED_V)<<(MCPWM_DT1_FED_S))
+#define MCPWM_DT1_FED_V  0xFFFF
+#define MCPWM_DT1_FED_S  0
+
+#define MCPWM_DT1_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0098)
+/* MCPWM_DT1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for RED*/
+#define MCPWM_DT1_RED  0x0000FFFF
+#define MCPWM_DT1_RED_M  ((MCPWM_DT1_RED_V)<<(MCPWM_DT1_RED_S))
+#define MCPWM_DT1_RED_V  0xFFFF
+#define MCPWM_DT1_RED_S  0
+
+#define MCPWM_CARRIER1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x009c)
+/* MCPWM_CARRIER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: When set  invert the input of PWM1A and PWM1B for this submodule*/
+#define MCPWM_CARRIER1_IN_INVERT  (BIT(13))
+#define MCPWM_CARRIER1_IN_INVERT_M  (BIT(13))
+#define MCPWM_CARRIER1_IN_INVERT_V  0x1
+#define MCPWM_CARRIER1_IN_INVERT_S  13
+/* MCPWM_CARRIER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: When set  invert the output of PWM1A and PWM1B for this submodule*/
+#define MCPWM_CARRIER1_OUT_INVERT  (BIT(12))
+#define MCPWM_CARRIER1_OUT_INVERT_M  (BIT(12))
+#define MCPWM_CARRIER1_OUT_INVERT_V  0x1
+#define MCPWM_CARRIER1_OUT_INVERT_S  12
+/* MCPWM_CARRIER1_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Width of the fist pulse in number of periods of the carrier*/
+#define MCPWM_CARRIER1_OSHWTH  0x0000000F
+#define MCPWM_CARRIER1_OSHWTH_M  ((MCPWM_CARRIER1_OSHWTH_V)<<(MCPWM_CARRIER1_OSHWTH_S))
+#define MCPWM_CARRIER1_OSHWTH_V  0xF
+#define MCPWM_CARRIER1_OSHWTH_S  8
+/* MCPWM_CARRIER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
+/*description: Carrier duty selection. Duty = PWM_CARRIER1_DUTY / 8*/
+#define MCPWM_CARRIER1_DUTY  0x00000007
+#define MCPWM_CARRIER1_DUTY_M  ((MCPWM_CARRIER1_DUTY_V)<<(MCPWM_CARRIER1_DUTY_S))
+#define MCPWM_CARRIER1_DUTY_V  0x7
+#define MCPWM_CARRIER1_DUTY_S  5
+/* MCPWM_CARRIER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk
+ = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1)*/
+#define MCPWM_CARRIER1_PRESCALE  0x0000000F
+#define MCPWM_CARRIER1_PRESCALE_M  ((MCPWM_CARRIER1_PRESCALE_V)<<(MCPWM_CARRIER1_PRESCALE_S))
+#define MCPWM_CARRIER1_PRESCALE_V  0xF
+#define MCPWM_CARRIER1_PRESCALE_S  1
+/* MCPWM_CARRIER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  carrier1 function is enabled. When cleared  carrier1 is bypassed*/
+#define MCPWM_CARRIER1_EN  (BIT(0))
+#define MCPWM_CARRIER1_EN_M  (BIT(0))
+#define MCPWM_CARRIER1_EN_V  0x1
+#define MCPWM_CARRIER1_EN_S  0
+
+#define MCPWM_FH1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00a0)
+/* MCPWM_FH1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1B when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_OST_U  0x00000003
+#define MCPWM_FH1_B_OST_U_M  ((MCPWM_FH1_B_OST_U_V)<<(MCPWM_FH1_B_OST_U_S))
+#define MCPWM_FH1_B_OST_U_V  0x3
+#define MCPWM_FH1_B_OST_U_S  22
+/* MCPWM_FH1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1B when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_OST_D  0x00000003
+#define MCPWM_FH1_B_OST_D_M  ((MCPWM_FH1_B_OST_D_V)<<(MCPWM_FH1_B_OST_D_S))
+#define MCPWM_FH1_B_OST_D_V  0x3
+#define MCPWM_FH1_B_OST_D_S  20
+/* MCPWM_FH1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_CBC_U  0x00000003
+#define MCPWM_FH1_B_CBC_U_M  ((MCPWM_FH1_B_CBC_U_V)<<(MCPWM_FH1_B_CBC_U_S))
+#define MCPWM_FH1_B_CBC_U_V  0x3
+#define MCPWM_FH1_B_CBC_U_S  18
+/* MCPWM_FH1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_CBC_D  0x00000003
+#define MCPWM_FH1_B_CBC_D_M  ((MCPWM_FH1_B_CBC_D_V)<<(MCPWM_FH1_B_CBC_D_S))
+#define MCPWM_FH1_B_CBC_D_V  0x3
+#define MCPWM_FH1_B_CBC_D_S  16
+/* MCPWM_FH1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1A when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_OST_U  0x00000003
+#define MCPWM_FH1_A_OST_U_M  ((MCPWM_FH1_A_OST_U_V)<<(MCPWM_FH1_A_OST_U_S))
+#define MCPWM_FH1_A_OST_U_V  0x3
+#define MCPWM_FH1_A_OST_U_S  14
+/* MCPWM_FH1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1A when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_OST_D  0x00000003
+#define MCPWM_FH1_A_OST_D_M  ((MCPWM_FH1_A_OST_D_V)<<(MCPWM_FH1_A_OST_D_S))
+#define MCPWM_FH1_A_OST_D_V  0x3
+#define MCPWM_FH1_A_OST_D_S  12
+/* MCPWM_FH1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_CBC_U  0x00000003
+#define MCPWM_FH1_A_CBC_U_M  ((MCPWM_FH1_A_CBC_U_V)<<(MCPWM_FH1_A_CBC_U_S))
+#define MCPWM_FH1_A_CBC_U_V  0x3
+#define MCPWM_FH1_A_CBC_U_S  10
+/* MCPWM_FH1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_CBC_D  0x00000003
+#define MCPWM_FH1_A_CBC_D_M  ((MCPWM_FH1_A_CBC_D_V)<<(MCPWM_FH1_A_CBC_D_S))
+#define MCPWM_FH1_A_CBC_D_V  0x3
+#define MCPWM_FH1_A_CBC_D_S  8
+/* MCPWM_FH1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F0_OST  (BIT(7))
+#define MCPWM_FH1_F0_OST_M  (BIT(7))
+#define MCPWM_FH1_F0_OST_V  0x1
+#define MCPWM_FH1_F0_OST_S  7
+/* MCPWM_FH1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F1_OST  (BIT(6))
+#define MCPWM_FH1_F1_OST_M  (BIT(6))
+#define MCPWM_FH1_F1_OST_V  0x1
+#define MCPWM_FH1_F1_OST_S  6
+/* MCPWM_FH1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F2_OST  (BIT(5))
+#define MCPWM_FH1_F2_OST_M  (BIT(5))
+#define MCPWM_FH1_F2_OST_V  0x1
+#define MCPWM_FH1_F2_OST_S  5
+/* MCPWM_FH1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_SW_OST  (BIT(4))
+#define MCPWM_FH1_SW_OST_M  (BIT(4))
+#define MCPWM_FH1_SW_OST_V  0x1
+#define MCPWM_FH1_SW_OST_S  4
+/* MCPWM_FH1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F0_CBC  (BIT(3))
+#define MCPWM_FH1_F0_CBC_M  (BIT(3))
+#define MCPWM_FH1_F0_CBC_V  0x1
+#define MCPWM_FH1_F0_CBC_S  3
+/* MCPWM_FH1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F1_CBC  (BIT(2))
+#define MCPWM_FH1_F1_CBC_M  (BIT(2))
+#define MCPWM_FH1_F1_CBC_V  0x1
+#define MCPWM_FH1_F1_CBC_S  2
+/* MCPWM_FH1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F2_CBC  (BIT(1))
+#define MCPWM_FH1_F2_CBC_M  (BIT(1))
+#define MCPWM_FH1_F2_CBC_V  0x1
+#define MCPWM_FH1_F2_CBC_S  1
+/* MCPWM_FH1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Enable register for software force cycle-by-cycle mode action.
+ 0: disable  1: enable*/
+#define MCPWM_FH1_SW_CBC  (BIT(0))
+#define MCPWM_FH1_SW_CBC_M  (BIT(0))
+#define MCPWM_FH1_SW_CBC_V  0x1
+#define MCPWM_FH1_SW_CBC_S  0
+
+#define MCPWM_FH1_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x00a4)
+/* MCPWM_FH1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) triggers a
+ one-shot mode action*/
+#define MCPWM_FH1_FORCE_OST  (BIT(4))
+#define MCPWM_FH1_FORCE_OST_M  (BIT(4))
+#define MCPWM_FH1_FORCE_OST_V  0x1
+#define MCPWM_FH1_FORCE_OST_S  4
+/* MCPWM_FH1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle triggers a cycle-by-cycle mode action*/
+#define MCPWM_FH1_FORCE_CBC  (BIT(3))
+#define MCPWM_FH1_FORCE_CBC_M  (BIT(3))
+#define MCPWM_FH1_FORCE_CBC_V  0x1
+#define MCPWM_FH1_FORCE_CBC_S  3
+/* MCPWM_FH1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
+#define MCPWM_FH1_CBCPULSE  0x00000003
+#define MCPWM_FH1_CBCPULSE_M  ((MCPWM_FH1_CBCPULSE_V)<<(MCPWM_FH1_CBCPULSE_S))
+#define MCPWM_FH1_CBCPULSE_V  0x3
+#define MCPWM_FH1_CBCPULSE_S  1
+/* MCPWM_FH1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: A toggle will clear on going one-shot mode action*/
+#define MCPWM_FH1_CLR_OST  (BIT(0))
+#define MCPWM_FH1_CLR_OST_M  (BIT(0))
+#define MCPWM_FH1_CLR_OST_V  0x1
+#define MCPWM_FH1_CLR_OST_S  0
+
+#define MCPWM_FH1_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x00a8)
+/* MCPWM_FH1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
+#define MCPWM_FH1_OST_ON  (BIT(1))
+#define MCPWM_FH1_OST_ON_M  (BIT(1))
+#define MCPWM_FH1_OST_ON_V  0x1
+#define MCPWM_FH1_OST_ON_S  1
+/* MCPWM_FH1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
+#define MCPWM_FH1_CBC_ON  (BIT(0))
+#define MCPWM_FH1_CBC_ON_M  (BIT(0))
+#define MCPWM_FH1_CBC_ON_V  0x1
+#define MCPWM_FH1_CBC_ON_S  0
+
+#define MCPWM_GEN2_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00ac)
+/* MCPWM_GEN2_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 2 time stamp
+ B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN2_B_SHDW_FULL  (BIT(9))
+#define MCPWM_GEN2_B_SHDW_FULL_M  (BIT(9))
+#define MCPWM_GEN2_B_SHDW_FULL_V  0x1
+#define MCPWM_GEN2_B_SHDW_FULL_S  9
+/* MCPWM_GEN2_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 2 time stamp
+ A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN2_A_SHDW_FULL  (BIT(8))
+#define MCPWM_GEN2_A_SHDW_FULL_M  (BIT(8))
+#define MCPWM_GEN2_A_SHDW_FULL_V  0x1
+#define MCPWM_GEN2_A_SHDW_FULL_S  8
+/* MCPWM_GEN2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 2 time stamp B's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN2_B_UPMETHOD  0x0000000F
+#define MCPWM_GEN2_B_UPMETHOD_M  ((MCPWM_GEN2_B_UPMETHOD_V)<<(MCPWM_GEN2_B_UPMETHOD_S))
+#define MCPWM_GEN2_B_UPMETHOD_V  0xF
+#define MCPWM_GEN2_B_UPMETHOD_S  4
+/* MCPWM_GEN2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 2 time stamp A's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN2_A_UPMETHOD  0x0000000F
+#define MCPWM_GEN2_A_UPMETHOD_M  ((MCPWM_GEN2_A_UPMETHOD_V)<<(MCPWM_GEN2_A_UPMETHOD_S))
+#define MCPWM_GEN2_A_UPMETHOD_V  0xF
+#define MCPWM_GEN2_A_UPMETHOD_S  0
+
+#define MCPWM_GEN2_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x00b0)
+/* MCPWM_GEN2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 2 time stamp A's shadow reg*/
+#define MCPWM_GEN2_A  0x0000FFFF
+#define MCPWM_GEN2_A_M  ((MCPWM_GEN2_A_V)<<(MCPWM_GEN2_A_S))
+#define MCPWM_GEN2_A_V  0xFFFF
+#define MCPWM_GEN2_A_S  0
+
+#define MCPWM_GEN2_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x00b4)
+/* MCPWM_GEN2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 2 time stamp B's shadow reg*/
+#define MCPWM_GEN2_B  0x0000FFFF
+#define MCPWM_GEN2_B_M  ((MCPWM_GEN2_B_V)<<(MCPWM_GEN2_B_S))
+#define MCPWM_GEN2_B_V  0xFFFF
+#define MCPWM_GEN2_B_S  0
+
+#define MCPWM_GEN2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00b8)
+/* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate2 event_t1  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN2_T1_SEL  0x00000007
+#define MCPWM_GEN2_T1_SEL_M  ((MCPWM_GEN2_T1_SEL_V)<<(MCPWM_GEN2_T1_SEL_S))
+#define MCPWM_GEN2_T1_SEL_V  0x7
+#define MCPWM_GEN2_T1_SEL_S  7
+/* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate2 event_t0  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN2_T0_SEL  0x00000007
+#define MCPWM_GEN2_T0_SEL_M  ((MCPWM_GEN2_T0_SEL_V)<<(MCPWM_GEN2_T0_SEL_S))
+#define MCPWM_GEN2_T0_SEL_V  0x7
+#define MCPWM_GEN2_T0_SEL_S  4
+/* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generate2's active reg of configuration.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
+#define MCPWM_GEN2_CFG_UPMETHOD  0x0000000F
+#define MCPWM_GEN2_CFG_UPMETHOD_M  ((MCPWM_GEN2_CFG_UPMETHOD_V)<<(MCPWM_GEN2_CFG_UPMETHOD_S))
+#define MCPWM_GEN2_CFG_UPMETHOD_V  0xF
+#define MCPWM_GEN2_CFG_UPMETHOD_S  0
+
+#define MCPWM_GEN2_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x00bc)
+/* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM2B  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN2_B_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN2_B_NCIFORCE_MODE_M  ((MCPWM_GEN2_B_NCIFORCE_MODE_V)<<(MCPWM_GEN2_B_NCIFORCE_MODE_S))
+#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
+/* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM2B  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN2_B_NCIFORCE  (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_M  (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_V  0x1
+#define MCPWM_GEN2_B_NCIFORCE_S  13
+/* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM2A  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN2_A_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN2_A_NCIFORCE_MODE_M  ((MCPWM_GEN2_A_NCIFORCE_MODE_V)<<(MCPWM_GEN2_A_NCIFORCE_MODE_S))
+#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
+/* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM2A  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN2_A_NCIFORCE  (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_M  (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_V  0x1
+#define MCPWM_GEN2_A_NCIFORCE_S  10
+/* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM2B. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN2_B_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  ((MCPWM_GEN2_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_B_CNTUFORCE_MODE_S))
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
+/* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM2A. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN2_A_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  ((MCPWM_GEN2_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_A_CNTUFORCE_MODE_S))
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
+/* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: Update method for continuous software force of PWM generator2.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD  0x0000003F
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN2_CNTUFORCE_UPMETHOD_S))
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x3F
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
+
+#define MCPWM_GEN2_A_REG(i)          (REG_MCPWM_BASE(i) + 0x00c0)
+/* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN2_A_DT1  0x00000003
+#define MCPWM_GEN2_A_DT1_M  ((MCPWM_GEN2_A_DT1_V)<<(MCPWM_GEN2_A_DT1_S))
+#define MCPWM_GEN2_A_DT1_V  0x3
+#define MCPWM_GEN2_A_DT1_S  22
+/* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN2_A_DT0  0x00000003
+#define MCPWM_GEN2_A_DT0_M  ((MCPWM_GEN2_A_DT0_V)<<(MCPWM_GEN2_A_DT0_S))
+#define MCPWM_GEN2_A_DT0_V  0x3
+#define MCPWM_GEN2_A_DT0_S  20
+/* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN2_A_DTEB  0x00000003
+#define MCPWM_GEN2_A_DTEB_M  ((MCPWM_GEN2_A_DTEB_V)<<(MCPWM_GEN2_A_DTEB_S))
+#define MCPWM_GEN2_A_DTEB_V  0x3
+#define MCPWM_GEN2_A_DTEB_S  18
+/* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN2_A_DTEA  0x00000003
+#define MCPWM_GEN2_A_DTEA_M  ((MCPWM_GEN2_A_DTEA_V)<<(MCPWM_GEN2_A_DTEA_S))
+#define MCPWM_GEN2_A_DTEA_V  0x3
+#define MCPWM_GEN2_A_DTEA_S  16
+/* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN2_A_DTEP  0x00000003
+#define MCPWM_GEN2_A_DTEP_M  ((MCPWM_GEN2_A_DTEP_V)<<(MCPWM_GEN2_A_DTEP_S))
+#define MCPWM_GEN2_A_DTEP_V  0x3
+#define MCPWM_GEN2_A_DTEP_S  14
+/* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN2_A_DTEZ  0x00000003
+#define MCPWM_GEN2_A_DTEZ_M  ((MCPWM_GEN2_A_DTEZ_V)<<(MCPWM_GEN2_A_DTEZ_S))
+#define MCPWM_GEN2_A_DTEZ_V  0x3
+#define MCPWM_GEN2_A_DTEZ_S  12
+/* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN2_A_UT1  0x00000003
+#define MCPWM_GEN2_A_UT1_M  ((MCPWM_GEN2_A_UT1_V)<<(MCPWM_GEN2_A_UT1_S))
+#define MCPWM_GEN2_A_UT1_V  0x3
+#define MCPWM_GEN2_A_UT1_S  10
+/* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN2_A_UT0  0x00000003
+#define MCPWM_GEN2_A_UT0_M  ((MCPWM_GEN2_A_UT0_V)<<(MCPWM_GEN2_A_UT0_S))
+#define MCPWM_GEN2_A_UT0_V  0x3
+#define MCPWM_GEN2_A_UT0_S  8
+/* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEB when timer increasing*/
+#define MCPWM_GEN2_A_UTEB  0x00000003
+#define MCPWM_GEN2_A_UTEB_M  ((MCPWM_GEN2_A_UTEB_V)<<(MCPWM_GEN2_A_UTEB_S))
+#define MCPWM_GEN2_A_UTEB_V  0x3
+#define MCPWM_GEN2_A_UTEB_S  6
+/* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEA when timer increasing*/
+#define MCPWM_GEN2_A_UTEA  0x00000003
+#define MCPWM_GEN2_A_UTEA_M  ((MCPWM_GEN2_A_UTEA_V)<<(MCPWM_GEN2_A_UTEA_S))
+#define MCPWM_GEN2_A_UTEA_V  0x3
+#define MCPWM_GEN2_A_UTEA_S  4
+/* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEP when timer increasing*/
+#define MCPWM_GEN2_A_UTEP  0x00000003
+#define MCPWM_GEN2_A_UTEP_M  ((MCPWM_GEN2_A_UTEP_V)<<(MCPWM_GEN2_A_UTEP_S))
+#define MCPWM_GEN2_A_UTEP_V  0x3
+#define MCPWM_GEN2_A_UTEP_S  2
+/* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN2_A_UTEZ  0x00000003
+#define MCPWM_GEN2_A_UTEZ_M  ((MCPWM_GEN2_A_UTEZ_V)<<(MCPWM_GEN2_A_UTEZ_S))
+#define MCPWM_GEN2_A_UTEZ_V  0x3
+#define MCPWM_GEN2_A_UTEZ_S  0
+
+#define MCPWM_GEN2_B_REG(i)          (REG_MCPWM_BASE(i) + 0x00c4)
+/* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN2_B_DT1  0x00000003
+#define MCPWM_GEN2_B_DT1_M  ((MCPWM_GEN2_B_DT1_V)<<(MCPWM_GEN2_B_DT1_S))
+#define MCPWM_GEN2_B_DT1_V  0x3
+#define MCPWM_GEN2_B_DT1_S  22
+/* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN2_B_DT0  0x00000003
+#define MCPWM_GEN2_B_DT0_M  ((MCPWM_GEN2_B_DT0_V)<<(MCPWM_GEN2_B_DT0_S))
+#define MCPWM_GEN2_B_DT0_V  0x3
+#define MCPWM_GEN2_B_DT0_S  20
+/* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN2_B_DTEB  0x00000003
+#define MCPWM_GEN2_B_DTEB_M  ((MCPWM_GEN2_B_DTEB_V)<<(MCPWM_GEN2_B_DTEB_S))
+#define MCPWM_GEN2_B_DTEB_V  0x3
+#define MCPWM_GEN2_B_DTEB_S  18
+/* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN2_B_DTEA  0x00000003
+#define MCPWM_GEN2_B_DTEA_M  ((MCPWM_GEN2_B_DTEA_V)<<(MCPWM_GEN2_B_DTEA_S))
+#define MCPWM_GEN2_B_DTEA_V  0x3
+#define MCPWM_GEN2_B_DTEA_S  16
+/* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN2_B_DTEP  0x00000003
+#define MCPWM_GEN2_B_DTEP_M  ((MCPWM_GEN2_B_DTEP_V)<<(MCPWM_GEN2_B_DTEP_S))
+#define MCPWM_GEN2_B_DTEP_V  0x3
+#define MCPWM_GEN2_B_DTEP_S  14
+/* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN2_B_DTEZ  0x00000003
+#define MCPWM_GEN2_B_DTEZ_M  ((MCPWM_GEN2_B_DTEZ_V)<<(MCPWM_GEN2_B_DTEZ_S))
+#define MCPWM_GEN2_B_DTEZ_V  0x3
+#define MCPWM_GEN2_B_DTEZ_S  12
+/* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN2_B_UT1  0x00000003
+#define MCPWM_GEN2_B_UT1_M  ((MCPWM_GEN2_B_UT1_V)<<(MCPWM_GEN2_B_UT1_S))
+#define MCPWM_GEN2_B_UT1_V  0x3
+#define MCPWM_GEN2_B_UT1_S  10
+/* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN2_B_UT0  0x00000003
+#define MCPWM_GEN2_B_UT0_M  ((MCPWM_GEN2_B_UT0_V)<<(MCPWM_GEN2_B_UT0_S))
+#define MCPWM_GEN2_B_UT0_V  0x3
+#define MCPWM_GEN2_B_UT0_S  8
+/* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEB when timer increasing*/
+#define MCPWM_GEN2_B_UTEB  0x00000003
+#define MCPWM_GEN2_B_UTEB_M  ((MCPWM_GEN2_B_UTEB_V)<<(MCPWM_GEN2_B_UTEB_S))
+#define MCPWM_GEN2_B_UTEB_V  0x3
+#define MCPWM_GEN2_B_UTEB_S  6
+/* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEA when timer increasing*/
+#define MCPWM_GEN2_B_UTEA  0x00000003
+#define MCPWM_GEN2_B_UTEA_M  ((MCPWM_GEN2_B_UTEA_V)<<(MCPWM_GEN2_B_UTEA_S))
+#define MCPWM_GEN2_B_UTEA_V  0x3
+#define MCPWM_GEN2_B_UTEA_S  4
+/* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEP when timer increasing*/
+#define MCPWM_GEN2_B_UTEP  0x00000003
+#define MCPWM_GEN2_B_UTEP_M  ((MCPWM_GEN2_B_UTEP_V)<<(MCPWM_GEN2_B_UTEP_S))
+#define MCPWM_GEN2_B_UTEP_V  0x3
+#define MCPWM_GEN2_B_UTEP_S  2
+/* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN2_B_UTEZ  0x00000003
+#define MCPWM_GEN2_B_UTEZ_M  ((MCPWM_GEN2_B_UTEZ_V)<<(MCPWM_GEN2_B_UTEZ_S))
+#define MCPWM_GEN2_B_UTEZ_V  0x3
+#define MCPWM_GEN2_B_UTEZ_S  0
+
+#define MCPWM_DT2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00c8)
+/* MCPWM_DT2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Dead time generator 1 clock selection. 0: PWM_clk  1: PT_clk*/
+#define MCPWM_DT2_CLK_SEL  (BIT(17))
+#define MCPWM_DT2_CLK_SEL_M  (BIT(17))
+#define MCPWM_DT2_CLK_SEL_V  0x1
+#define MCPWM_DT2_CLK_SEL_S  17
+/* MCPWM_DT2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: S0 in documentation*/
+#define MCPWM_DT2_B_OUTBYPASS  (BIT(16))
+#define MCPWM_DT2_B_OUTBYPASS_M  (BIT(16))
+#define MCPWM_DT2_B_OUTBYPASS_V  0x1
+#define MCPWM_DT2_B_OUTBYPASS_S  16
+/* MCPWM_DT2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: S1 in documentation*/
+#define MCPWM_DT2_A_OUTBYPASS  (BIT(15))
+#define MCPWM_DT2_A_OUTBYPASS_M  (BIT(15))
+#define MCPWM_DT2_A_OUTBYPASS_V  0x1
+#define MCPWM_DT2_A_OUTBYPASS_S  15
+/* MCPWM_DT2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: S3 in documentation*/
+#define MCPWM_DT2_FED_OUTINVERT  (BIT(14))
+#define MCPWM_DT2_FED_OUTINVERT_M  (BIT(14))
+#define MCPWM_DT2_FED_OUTINVERT_V  0x1
+#define MCPWM_DT2_FED_OUTINVERT_S  14
+/* MCPWM_DT2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: S2 in documentation*/
+#define MCPWM_DT2_RED_OUTINVERT  (BIT(13))
+#define MCPWM_DT2_RED_OUTINVERT_M  (BIT(13))
+#define MCPWM_DT2_RED_OUTINVERT_V  0x1
+#define MCPWM_DT2_RED_OUTINVERT_S  13
+/* MCPWM_DT2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: S5 in documentation*/
+#define MCPWM_DT2_FED_INSEL  (BIT(12))
+#define MCPWM_DT2_FED_INSEL_M  (BIT(12))
+#define MCPWM_DT2_FED_INSEL_V  0x1
+#define MCPWM_DT2_FED_INSEL_S  12
+/* MCPWM_DT2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: S4 in documentation*/
+#define MCPWM_DT2_RED_INSEL  (BIT(11))
+#define MCPWM_DT2_RED_INSEL_M  (BIT(11))
+#define MCPWM_DT2_RED_INSEL_V  0x1
+#define MCPWM_DT2_RED_INSEL_S  11
+/* MCPWM_DT2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: S7 in documentation*/
+#define MCPWM_DT2_B_OUTSWAP  (BIT(10))
+#define MCPWM_DT2_B_OUTSWAP_M  (BIT(10))
+#define MCPWM_DT2_B_OUTSWAP_V  0x1
+#define MCPWM_DT2_B_OUTSWAP_S  10
+/* MCPWM_DT2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: S6 in documentation*/
+#define MCPWM_DT2_A_OUTSWAP  (BIT(9))
+#define MCPWM_DT2_A_OUTSWAP_M  (BIT(9))
+#define MCPWM_DT2_A_OUTSWAP_V  0x1
+#define MCPWM_DT2_A_OUTSWAP_S  9
+/* MCPWM_DT2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
+ on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
+#define MCPWM_DT2_DEB_MODE  (BIT(8))
+#define MCPWM_DT2_DEB_MODE_M  (BIT(8))
+#define MCPWM_DT2_DEB_MODE_V  0x1
+#define MCPWM_DT2_DEB_MODE_S  8
+/* MCPWM_DT2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for RED (rising edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT2_RED_UPMETHOD  0x0000000F
+#define MCPWM_DT2_RED_UPMETHOD_M  ((MCPWM_DT2_RED_UPMETHOD_V)<<(MCPWM_DT2_RED_UPMETHOD_S))
+#define MCPWM_DT2_RED_UPMETHOD_V  0xF
+#define MCPWM_DT2_RED_UPMETHOD_S  4
+/* MCPWM_DT2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for FED (falling edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT2_FED_UPMETHOD  0x0000000F
+#define MCPWM_DT2_FED_UPMETHOD_M  ((MCPWM_DT2_FED_UPMETHOD_V)<<(MCPWM_DT2_FED_UPMETHOD_S))
+#define MCPWM_DT2_FED_UPMETHOD_V  0xF
+#define MCPWM_DT2_FED_UPMETHOD_S  0
+
+#define MCPWM_DT2_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00cc)
+/* MCPWM_DT2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for FED*/
+#define MCPWM_DT2_FED  0x0000FFFF
+#define MCPWM_DT2_FED_M  ((MCPWM_DT2_FED_V)<<(MCPWM_DT2_FED_S))
+#define MCPWM_DT2_FED_V  0xFFFF
+#define MCPWM_DT2_FED_S  0
+
+#define MCPWM_DT2_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00d0)
+/* MCPWM_DT2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for RED*/
+#define MCPWM_DT2_RED  0x0000FFFF
+#define MCPWM_DT2_RED_M  ((MCPWM_DT2_RED_V)<<(MCPWM_DT2_RED_S))
+#define MCPWM_DT2_RED_V  0xFFFF
+#define MCPWM_DT2_RED_S  0
+
+#define MCPWM_CARRIER2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00d4)
+/* MCPWM_CARRIER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: When set  invert the input of PWM2A and PWM2B for this submodule*/
+#define MCPWM_CARRIER2_IN_INVERT  (BIT(13))
+#define MCPWM_CARRIER2_IN_INVERT_M  (BIT(13))
+#define MCPWM_CARRIER2_IN_INVERT_V  0x1
+#define MCPWM_CARRIER2_IN_INVERT_S  13
+/* MCPWM_CARRIER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: When set  invert the output of PWM2A and PWM2B for this submodule*/
+#define MCPWM_CARRIER2_OUT_INVERT  (BIT(12))
+#define MCPWM_CARRIER2_OUT_INVERT_M  (BIT(12))
+#define MCPWM_CARRIER2_OUT_INVERT_V  0x1
+#define MCPWM_CARRIER2_OUT_INVERT_S  12
+/* MCPWM_CARRIER2_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Width of the fist pulse in number of periods of the carrier*/
+#define MCPWM_CARRIER2_OSHWTH  0x0000000F
+#define MCPWM_CARRIER2_OSHWTH_M  ((MCPWM_CARRIER2_OSHWTH_V)<<(MCPWM_CARRIER2_OSHWTH_S))
+#define MCPWM_CARRIER2_OSHWTH_V  0xF
+#define MCPWM_CARRIER2_OSHWTH_S  8
+/* MCPWM_CARRIER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
+/*description: Carrier duty selection. Duty = PWM_CARRIER2_DUTY / 8*/
+#define MCPWM_CARRIER2_DUTY  0x00000007
+#define MCPWM_CARRIER2_DUTY_M  ((MCPWM_CARRIER2_DUTY_V)<<(MCPWM_CARRIER2_DUTY_S))
+#define MCPWM_CARRIER2_DUTY_V  0x7
+#define MCPWM_CARRIER2_DUTY_S  5
+/* MCPWM_CARRIER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk
+ = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1)*/
+#define MCPWM_CARRIER2_PRESCALE  0x0000000F
+#define MCPWM_CARRIER2_PRESCALE_M  ((MCPWM_CARRIER2_PRESCALE_V)<<(MCPWM_CARRIER2_PRESCALE_S))
+#define MCPWM_CARRIER2_PRESCALE_V  0xF
+#define MCPWM_CARRIER2_PRESCALE_S  1
+/* MCPWM_CARRIER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  carrier2 function is enabled. When cleared  carrier2 is bypassed*/
+#define MCPWM_CARRIER2_EN  (BIT(0))
+#define MCPWM_CARRIER2_EN_M  (BIT(0))
+#define MCPWM_CARRIER2_EN_V  0x1
+#define MCPWM_CARRIER2_EN_S  0
+
+#define MCPWM_FH2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00d8)
+/* MCPWM_FH2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2B when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_OST_U  0x00000003
+#define MCPWM_FH2_B_OST_U_M  ((MCPWM_FH2_B_OST_U_V)<<(MCPWM_FH2_B_OST_U_S))
+#define MCPWM_FH2_B_OST_U_V  0x3
+#define MCPWM_FH2_B_OST_U_S  22
+/* MCPWM_FH2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2B when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_OST_D  0x00000003
+#define MCPWM_FH2_B_OST_D_M  ((MCPWM_FH2_B_OST_D_V)<<(MCPWM_FH2_B_OST_D_S))
+#define MCPWM_FH2_B_OST_D_V  0x3
+#define MCPWM_FH2_B_OST_D_S  20
+/* MCPWM_FH2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_CBC_U  0x00000003
+#define MCPWM_FH2_B_CBC_U_M  ((MCPWM_FH2_B_CBC_U_V)<<(MCPWM_FH2_B_CBC_U_S))
+#define MCPWM_FH2_B_CBC_U_V  0x3
+#define MCPWM_FH2_B_CBC_U_S  18
+/* MCPWM_FH2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_CBC_D  0x00000003
+#define MCPWM_FH2_B_CBC_D_M  ((MCPWM_FH2_B_CBC_D_V)<<(MCPWM_FH2_B_CBC_D_S))
+#define MCPWM_FH2_B_CBC_D_V  0x3
+#define MCPWM_FH2_B_CBC_D_S  16
+/* MCPWM_FH2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2A when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_OST_U  0x00000003
+#define MCPWM_FH2_A_OST_U_M  ((MCPWM_FH2_A_OST_U_V)<<(MCPWM_FH2_A_OST_U_S))
+#define MCPWM_FH2_A_OST_U_V  0x3
+#define MCPWM_FH2_A_OST_U_S  14
+/* MCPWM_FH2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2A when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_OST_D  0x00000003
+#define MCPWM_FH2_A_OST_D_M  ((MCPWM_FH2_A_OST_D_V)<<(MCPWM_FH2_A_OST_D_S))
+#define MCPWM_FH2_A_OST_D_V  0x3
+#define MCPWM_FH2_A_OST_D_S  12
+/* MCPWM_FH2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_CBC_U  0x00000003
+#define MCPWM_FH2_A_CBC_U_M  ((MCPWM_FH2_A_CBC_U_V)<<(MCPWM_FH2_A_CBC_U_S))
+#define MCPWM_FH2_A_CBC_U_V  0x3
+#define MCPWM_FH2_A_CBC_U_S  10
+/* MCPWM_FH2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_CBC_D  0x00000003
+#define MCPWM_FH2_A_CBC_D_M  ((MCPWM_FH2_A_CBC_D_V)<<(MCPWM_FH2_A_CBC_D_S))
+#define MCPWM_FH2_A_CBC_D_V  0x3
+#define MCPWM_FH2_A_CBC_D_S  8
+/* MCPWM_FH2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F0_OST  (BIT(7))
+#define MCPWM_FH2_F0_OST_M  (BIT(7))
+#define MCPWM_FH2_F0_OST_V  0x1
+#define MCPWM_FH2_F0_OST_S  7
+/* MCPWM_FH2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F1_OST  (BIT(6))
+#define MCPWM_FH2_F1_OST_M  (BIT(6))
+#define MCPWM_FH2_F1_OST_V  0x1
+#define MCPWM_FH2_F1_OST_S  6
+/* MCPWM_FH2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F2_OST  (BIT(5))
+#define MCPWM_FH2_F2_OST_M  (BIT(5))
+#define MCPWM_FH2_F2_OST_V  0x1
+#define MCPWM_FH2_F2_OST_S  5
+/* MCPWM_FH2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_SW_OST  (BIT(4))
+#define MCPWM_FH2_SW_OST_M  (BIT(4))
+#define MCPWM_FH2_SW_OST_V  0x1
+#define MCPWM_FH2_SW_OST_S  4
+/* MCPWM_FH2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F0_CBC  (BIT(3))
+#define MCPWM_FH2_F0_CBC_M  (BIT(3))
+#define MCPWM_FH2_F0_CBC_V  0x1
+#define MCPWM_FH2_F0_CBC_S  3
+/* MCPWM_FH2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F1_CBC  (BIT(2))
+#define MCPWM_FH2_F1_CBC_M  (BIT(2))
+#define MCPWM_FH2_F1_CBC_V  0x1
+#define MCPWM_FH2_F1_CBC_S  2
+/* MCPWM_FH2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F2_CBC  (BIT(1))
+#define MCPWM_FH2_F2_CBC_M  (BIT(1))
+#define MCPWM_FH2_F2_CBC_V  0x1
+#define MCPWM_FH2_F2_CBC_S  1
+/* MCPWM_FH2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Enable register for software force cycle-by-cycle mode action.
+ 0: disable  1: enable*/
+#define MCPWM_FH2_SW_CBC  (BIT(0))
+#define MCPWM_FH2_SW_CBC_M  (BIT(0))
+#define MCPWM_FH2_SW_CBC_V  0x1
+#define MCPWM_FH2_SW_CBC_S  0
+
+#define MCPWM_FH2_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x00dc)
+/* MCPWM_FH2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) triggers a
+ one-shot mode action*/
+#define MCPWM_FH2_FORCE_OST  (BIT(4))
+#define MCPWM_FH2_FORCE_OST_M  (BIT(4))
+#define MCPWM_FH2_FORCE_OST_V  0x1
+#define MCPWM_FH2_FORCE_OST_S  4
+/* MCPWM_FH2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle triggers a cycle-by-cycle mode action*/
+#define MCPWM_FH2_FORCE_CBC  (BIT(3))
+#define MCPWM_FH2_FORCE_CBC_M  (BIT(3))
+#define MCPWM_FH2_FORCE_CBC_V  0x1
+#define MCPWM_FH2_FORCE_CBC_S  3
+/* MCPWM_FH2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
+#define MCPWM_FH2_CBCPULSE  0x00000003
+#define MCPWM_FH2_CBCPULSE_M  ((MCPWM_FH2_CBCPULSE_V)<<(MCPWM_FH2_CBCPULSE_S))
+#define MCPWM_FH2_CBCPULSE_V  0x3
+#define MCPWM_FH2_CBCPULSE_S  1
+/* MCPWM_FH2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: A toggle will clear on going one-shot mode action*/
+#define MCPWM_FH2_CLR_OST  (BIT(0))
+#define MCPWM_FH2_CLR_OST_M  (BIT(0))
+#define MCPWM_FH2_CLR_OST_V  0x1
+#define MCPWM_FH2_CLR_OST_S  0
+
+#define MCPWM_FH2_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x00e0)
+/* MCPWM_FH2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
+#define MCPWM_FH2_OST_ON  (BIT(1))
+#define MCPWM_FH2_OST_ON_M  (BIT(1))
+#define MCPWM_FH2_OST_ON_V  0x1
+#define MCPWM_FH2_OST_ON_S  1
+/* MCPWM_FH2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
+#define MCPWM_FH2_CBC_ON  (BIT(0))
+#define MCPWM_FH2_CBC_ON_M  (BIT(0))
+#define MCPWM_FH2_CBC_ON_V  0x1
+#define MCPWM_FH2_CBC_ON_S  0
+
+#define MCPWM_FAULT_DETECT_REG(i)          (REG_MCPWM_BASE(i) + 0x00e4)
+/* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  event_f2 is on going*/
+#define MCPWM_EVENT_F2  (BIT(8))
+#define MCPWM_EVENT_F2_M  (BIT(8))
+#define MCPWM_EVENT_F2_V  0x1
+#define MCPWM_EVENT_F2_S  8
+/* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  event_f1 is on going*/
+#define MCPWM_EVENT_F1  (BIT(7))
+#define MCPWM_EVENT_F1_M  (BIT(7))
+#define MCPWM_EVENT_F1_V  0x1
+#define MCPWM_EVENT_F1_S  7
+/* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  event_f0 is on going*/
+#define MCPWM_EVENT_F0  (BIT(6))
+#define MCPWM_EVENT_F0_M  (BIT(6))
+#define MCPWM_EVENT_F0_V  0x1
+#define MCPWM_EVENT_F0_S  6
+/* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: Set event_f2 trigger polarity on FAULT2 source from GPIO matrix.
+ 0: level low  1: level high*/
+#define MCPWM_F2_POLE  (BIT(5))
+#define MCPWM_F2_POLE_M  (BIT(5))
+#define MCPWM_F2_POLE_V  0x1
+#define MCPWM_F2_POLE_S  5
+/* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Set event_f1 trigger polarity on FAULT2 source from GPIO matrix.
+ 0: level low  1: level high*/
+#define MCPWM_F1_POLE  (BIT(4))
+#define MCPWM_F1_POLE_M  (BIT(4))
+#define MCPWM_F1_POLE_V  0x1
+#define MCPWM_F1_POLE_S  4
+/* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: Set event_f0 trigger polarity on FAULT2 source from GPIO matrix.
+ 0: level low  1: level high*/
+#define MCPWM_F0_POLE  (BIT(3))
+#define MCPWM_F0_POLE_M  (BIT(3))
+#define MCPWM_F0_POLE_V  0x1
+#define MCPWM_F0_POLE_S  3
+/* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: Set to enable generation of event_f2*/
+#define MCPWM_F2_EN  (BIT(2))
+#define MCPWM_F2_EN_M  (BIT(2))
+#define MCPWM_F2_EN_V  0x1
+#define MCPWM_F2_EN_S  2
+/* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set to enable generation of event_f1*/
+#define MCPWM_F1_EN  (BIT(1))
+#define MCPWM_F1_EN_M  (BIT(1))
+#define MCPWM_F1_EN_V  0x1
+#define MCPWM_F1_EN_S  1
+/* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set to enable generation of event_f0*/
+#define MCPWM_F0_EN  (BIT(0))
+#define MCPWM_F0_EN_M  (BIT(0))
+#define MCPWM_F0_EN_V  0x1
+#define MCPWM_F0_EN_S  0
+
+#define MCPWM_CAP_TIMER_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00e8)
+/* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */
+/*description: Set this bit to force a capture timer sync  capture timer is
+ loaded with value in phase register.*/
+#define MCPWM_CAP_SYNC_SW  (BIT(5))
+#define MCPWM_CAP_SYNC_SW_M  (BIT(5))
+#define MCPWM_CAP_SYNC_SW_V  0x1
+#define MCPWM_CAP_SYNC_SW_S  5
+/* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: Capture module sync input selection. 0: none  1: timer0 synco
+  2: timer1 synco  3: timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix*/
+#define MCPWM_CAP_SYNCI_SEL  0x00000007
+#define MCPWM_CAP_SYNCI_SEL_M  ((MCPWM_CAP_SYNCI_SEL_V)<<(MCPWM_CAP_SYNCI_SEL_S))
+#define MCPWM_CAP_SYNCI_SEL_V  0x7
+#define MCPWM_CAP_SYNCI_SEL_S  2
+/* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: When set  capture timer sync is enabled.*/
+#define MCPWM_CAP_SYNCI_EN  (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_M  (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_V  0x1
+#define MCPWM_CAP_SYNCI_EN_S  1
+/* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture timer incrementing under APB_clk is enabled.*/
+#define MCPWM_CAP_TIMER_EN  (BIT(0))
+#define MCPWM_CAP_TIMER_EN_M  (BIT(0))
+#define MCPWM_CAP_TIMER_EN_V  0x1
+#define MCPWM_CAP_TIMER_EN_S  0
+
+#define MCPWM_CAP_TIMER_PHASE_REG(i)          (REG_MCPWM_BASE(i) + 0x00ec)
+/* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Phase value for capture timer sync operation.*/
+#define MCPWM_CAP_PHASE  0xFFFFFFFF
+#define MCPWM_CAP_PHASE_M  ((MCPWM_CAP_PHASE_V)<<(MCPWM_CAP_PHASE_S))
+#define MCPWM_CAP_PHASE_V  0xFFFFFFFF
+#define MCPWM_CAP_PHASE_S  0
+
+#define MCPWM_CAP_CH0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f0)
+/* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Write 1 will trigger a software forced capture on channel 0*/
+#define MCPWM_CAP0_SW  (BIT(12))
+#define MCPWM_CAP0_SW_M  (BIT(12))
+#define MCPWM_CAP0_SW_V  0x1
+#define MCPWM_CAP0_SW_S  12
+/* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: When set  CAP0 form GPIO matrix is inverted before prescale*/
+#define MCPWM_CAP0_IN_INVERT  (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_V  0x1
+#define MCPWM_CAP0_IN_INVERT_S  11
+/* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: Value of prescale on possitive edge of CAP0. Prescale value =
+ PWM_CAP0_PRESCALE + 1*/
+#define MCPWM_CAP0_PRESCALE  0x000000FF
+#define MCPWM_CAP0_PRESCALE_M  ((MCPWM_CAP0_PRESCALE_V)<<(MCPWM_CAP0_PRESCALE_S))
+#define MCPWM_CAP0_PRESCALE_V  0xFF
+#define MCPWM_CAP0_PRESCALE_S  3
+/* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: Edge of capture on channel 0 after prescale.  bit0: negedge cap
+ en  bit1: posedge cap en*/
+#define MCPWM_CAP0_MODE  0x00000003
+#define MCPWM_CAP0_MODE_M  ((MCPWM_CAP0_MODE_V)<<(MCPWM_CAP0_MODE_S))
+#define MCPWM_CAP0_MODE_V  0x3
+#define MCPWM_CAP0_MODE_S  1
+/* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture on channel 0 is enabled*/
+#define MCPWM_CAP0_EN  (BIT(0))
+#define MCPWM_CAP0_EN_M  (BIT(0))
+#define MCPWM_CAP0_EN_V  0x1
+#define MCPWM_CAP0_EN_S  0
+
+#define MCPWM_CAP_CH1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f4)
+/* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Write 1 will trigger a software forced capture on channel 1*/
+#define MCPWM_CAP1_SW  (BIT(12))
+#define MCPWM_CAP1_SW_M  (BIT(12))
+#define MCPWM_CAP1_SW_V  0x1
+#define MCPWM_CAP1_SW_S  12
+/* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: When set  CAP1 form GPIO matrix is inverted before prescale*/
+#define MCPWM_CAP1_IN_INVERT  (BIT(11))
+#define MCPWM_CAP1_IN_INVERT_M  (BIT(11))
+#define MCPWM_CAP1_IN_INVERT_V  0x1
+#define MCPWM_CAP1_IN_INVERT_S  11
+/* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: Value of prescale on possitive edge of CAP1. Prescale value =
+ PWM_CAP1_PRESCALE + 1*/
+#define MCPWM_CAP1_PRESCALE  0x000000FF
+#define MCPWM_CAP1_PRESCALE_M  ((MCPWM_CAP1_PRESCALE_V)<<(MCPWM_CAP1_PRESCALE_S))
+#define MCPWM_CAP1_PRESCALE_V  0xFF
+#define MCPWM_CAP1_PRESCALE_S  3
+/* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: Edge of capture on channel 1 after prescale.  bit0: negedge cap
+ en  bit1: posedge cap en*/
+#define MCPWM_CAP1_MODE  0x00000003
+#define MCPWM_CAP1_MODE_M  ((MCPWM_CAP1_MODE_V)<<(MCPWM_CAP1_MODE_S))
+#define MCPWM_CAP1_MODE_V  0x3
+#define MCPWM_CAP1_MODE_S  1
+/* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture on channel 1 is enabled*/
+#define MCPWM_CAP1_EN  (BIT(0))
+#define MCPWM_CAP1_EN_M  (BIT(0))
+#define MCPWM_CAP1_EN_V  0x1
+#define MCPWM_CAP1_EN_S  0
+
+#define MCPWM_CAP_CH2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f8)
+/* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Write 1 will trigger a software forced capture on channel 2*/
+#define MCPWM_CAP2_SW  (BIT(12))
+#define MCPWM_CAP2_SW_M  (BIT(12))
+#define MCPWM_CAP2_SW_V  0x1
+#define MCPWM_CAP2_SW_S  12
+/* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: When set  CAP2 form GPIO matrix is inverted before prescale*/
+#define MCPWM_CAP2_IN_INVERT  (BIT(11))
+#define MCPWM_CAP2_IN_INVERT_M  (BIT(11))
+#define MCPWM_CAP2_IN_INVERT_V  0x1
+#define MCPWM_CAP2_IN_INVERT_S  11
+/* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: Value of prescale on possitive edge of CAP2. Prescale value =
+ PWM_CAP2_PRESCALE + 1*/
+#define MCPWM_CAP2_PRESCALE  0x000000FF
+#define MCPWM_CAP2_PRESCALE_M  ((MCPWM_CAP2_PRESCALE_V)<<(MCPWM_CAP2_PRESCALE_S))
+#define MCPWM_CAP2_PRESCALE_V  0xFF
+#define MCPWM_CAP2_PRESCALE_S  3
+/* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: Edge of capture on channel 2 after prescale.  bit0: negedge cap
+ en  bit1: posedge cap en*/
+#define MCPWM_CAP2_MODE  0x00000003
+#define MCPWM_CAP2_MODE_M  ((MCPWM_CAP2_MODE_V)<<(MCPWM_CAP2_MODE_S))
+#define MCPWM_CAP2_MODE_V  0x3
+#define MCPWM_CAP2_MODE_S  1
+/* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture on channel 2 is enabled*/
+#define MCPWM_CAP2_EN  (BIT(0))
+#define MCPWM_CAP2_EN_M  (BIT(0))
+#define MCPWM_CAP2_EN_V  0x1
+#define MCPWM_CAP2_EN_S  0
+
+#define MCPWM_CAP_CH0_REG(i)          (REG_MCPWM_BASE(i) + 0x00fc)
+/* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Value of last capture on channel 0*/
+#define MCPWM_CAP0_VALUE  0xFFFFFFFF
+#define MCPWM_CAP0_VALUE_M  ((MCPWM_CAP0_VALUE_V)<<(MCPWM_CAP0_VALUE_S))
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFF
+#define MCPWM_CAP0_VALUE_S  0
+
+#define MCPWM_CAP_CH1_REG(i)          (REG_MCPWM_BASE(i) + 0x0100)
+/* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Value of last capture on channel 1*/
+#define MCPWM_CAP1_VALUE  0xFFFFFFFF
+#define MCPWM_CAP1_VALUE_M  ((MCPWM_CAP1_VALUE_V)<<(MCPWM_CAP1_VALUE_S))
+#define MCPWM_CAP1_VALUE_V  0xFFFFFFFF
+#define MCPWM_CAP1_VALUE_S  0
+
+#define MCPWM_CAP_CH2_REG(i)          (REG_MCPWM_BASE(i) + 0x0104)
+/* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Value of last capture on channel 2*/
+#define MCPWM_CAP2_VALUE  0xFFFFFFFF
+#define MCPWM_CAP2_VALUE_M  ((MCPWM_CAP2_VALUE_V)<<(MCPWM_CAP2_VALUE_S))
+#define MCPWM_CAP2_VALUE_V  0xFFFFFFFF
+#define MCPWM_CAP2_VALUE_S  0
+
+#define MCPWM_CAP_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0108)
+/* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */
+/*description: Edge of last capture trigger on channel 2  0: posedge  1: negedge*/
+#define MCPWM_CAP2_EDGE  (BIT(2))
+#define MCPWM_CAP2_EDGE_M  (BIT(2))
+#define MCPWM_CAP2_EDGE_V  0x1
+#define MCPWM_CAP2_EDGE_S  2
+/* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Edge of last capture trigger on channel 1  0: posedge  1: negedge*/
+#define MCPWM_CAP1_EDGE  (BIT(1))
+#define MCPWM_CAP1_EDGE_M  (BIT(1))
+#define MCPWM_CAP1_EDGE_V  0x1
+#define MCPWM_CAP1_EDGE_S  1
+/* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Edge of last capture trigger on channel 0  0: posedge  1: negedge*/
+#define MCPWM_CAP0_EDGE  (BIT(0))
+#define MCPWM_CAP0_EDGE_M  (BIT(0))
+#define MCPWM_CAP0_EDGE_V  0x1
+#define MCPWM_CAP0_EDGE_S  0
+
+#define MCPWM_UPDATE_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x010c)
+/* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of active registers in PWM operator 2*/
+#define MCPWM_OP2_FORCE_UP  (BIT(7))
+#define MCPWM_OP2_FORCE_UP_M  (BIT(7))
+#define MCPWM_OP2_FORCE_UP_V  0x1
+#define MCPWM_OP2_FORCE_UP_S  7
+/* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */
+/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
+ in PWM operator 2 are enabled*/
+#define MCPWM_OP2_UP_EN  (BIT(6))
+#define MCPWM_OP2_UP_EN_M  (BIT(6))
+#define MCPWM_OP2_UP_EN_V  0x1
+#define MCPWM_OP2_UP_EN_S  6
+/* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of active registers in PWM operator 1*/
+#define MCPWM_OP1_FORCE_UP  (BIT(5))
+#define MCPWM_OP1_FORCE_UP_M  (BIT(5))
+#define MCPWM_OP1_FORCE_UP_V  0x1
+#define MCPWM_OP1_FORCE_UP_S  5
+/* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */
+/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
+ in PWM operator 1 are enabled*/
+#define MCPWM_OP1_UP_EN  (BIT(4))
+#define MCPWM_OP1_UP_EN_M  (BIT(4))
+#define MCPWM_OP1_UP_EN_V  0x1
+#define MCPWM_OP1_UP_EN_S  4
+/* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of active registers in PWM operator 0*/
+#define MCPWM_OP0_FORCE_UP  (BIT(3))
+#define MCPWM_OP0_FORCE_UP_M  (BIT(3))
+#define MCPWM_OP0_FORCE_UP_V  0x1
+#define MCPWM_OP0_FORCE_UP_S  3
+/* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */
+/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
+ in PWM operator 0 are enabled*/
+#define MCPWM_OP0_UP_EN  (BIT(2))
+#define MCPWM_OP0_UP_EN_M  (BIT(2))
+#define MCPWM_OP0_UP_EN_V  0x1
+#define MCPWM_OP0_UP_EN_S  2
+/* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of all active registers in MCPWM module*/
+#define MCPWM_GLOBAL_FORCE_UP  (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_M  (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_V  0x1
+#define MCPWM_GLOBAL_FORCE_UP_S  1
+/* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
+/*description: The global enable of update of all active registers in MCPWM module*/
+#define MCPWM_GLOBAL_UP_EN  (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_M  (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_V  0x1
+#define MCPWM_GLOBAL_UP_EN_S  0
+
+#define MCMCPWM_INT_ENA_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0110)
+/* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_ENA  (BIT(29))
+#define MCPWM_CAP2_INT_ENA_M  (BIT(29))
+#define MCPWM_CAP2_INT_ENA_V  0x1
+#define MCPWM_CAP2_INT_ENA_S  29
+/* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_ENA  (BIT(28))
+#define MCPWM_CAP1_INT_ENA_M  (BIT(28))
+#define MCPWM_CAP1_INT_ENA_V  0x1
+#define MCPWM_CAP1_INT_ENA_S  28
+/* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_ENA  (BIT(27))
+#define MCPWM_CAP0_INT_ENA_M  (BIT(27))
+#define MCPWM_CAP0_INT_ENA_V  0x1
+#define MCPWM_CAP0_INT_ENA_S  27
+/* MCPWM_FH2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_ENA  (BIT(26))
+#define MCPWM_FH2_OST_INT_ENA_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_ENA_V  0x1
+#define MCPWM_FH2_OST_INT_ENA_S  26
+/* MCPWM_FH1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_ENA  (BIT(25))
+#define MCPWM_FH1_OST_INT_ENA_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_ENA_V  0x1
+#define MCPWM_FH1_OST_INT_ENA_S  25
+/* MCPWM_FH0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_ENA  (BIT(24))
+#define MCPWM_FH0_OST_INT_ENA_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_ENA_V  0x1
+#define MCPWM_FH0_OST_INT_ENA_S  24
+/* MCPWM_FH2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_ENA  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ENA_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ENA_V  0x1
+#define MCPWM_FH2_CBC_INT_ENA_S  23
+/* MCPWM_FH1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_ENA  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ENA_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ENA_V  0x1
+#define MCPWM_FH1_CBC_INT_ENA_S  22
+/* MCPWM_FH0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_ENA  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ENA_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ENA_V  0x1
+#define MCPWM_FH0_CBC_INT_ENA_S  21
+/* MCPWM_OP2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_ENA  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ENA_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ENA_V  0x1
+#define MCPWM_OP2_TEB_INT_ENA_S  20
+/* MCPWM_OP1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_ENA  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ENA_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ENA_V  0x1
+#define MCPWM_OP1_TEB_INT_ENA_S  19
+/* MCPWM_OP0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_ENA  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ENA_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ENA_V  0x1
+#define MCPWM_OP0_TEB_INT_ENA_S  18
+/* MCPWM_OP2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_ENA  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ENA_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ENA_V  0x1
+#define MCPWM_OP2_TEA_INT_ENA_S  17
+/* MCPWM_OP1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_ENA  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ENA_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ENA_V  0x1
+#define MCPWM_OP1_TEA_INT_ENA_S  16
+/* MCPWM_OP0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_ENA  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ENA_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ENA_V  0x1
+#define MCPWM_OP0_TEA_INT_ENA_S  15
+/* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_ENA  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_V  0x1
+#define MCPWM_FAULT2_CLR_INT_ENA_S  14
+/* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_ENA  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_V  0x1
+#define MCPWM_FAULT1_CLR_INT_ENA_S  13
+/* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_ENA  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_V  0x1
+#define MCPWM_FAULT0_CLR_INT_ENA_S  12
+/* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_ENA  (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_M  (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_V  0x1
+#define MCPWM_FAULT2_INT_ENA_S  11
+/* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_ENA  (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_M  (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_V  0x1
+#define MCPWM_FAULT1_INT_ENA_S  10
+/* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_ENA  (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_M  (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_V  0x1
+#define MCPWM_FAULT0_INT_ENA_S  9
+/* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_ENA  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_V  0x1
+#define MCPWM_TIMER2_TEP_INT_ENA_S  8
+/* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_ENA  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_V  0x1
+#define MCPWM_TIMER1_TEP_INT_ENA_S  7
+/* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_ENA  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_V  0x1
+#define MCPWM_TIMER0_TEP_INT_ENA_S  6
+/* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_ENA  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
+/* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_ENA  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
+/* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_ENA  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
+/* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_ENA  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_V  0x1
+#define MCPWM_TIMER2_STOP_INT_ENA_S  2
+/* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_ENA  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_V  0x1
+#define MCPWM_TIMER1_STOP_INT_ENA_S  1
+/* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_ENA  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_V  0x1
+#define MCPWM_TIMER0_STOP_INT_ENA_S  0
+
+#define MCMCPWM_INT_RAW_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0114)
+/* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_RAW  (BIT(29))
+#define MCPWM_CAP2_INT_RAW_M  (BIT(29))
+#define MCPWM_CAP2_INT_RAW_V  0x1
+#define MCPWM_CAP2_INT_RAW_S  29
+/* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_RAW  (BIT(28))
+#define MCPWM_CAP1_INT_RAW_M  (BIT(28))
+#define MCPWM_CAP1_INT_RAW_V  0x1
+#define MCPWM_CAP1_INT_RAW_S  28
+/* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_RAW  (BIT(27))
+#define MCPWM_CAP0_INT_RAW_M  (BIT(27))
+#define MCPWM_CAP0_INT_RAW_V  0x1
+#define MCPWM_CAP0_INT_RAW_S  27
+/* MCPWM_FH2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_RAW  (BIT(26))
+#define MCPWM_FH2_OST_INT_RAW_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_RAW_V  0x1
+#define MCPWM_FH2_OST_INT_RAW_S  26
+/* MCPWM_FH1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_RAW  (BIT(25))
+#define MCPWM_FH1_OST_INT_RAW_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_RAW_V  0x1
+#define MCPWM_FH1_OST_INT_RAW_S  25
+/* MCPWM_FH0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_RAW  (BIT(24))
+#define MCPWM_FH0_OST_INT_RAW_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_RAW_V  0x1
+#define MCPWM_FH0_OST_INT_RAW_S  24
+/* MCPWM_FH2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_RAW  (BIT(23))
+#define MCPWM_FH2_CBC_INT_RAW_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_RAW_V  0x1
+#define MCPWM_FH2_CBC_INT_RAW_S  23
+/* MCPWM_FH1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_RAW  (BIT(22))
+#define MCPWM_FH1_CBC_INT_RAW_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_RAW_V  0x1
+#define MCPWM_FH1_CBC_INT_RAW_S  22
+/* MCPWM_FH0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_RAW  (BIT(21))
+#define MCPWM_FH0_CBC_INT_RAW_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_RAW_V  0x1
+#define MCPWM_FH0_CBC_INT_RAW_S  21
+/* MCPWM_OP2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_RAW  (BIT(20))
+#define MCPWM_OP2_TEB_INT_RAW_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_RAW_V  0x1
+#define MCPWM_OP2_TEB_INT_RAW_S  20
+/* MCPWM_OP1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_RAW  (BIT(19))
+#define MCPWM_OP1_TEB_INT_RAW_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_RAW_V  0x1
+#define MCPWM_OP1_TEB_INT_RAW_S  19
+/* MCPWM_OP0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_RAW  (BIT(18))
+#define MCPWM_OP0_TEB_INT_RAW_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_RAW_V  0x1
+#define MCPWM_OP0_TEB_INT_RAW_S  18
+/* MCPWM_OP2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_RAW  (BIT(17))
+#define MCPWM_OP2_TEA_INT_RAW_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_RAW_V  0x1
+#define MCPWM_OP2_TEA_INT_RAW_S  17
+/* MCPWM_OP1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_RAW  (BIT(16))
+#define MCPWM_OP1_TEA_INT_RAW_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_RAW_V  0x1
+#define MCPWM_OP1_TEA_INT_RAW_S  16
+/* MCPWM_OP0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_RAW  (BIT(15))
+#define MCPWM_OP0_TEA_INT_RAW_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_RAW_V  0x1
+#define MCPWM_OP0_TEA_INT_RAW_S  15
+/* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_RAW  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_V  0x1
+#define MCPWM_FAULT2_CLR_INT_RAW_S  14
+/* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_RAW  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_V  0x1
+#define MCPWM_FAULT1_CLR_INT_RAW_S  13
+/* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_RAW  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_V  0x1
+#define MCPWM_FAULT0_CLR_INT_RAW_S  12
+/* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_RAW  (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_M  (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_V  0x1
+#define MCPWM_FAULT2_INT_RAW_S  11
+/* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_RAW  (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_M  (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_V  0x1
+#define MCPWM_FAULT1_INT_RAW_S  10
+/* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_RAW  (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_M  (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_V  0x1
+#define MCPWM_FAULT0_INT_RAW_S  9
+/* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_RAW  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_V  0x1
+#define MCPWM_TIMER2_TEP_INT_RAW_S  8
+/* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_RAW  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_V  0x1
+#define MCPWM_TIMER1_TEP_INT_RAW_S  7
+/* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_RAW  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_V  0x1
+#define MCPWM_TIMER0_TEP_INT_RAW_S  6
+/* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_RAW  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
+/* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_RAW  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
+/* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_RAW  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
+/* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_RAW  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_V  0x1
+#define MCPWM_TIMER2_STOP_INT_RAW_S  2
+/* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_RAW  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_V  0x1
+#define MCPWM_TIMER1_STOP_INT_RAW_S  1
+/* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_RAW  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_V  0x1
+#define MCPWM_TIMER0_STOP_INT_RAW_S  0
+
+#define MCMCPWM_INT_ST_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0118)
+/* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_ST  (BIT(29))
+#define MCPWM_CAP2_INT_ST_M  (BIT(29))
+#define MCPWM_CAP2_INT_ST_V  0x1
+#define MCPWM_CAP2_INT_ST_S  29
+/* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_ST  (BIT(28))
+#define MCPWM_CAP1_INT_ST_M  (BIT(28))
+#define MCPWM_CAP1_INT_ST_V  0x1
+#define MCPWM_CAP1_INT_ST_S  28
+/* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_ST  (BIT(27))
+#define MCPWM_CAP0_INT_ST_M  (BIT(27))
+#define MCPWM_CAP0_INT_ST_V  0x1
+#define MCPWM_CAP0_INT_ST_S  27
+/* MCPWM_FH2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_ST  (BIT(26))
+#define MCPWM_FH2_OST_INT_ST_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_ST_V  0x1
+#define MCPWM_FH2_OST_INT_ST_S  26
+/* MCPWM_FH1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_ST  (BIT(25))
+#define MCPWM_FH1_OST_INT_ST_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_ST_V  0x1
+#define MCPWM_FH1_OST_INT_ST_S  25
+/* MCPWM_FH0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_ST  (BIT(24))
+#define MCPWM_FH0_OST_INT_ST_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_ST_V  0x1
+#define MCPWM_FH0_OST_INT_ST_S  24
+/* MCPWM_FH2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_ST  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ST_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ST_V  0x1
+#define MCPWM_FH2_CBC_INT_ST_S  23
+/* MCPWM_FH1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_ST  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ST_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ST_V  0x1
+#define MCPWM_FH1_CBC_INT_ST_S  22
+/* MCPWM_FH0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_ST  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ST_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ST_V  0x1
+#define MCPWM_FH0_CBC_INT_ST_S  21
+/* MCPWM_OP2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_ST  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ST_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ST_V  0x1
+#define MCPWM_OP2_TEB_INT_ST_S  20
+/* MCPWM_OP1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_ST  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ST_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ST_V  0x1
+#define MCPWM_OP1_TEB_INT_ST_S  19
+/* MCPWM_OP0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_ST  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ST_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ST_V  0x1
+#define MCPWM_OP0_TEB_INT_ST_S  18
+/* MCPWM_OP2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_ST  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ST_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ST_V  0x1
+#define MCPWM_OP2_TEA_INT_ST_S  17
+/* MCPWM_OP1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_ST  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ST_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ST_V  0x1
+#define MCPWM_OP1_TEA_INT_ST_S  16
+/* MCPWM_OP0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_ST  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ST_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ST_V  0x1
+#define MCPWM_OP0_TEA_INT_ST_S  15
+/* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_ST  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_V  0x1
+#define MCPWM_FAULT2_CLR_INT_ST_S  14
+/* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_ST  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_V  0x1
+#define MCPWM_FAULT1_CLR_INT_ST_S  13
+/* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_ST  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_V  0x1
+#define MCPWM_FAULT0_CLR_INT_ST_S  12
+/* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_ST  (BIT(11))
+#define MCPWM_FAULT2_INT_ST_M  (BIT(11))
+#define MCPWM_FAULT2_INT_ST_V  0x1
+#define MCPWM_FAULT2_INT_ST_S  11
+/* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_ST  (BIT(10))
+#define MCPWM_FAULT1_INT_ST_M  (BIT(10))
+#define MCPWM_FAULT1_INT_ST_V  0x1
+#define MCPWM_FAULT1_INT_ST_S  10
+/* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_ST  (BIT(9))
+#define MCPWM_FAULT0_INT_ST_M  (BIT(9))
+#define MCPWM_FAULT0_INT_ST_V  0x1
+#define MCPWM_FAULT0_INT_ST_S  9
+/* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_ST  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_V  0x1
+#define MCPWM_TIMER2_TEP_INT_ST_S  8
+/* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_ST  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_V  0x1
+#define MCPWM_TIMER1_TEP_INT_ST_S  7
+/* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_ST  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_V  0x1
+#define MCPWM_TIMER0_TEP_INT_ST_S  6
+/* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_ST  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_ST_S  5
+/* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_ST  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_ST_S  4
+/* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_ST  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_ST_S  3
+/* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_ST  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_V  0x1
+#define MCPWM_TIMER2_STOP_INT_ST_S  2
+/* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_ST  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_V  0x1
+#define MCPWM_TIMER1_STOP_INT_ST_S  1
+/* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_ST  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_V  0x1
+#define MCPWM_TIMER0_STOP_INT_ST_S  0
+
+#define MCMCPWM_INT_CLR_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x011c)
+/* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_CLR  (BIT(29))
+#define MCPWM_CAP2_INT_CLR_M  (BIT(29))
+#define MCPWM_CAP2_INT_CLR_V  0x1
+#define MCPWM_CAP2_INT_CLR_S  29
+/* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_CLR  (BIT(28))
+#define MCPWM_CAP1_INT_CLR_M  (BIT(28))
+#define MCPWM_CAP1_INT_CLR_V  0x1
+#define MCPWM_CAP1_INT_CLR_S  28
+/* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_CLR  (BIT(27))
+#define MCPWM_CAP0_INT_CLR_M  (BIT(27))
+#define MCPWM_CAP0_INT_CLR_V  0x1
+#define MCPWM_CAP0_INT_CLR_S  27
+/* MCPWM_FH2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_CLR  (BIT(26))
+#define MCPWM_FH2_OST_INT_CLR_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_CLR_V  0x1
+#define MCPWM_FH2_OST_INT_CLR_S  26
+/* MCPWM_FH1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_CLR  (BIT(25))
+#define MCPWM_FH1_OST_INT_CLR_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_CLR_V  0x1
+#define MCPWM_FH1_OST_INT_CLR_S  25
+/* MCPWM_FH0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_CLR  (BIT(24))
+#define MCPWM_FH0_OST_INT_CLR_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_CLR_V  0x1
+#define MCPWM_FH0_OST_INT_CLR_S  24
+/* MCPWM_FH2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
+ mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_CLR  (BIT(23))
+#define MCPWM_FH2_CBC_INT_CLR_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_CLR_V  0x1
+#define MCPWM_FH2_CBC_INT_CLR_S  23
+/* MCPWM_FH1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
+ mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_CLR  (BIT(22))
+#define MCPWM_FH1_CBC_INT_CLR_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_CLR_V  0x1
+#define MCPWM_FH1_CBC_INT_CLR_S  22
+/* MCPWM_FH0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
+ mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_CLR  (BIT(21))
+#define MCPWM_FH0_CBC_INT_CLR_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_CLR_V  0x1
+#define MCPWM_FH0_CBC_INT_CLR_S  21
+/* MCPWM_OP2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_CLR  (BIT(20))
+#define MCPWM_OP2_TEB_INT_CLR_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_CLR_V  0x1
+#define MCPWM_OP2_TEB_INT_CLR_S  20
+/* MCPWM_OP1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_CLR  (BIT(19))
+#define MCPWM_OP1_TEB_INT_CLR_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_CLR_V  0x1
+#define MCPWM_OP1_TEB_INT_CLR_S  19
+/* MCPWM_OP0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_CLR  (BIT(18))
+#define MCPWM_OP0_TEB_INT_CLR_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_CLR_V  0x1
+#define MCPWM_OP0_TEB_INT_CLR_S  18
+/* MCPWM_OP2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_CLR  (BIT(17))
+#define MCPWM_OP2_TEA_INT_CLR_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_CLR_V  0x1
+#define MCPWM_OP2_TEA_INT_CLR_S  17
+/* MCPWM_OP1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_CLR  (BIT(16))
+#define MCPWM_OP1_TEA_INT_CLR_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_CLR_V  0x1
+#define MCPWM_OP1_TEA_INT_CLR_S  16
+/* MCPWM_OP0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_CLR  (BIT(15))
+#define MCPWM_OP0_TEA_INT_CLR_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_CLR_V  0x1
+#define MCPWM_OP0_TEA_INT_CLR_S  15
+/* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_CLR  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_V  0x1
+#define MCPWM_FAULT2_CLR_INT_CLR_S  14
+/* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_CLR  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_V  0x1
+#define MCPWM_FAULT1_CLR_INT_CLR_S  13
+/* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_CLR  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_V  0x1
+#define MCPWM_FAULT0_CLR_INT_CLR_S  12
+/* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_CLR  (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_M  (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_V  0x1
+#define MCPWM_FAULT2_INT_CLR_S  11
+/* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_CLR  (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_M  (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_V  0x1
+#define MCPWM_FAULT1_INT_CLR_S  10
+/* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_CLR  (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_M  (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_V  0x1
+#define MCPWM_FAULT0_INT_CLR_S  9
+/* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_CLR  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_V  0x1
+#define MCPWM_TIMER2_TEP_INT_CLR_S  8
+/* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_CLR  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_V  0x1
+#define MCPWM_TIMER1_TEP_INT_CLR_S  7
+/* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_CLR  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_V  0x1
+#define MCPWM_TIMER0_TEP_INT_CLR_S  6
+/* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_CLR  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
+/* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_CLR  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
+/* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_CLR  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
+/* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_CLR  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_V  0x1
+#define MCPWM_TIMER2_STOP_INT_CLR_S  2
+/* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_CLR  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_V  0x1
+#define MCPWM_TIMER1_STOP_INT_CLR_S  1
+/* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_CLR  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_V  0x1
+#define MCPWM_TIMER0_STOP_INT_CLR_S  0
+
+#define MCPWM_CLK_REG(i)          (REG_MCPWM_BASE(i) + 0x0120)
+/* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Force clock on for this reg file*/
+#define MCPWM_CLK_EN  (BIT(0))
+#define MCPWM_CLK_EN_M  (BIT(0))
+#define MCPWM_CLK_EN_V  0x1
+#define MCPWM_CLK_EN_S  0
+
+#define MCPWM_VERSION_REG(i)          (REG_MCPWM_BASE(i) + 0x0124)
+/* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */
+/*description: Version of this reg file*/
+#define MCPWM_DATE  0x0FFFFFFF
+#define MCPWM_DATE_M  ((MCPWM_DATE_V)<<(MCPWM_DATE_S))
+#define MCPWM_DATE_V  0xFFFFFFF
+#define MCPWM_DATE_S  0
+
+
+
+
+#endif /*_SOC_MCPWM_REG_H_ */
+
+
diff --git a/components/soc/esp32/include/soc/mcpwm_struct.h b/components/soc/esp32/include/soc/mcpwm_struct.h
new file mode 100644
index 000000000..4d49e504d
--- /dev/null
+++ b/components/soc/esp32/include/soc/mcpwm_struct.h
@@ -0,0 +1,452 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_MCPWM_STRUCT_H__
+#define _SOC_MCPWM_STRUCT_H__
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t prescale: 8;                  /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
+            uint32_t reserved8:   24;
+        };
+        uint32_t val;
+    }clk_cfg;
+    struct {
+        union {
+            struct {
+                uint32_t prescale:        8;        /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
+                uint32_t period:         16;        /*period shadow reg of PWM timer0*/
+                uint32_t upmethod: 2;        /*Update method for active reg of PWM timer0 period  0: immediate  1: TEZ  2: sync  3: TEZ | sync. TEZ here and below means timer equal zero event*/
+                uint32_t reserved26:      6;
+            };
+            uint32_t val;
+        }period;
+        union {
+            struct {
+                uint32_t start: 3;                  /*PWM timer0 start and stop control. 0: stop @ TEZ  1: stop @ TEP  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP. TEP here and below means timer equal period event*/
+                uint32_t mode:   2;                  /*PWM timer0 working mode  0: freeze  1: increase mod  2: decrease mod  3: up-down mod*/
+                uint32_t reserved5:   27;
+            };
+            uint32_t val;
+        }mode;
+        union {
+            struct {
+                uint32_t in_en:     1;              /*when set   timer reload with phase on sync input event is enabled*/
+                uint32_t sync_sw:   1;              /*write the negate value will trigger a software sync*/
+                uint32_t out_sel: 2;              /*PWM timer0 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+                uint32_t timer_phase:    17;              /*phase for timer reload on sync event*/
+                uint32_t reserved21:      11;
+            };
+            uint32_t val;
+        }sync;
+        union {
+            struct {
+                uint32_t value:    16;              /*current PWM timer0 counter value*/
+                uint32_t direction: 1;              /*current PWM timer0 counter direction  0: increment 1: decrement*/
+                uint32_t reserved17:      15;
+            };
+            uint32_t val;
+        }status;
+    }timer[3];
+
+
+    union {
+        struct {
+            uint32_t t0_in_sel:   3;        /*select sync input for PWM timer0  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
+            uint32_t t1_in_sel:   3;        /*select sync input for PWM timer1  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
+            uint32_t t2_in_sel:   3;        /*select sync input for PWM timer2  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
+            uint32_t ext_in0_inv: 1;        /*invert SYNC0 from GPIO matrix*/
+            uint32_t ext_in1_inv: 1;        /*invert SYNC1 from GPIO matrix*/
+            uint32_t ext_in2_inv: 1;        /*invert SYNC2 from GPIO matrix*/
+            uint32_t reserved12:            20;
+        };
+        uint32_t val;
+    }timer_synci_cfg;
+    union {
+        struct {
+            uint32_t operator0_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator0  0: timer0  1: timer1  2: timer2*/
+            uint32_t operator1_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator1  0: timer0  1: timer1  2: timer2*/
+            uint32_t operator2_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator2  0: timer0  1: timer1  2: timer2*/
+            uint32_t reserved6:         26;
+        };
+        uint32_t val;
+    }timer_sel;
+
+
+    struct {
+        union {
+            struct {
+                uint32_t a_upmethod:  4;             /*Update method for PWM compare0 A's active reg. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: freeze*/
+                uint32_t b_upmethod:  4;             /*Update method for PWM compare0 B's active reg. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: freeze*/
+                uint32_t a_shdw_full: 1;             /*Set and reset by hardware. If set  PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+                uint32_t b_shdw_full: 1;             /*Set and reset by hardware. If set  PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+                uint32_t reserved10:       22;
+            };
+            uint32_t val;
+        }cmpr_cfg;
+        union {
+            struct {
+                uint32_t cmpr_val:       16;                    /*PWM compare0 A's shadow reg*/
+                uint32_t reserved16:16;
+            };
+            uint32_t val;
+        }cmpr_value[2];
+        union {
+            struct {
+                uint32_t upmethod: 4;             /*Update method for PWM generate0's active reg of configuration. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: freeze*/
+                uint32_t t0_sel:       3;             /*Source selection for PWM generate0 event_t0  take effect immediately  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+                uint32_t t1_sel:       3;             /*Source selection for PWM generate0 event_t1  take effect immediately  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+                uint32_t reserved10:       22;
+            };
+            uint32_t val;
+        }gen_cfg0;
+        union {
+            struct {
+                uint32_t cntu_force_upmethod: 6;       /*Update method for continuous software force of PWM generate0. 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: freeze. (TEA/B here and below means timer equals A/B event)*/
+                uint32_t a_cntuforce_mode:   2;       /*Continuous software force mode for PWM0A. 0: disabled  1: low  2: high  3: disabled*/
+                uint32_t b_cntuforce_mode:   2;       /*Continuous software force mode for PWM0B. 0: disabled  1: low  2: high  3: disabled*/
+                uint32_t a_nciforce:         1;       /*non-continuous immediate software force trigger for PWM0A  a toggle will trigger a force event*/
+                uint32_t a_nciforce_mode:    2;       /*non-continuous immediate software force mode for PWM0A  0: disabled  1: low  2: high  3: disabled*/
+                uint32_t b_nciforce:         1;       /*non-continuous immediate software force trigger for PWM0B  a toggle will trigger a force event*/
+                uint32_t b_nciforce_mode:    2;       /*non-continuous immediate software force mode for PWM0B  0: disabled  1: low  2: high  3: disabled*/
+                uint32_t reserved16:             16;
+            };
+            uint32_t val;
+        }gen_force;
+        union {
+            struct {
+                uint32_t utez: 2;                   /*Action on PWM0A triggered by event TEZ when timer increasing*/
+                uint32_t utep: 2;                   /*Action on PWM0A triggered by event TEP when timer increasing*/
+                uint32_t utea: 2;                   /*Action on PWM0A triggered by event TEA when timer increasing*/
+                uint32_t uteb: 2;                   /*Action on PWM0A triggered by event TEB when timer increasing*/
+                uint32_t ut0:  2;                   /*Action on PWM0A triggered by event_t0 when timer increasing*/
+                uint32_t ut1:  2;                   /*Action on PWM0A triggered by event_t1 when timer increasing*/
+                uint32_t dtez: 2;                   /*Action on PWM0A triggered by event TEZ when timer decreasing*/
+                uint32_t dtep: 2;                   /*Action on PWM0A triggered by event TEP when timer decreasing*/
+                uint32_t dtea: 2;                   /*Action on PWM0A triggered by event TEA when timer decreasing*/
+                uint32_t dteb: 2;                   /*Action on PWM0A triggered by event TEB when timer decreasing*/
+                uint32_t dt0:  2;                   /*Action on PWM0A triggered by event_t0 when timer decreasing*/
+                uint32_t dt1:  2;                   /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change  1: low  2: high  3: toggle*/
+                uint32_t reserved24:  8;
+            };
+            uint32_t val;
+        }generator[2];
+        union {
+            struct {
+                uint32_t fed_upmethod:  4;             /*Update method for FED (falling edge delay) active reg. 0: immediate  bit0: tez  bit1: tep  bit2: sync  bit3: freeze*/
+                uint32_t red_upmethod:  4;             /*Update method for RED (rising edge delay) active reg. 0: immediate  bit0: tez  bit1: tep  bit2: sync  bit3: freeze*/
+                uint32_t deb_mode:      1;             /*S8 in documentation  dual-edge B mode  0: fed/red take effect on different path separately  1: fed/red take effect on B path  A out is in bypass or dulpB mode*/
+                uint32_t a_outswap:     1;             /*S6 in documentation*/
+                uint32_t b_outswap:     1;             /*S7 in documentation*/
+                uint32_t red_insel:     1;             /*S4 in documentation*/
+                uint32_t fed_insel:     1;             /*S5 in documentation*/
+                uint32_t red_outinvert: 1;             /*S2 in documentation*/
+                uint32_t fed_outinvert: 1;             /*S3 in documentation*/
+                uint32_t a_outbypass:   1;             /*S1 in documentation*/
+                uint32_t b_outbypass:   1;             /*S0 in documentation*/
+                uint32_t clk_sel:       1;             /*Dead band0 clock selection. 0: PWM_clk  1: PT_clk*/
+                uint32_t reserved18:   14;
+            };
+            uint32_t val;
+        }db_cfg;
+        union {
+            struct {
+                uint32_t fed:   16;                    /*Shadow reg for FED*/
+                uint32_t reserved16:16;
+            };
+            uint32_t val;
+        }db_fed_cfg;
+        union {
+            struct {
+                uint32_t red:   16;                    /*Shadow reg for RED*/
+                uint32_t reserved16:16;
+            };
+            uint32_t val;
+        }db_red_cfg;
+        union {
+            struct {
+                uint32_t en:         1;           /*When set  carrier0 function is enabled. When reset  carrier0 is bypassed*/
+                uint32_t prescale:   4;           /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
+                uint32_t duty:       3;           /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
+                uint32_t oshtwth:    4;           /*width of the fist pulse in number of periods of the carrier*/
+                uint32_t out_invert: 1;           /*when set  invert the output of PWM0A and PWM0B for this submodule*/
+                uint32_t in_invert:  1;           /*when set  invert the input of PWM0A and PWM0B for this submodule*/
+                uint32_t reserved14:         18;
+            };
+            uint32_t val;
+        }carrier_cfg;
+        union {
+            struct {
+                uint32_t sw_cbc:  1;                   /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t f2_cbc:  1;                   /*event_f2 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t f1_cbc:  1;                   /*event_f1 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t f0_cbc:  1;                   /*event_f0 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t sw_ost:  1;                   /*one-shot tripping software force event will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t f2_ost:  1;                   /*event_f2 will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t f1_ost:  1;                   /*event_f1 will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t f0_ost:  1;                   /*event_f0 will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t a_cbc_d: 2;                   /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t a_cbc_u: 2;                   /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t a_ost_d: 2;                   /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t a_ost_u: 2;                   /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_cbc_d: 2;                   /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_cbc_u: 2;                   /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_ost_d: 2;                   /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_ost_u: 2;                   /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t reserved24:  8;
+            };
+            uint32_t val;
+        }tz_cfg0;
+        union {
+            struct {
+                uint32_t clr_ost:   1;                 /*a toggle will clear on going one-shot tripping*/
+                uint32_t cbcpulse:  2;                 /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ  bit1:TEP*/
+                uint32_t force_cbc: 1;                 /*a toggle trigger a cycle-by-cycle tripping software force event*/
+                uint32_t force_ost: 1;                 /*a toggle (software negate its value) trigger a one-shot tripping software force event*/
+                uint32_t reserved5:    27;
+            };
+            uint32_t val;
+        }tz_cfg1;
+        union {
+            struct {
+                uint32_t cbc_on: 1;                    /*Set and reset by hardware. If set  an cycle-by-cycle trip event is on going*/
+                uint32_t ost_on: 1;                    /*Set and reset by hardware. If set  an one-shot trip event is on going*/
+                uint32_t reserved2: 30;
+            };
+            uint32_t val;
+        }tz_status;
+    }channel[3];
+
+    union {
+        struct {
+            uint32_t f0_en:      1;                    /*When set  event_f0 generation is enabled*/
+            uint32_t f1_en:      1;                    /*When set  event_f1 generation is enabled*/
+            uint32_t f2_en:      1;                    /*When set  event_f2 generation is enabled*/
+            uint32_t f0_pole:    1;                    /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
+            uint32_t f1_pole:    1;                    /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
+            uint32_t f2_pole:    1;                    /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
+            uint32_t event_f0:   1;                    /*Set and reset by hardware. If set  event_f0 is on going*/
+            uint32_t event_f1:   1;                    /*Set and reset by hardware. If set  event_f1 is on going*/
+            uint32_t event_f2:   1;                    /*Set and reset by hardware. If set  event_f2 is on going*/
+            uint32_t reserved9: 23;
+        };
+        uint32_t val;
+    }fault_detect;
+    union {
+        struct {
+            uint32_t timer_en:  1;                 /*When set  capture timer incrementing under APB_clk is enabled.*/
+            uint32_t synci_en:  1;                 /*When set  capture timer sync is enabled.*/
+            uint32_t synci_sel: 3;                 /*capture module sync input selection. 0: none  1: timer0 synco  2: timer1 synco  3: timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix*/
+            uint32_t sync_sw:   1;                 /*Write 1 will force a capture timer sync  capture timer is loaded with value in phase register.*/
+            uint32_t reserved6:    26;
+        };
+        uint32_t val;
+    }cap_timer_cfg;
+    uint32_t cap_timer_phase;                      /*Phase value for capture timer sync operation.*/
+    union {
+        struct {
+            uint32_t en:        1;                /*When set  capture on channel 0 is enabled*/
+            uint32_t mode:      2;                /*Edge of capture on channel 0 after prescale.  bit0: negedge cap en  bit1: posedge cap en*/
+            uint32_t prescale:  8;                /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/
+            uint32_t in_invert: 1;                /*when set  CAP0 form GPIO matrix is inverted before prescale*/
+            uint32_t sw:        1;                /*Write 1 will trigger a software forced capture on channel 0*/
+            uint32_t reserved13:    19;
+        };
+        uint32_t val;
+    }cap_cfg_ch[3];
+    uint32_t cap_val_ch[3];                              /*Value of last capture on channel 0*/
+    union {
+        struct {
+            uint32_t cap0_edge:  1;                    /*Edge of last capture trigger on channel 0  0: posedge  1: negedge*/
+            uint32_t cap1_edge:  1;                    /*Edge of last capture trigger on channel 1  0: posedge  1: negedge*/
+            uint32_t cap2_edge:  1;                    /*Edge of last capture trigger on channel 2  0: posedge  1: negedge*/
+            uint32_t reserved3: 29;
+        };
+        uint32_t val;
+    }cap_status;
+    union {
+        struct {
+            uint32_t global_up_en:    1;               /*The global enable of update of all active registers in MCPWM module*/
+            uint32_t global_force_up: 1;               /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/
+            uint32_t op0_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 0 are enabled*/
+            uint32_t op0_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/
+            uint32_t op1_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 1 are enabled*/
+            uint32_t op1_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/
+            uint32_t op2_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 2 are enabled*/
+            uint32_t op2_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/
+            uint32_t reserved8:      24;
+        };
+        uint32_t val;
+    }update_cfg;
+    union {
+        struct {
+            uint32_t timer0_stop_int_ena: 1;           /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_ena: 1;           /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_ena: 1;           /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_ena:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_ena:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_ena:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_ena:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_ena:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_ena:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_ena:      1;           /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_ena:      1;           /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_ena:      1;           /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_ena:  1;           /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_ena:  1;           /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_ena:  1;           /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_ena:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_ena:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_ena:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_ena:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_ena:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_ena:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_ena:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_ena:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_ena:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_ena:        1;           /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_ena:        1;           /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_ena:        1;           /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    }int_ena;
+    union {
+        struct {
+            uint32_t timer0_stop_int_raw: 1;           /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_raw: 1;           /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_raw: 1;           /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_raw:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_raw:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_raw:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_raw:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_raw:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_raw:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_raw:      1;           /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_raw:      1;           /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_raw:      1;           /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_raw:  1;           /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_raw:  1;           /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_raw:  1;           /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_raw:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_raw:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_raw:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_raw:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_raw:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_raw:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_raw:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_raw:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_raw:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_raw:        1;           /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_raw:        1;           /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_raw:        1;           /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    }int_raw;
+    union {
+        struct {
+            uint32_t timer0_stop_int_st: 1;            /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_st: 1;            /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_st: 1;            /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_st:  1;            /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_st:  1;            /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_st:  1;            /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_st:  1;            /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_st:  1;            /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_st:  1;            /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_st:      1;            /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_st:      1;            /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_st:      1;            /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_st:  1;            /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_st:  1;            /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_st:  1;            /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_st:   1;            /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_st:   1;            /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_st:   1;            /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_st:   1;            /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_st:   1;            /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_st:   1;            /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_st:     1;            /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_st:     1;            /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_st:     1;            /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_st:        1;            /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_st:        1;            /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_st:        1;            /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:         2;
+        };
+        uint32_t val;
+    }int_st;
+    union {
+        struct {
+            uint32_t timer0_stop_int_clr: 1;           /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_clr: 1;           /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_clr: 1;           /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_clr:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_clr:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_clr:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_clr:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_clr:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_clr:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_clr:      1;           /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_clr:      1;           /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_clr:      1;           /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_clr:  1;           /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_clr:  1;           /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_clr:  1;           /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_clr:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_clr:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_clr:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_clr:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_clr:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_clr:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_clr:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_clr:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_clr:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_clr:        1;           /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_clr:        1;           /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_clr:        1;           /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    }int_clr;
+    union {
+        struct {
+            uint32_t clk_en:     1;                    /*Force clock on for this reg file*/
+            uint32_t reserved1: 31;
+        };
+        uint32_t val;
+    }reg_clk;
+    union {
+        struct {
+            uint32_t date:      28;                    /*Version of this reg file*/
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    }version;
+} mcpwm_dev_t;
+extern mcpwm_dev_t MCPWM0;
+extern mcpwm_dev_t MCPWM1;
+#endif  /* _SOC_MCPWM_STRUCT_H__ */
diff --git a/docs/api/peripherals/mcpwm.rst b/docs/api/peripherals/mcpwm.rst
new file mode 100644
index 000000000..a6533e6a8
--- /dev/null
+++ b/docs/api/peripherals/mcpwm.rst
@@ -0,0 +1,133 @@
+MCPWM
+=====
+
+Overview
+--------
+
+ESP32 has two MCPWM units which can be used to control different motors.
+
+Block Diagram
+-------------
+
+The block diagram of MCPWM unit is as shown.
+
+::
+
+                __________________________________________________________________________
+                |     SYNCSIG              FAULT SIG		CAPTURE SIG               |
+                |    0   1   2	           0   1   2        0   1   2                     |
+                |___________________________________________________________________   G  |
+  INTERRUPTS<-----+ |   |   |             |   |   |         |   |   |               |  P  |
+                  | |   |   |             |   |   |         |   |   |               |  I  |
+          ________|_|___|___|_____________|___|___|_________|___|___|_________      |  O  |
+          |         |   |   |             |   |   |         |   |   |         |     |     |
+          |         |   |   |             |   |   |         |   |   |         |     |  M  |
+          |         |   |   |           __v___v___v__     __v___v___v__       |     |  A  |
+          |         |   |   |           |           |     |           |       |     |  T  |
+          |         |   |   |           |   FAULT   |     |  CAPTURE  |       |	    |  R  |
+          |         |   |   |           |  HANDLER  |     |           |       |     |  I  |
+          |         |   |   |           |           |     |___________|       |     |  X  |
+          |         |   |   |           |___________|                         |     |     |
+          |         |   |   |                                                 |     |     |
+          |	 ____v___v___v____                    ____________________    |     |     |
+          |	 |  +---------+  |                    |  +------------+  |--------->|PWM0A|
+          |	 |  | Timer 0 |  |                    |  | Operator 0 |  |    |     |     |
+          |	 |  +---------+  |                    |  +------------+  |--------->|PWM0B|
+          |	 |               |                    |                  |    |     |     |
+          |	 |  +---------+  |	      	      |  +------------+  |--------->|PWM1A|
+          |	 |  | Timer 1 |  |------------------->|  | Operator 1 |  |    |     |     |
+          |	 |  +---------+  |                    |  +------------+  |--------->|PWM1B|
+          |	 |               |                    |                  |    |     |     |
+          |	 |  +---------+  |                    |  +------------+  |--------->|PWM2A|
+          |	 |  | Timer 2 |  |                    |  | Operator 2 |  |    |     |     |
+          |	 |  +---------+  |                    |  +------------+  |--------->|PWM2B|
+          |	 |_______________|                    |__________________|    |     |_____|
+          |                                                                   |
+          | MCPWM-UNIT 0/1                                                    |
+          |___________________________________________________________________|
+
+			  
+Application Example
+-------------------
+
+MCPWM different motor example: :example:`peripherals/mcpwm`.
+
+API Reference
+-------------
+
+Header Files
+^^^^^^^^^^^^
+
+  * :component_file:`driver/include/driver/mcpwm.h`
+    
+Type Definitions
+^^^^^^^^^^^^^^^^
+
+
+Enumerations
+^^^^^^^^^^^^
+
+.. doxygenenum:: mcpwm_io_signals_t
+.. doxygenenum:: mcpwm_unit_t
+.. doxygenenum:: mcpwm_timer_t
+.. doxygenenum:: mcpwm_operator_t
+.. doxygenenum:: mcpwm_counter_type_t
+.. doxygenenum:: mcpwm_duty_type_t
+.. doxygenenum:: mcpwm_carrier_os_t
+.. doxygenenum:: mcpwm_carrier_out_ivt_t
+.. doxygenenum:: mcpwm_sync_signal_t
+.. doxygenenum:: mcpwm_fault_signal_t
+.. doxygenenum:: mcpwm_fault_input_level_t
+.. doxygenenum:: mcpwm_action_on_pwmxa_t
+.. doxygenenum:: mcpwm_action_on_pwmxb_t
+.. doxygenenum:: mcpwm_capture_signal_t
+.. doxygenenum:: mcpwm_capture_on_edge_t
+.. doxygenenum:: mcpwm_deadtime_type_t
+
+Structures
+^^^^^^^^^^
+
+.. doxygenstruct:: mcpwm_config_t
+    :members:
+
+.. doxygenstruct:: mcpwm_carrier_config_t
+    :members:
+
+
+Functions
+^^^^^^^^^
+
+.. doxygenfunction:: mcpwm_gpio_init
+.. doxygenfunction:: mcpwm_init
+.. doxygenfunction:: mcpwm_set_frequency
+.. doxygenfunction:: mcpwm_set_duty
+.. doxygenfunction:: mcpwm_set_duty_in_us
+.. doxygenfunction:: mcpwm_set_duty_type
+.. doxygenfunction:: mcpwm_get_frequency
+.. doxygenfunction:: mcpwm_get_duty
+.. doxygenfunction:: mcpwm_set_signal_high
+.. doxygenfunction:: mcpwm_set_signal_low
+.. doxygenfunction:: mcpwm_start
+.. doxygenfunction:: mcpwm_stop
+.. doxygenfunction:: mcpwm_carrier_init
+.. doxygenfunction:: mcpwm_carrier_enable
+.. doxygenfunction:: mcpwm_carrier_disable
+.. doxygenfunction:: mcpwm_carrier_set_period
+.. doxygenfunction:: mcpwm_carrier_set_duty_cycle
+.. doxygenfunction:: mcpwm_carrier_oneshot_mode_enable
+.. doxygenfunction:: mcpwm_carrier_oneshot_mode_disable
+.. doxygenfunction:: mcpwm_carrier_output_invert
+.. doxygenfunction:: mcpwm_deadtime_enable
+.. doxygenfunction:: mcpwm_deadtime_disable
+.. doxygenfunction:: mcpwm_fault_init
+.. doxygenfunction:: mcpwm_fault_set_oneshot_mode
+.. doxygenfunction:: mcpwm_fault_set_cyc_mode
+.. doxygenfunction:: mcpwm_fault_deinit
+.. doxygenfunction:: mcpwm_capture_enable
+.. doxygenfunction:: mcpwm_capture_disable
+.. doxygenfunction:: mcpwm_capture_signal_get_value
+.. doxygenfunction:: mcpwm_capture_signal_get_edge
+.. doxygenfunction:: mcpwm_sync_enable
+.. doxygenfunction:: mcpwm_sync_disable
+.. doxygenfunction:: mcpwm_isr_register
+
diff --git a/examples/peripherals/mcpwm/mcpwm_basic_config/Makefile b/examples/peripherals/mcpwm/mcpwm_basic_config/Makefile
new file mode 100644
index 000000000..55d30f942
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_basic_config/Makefile
@@ -0,0 +1,9 @@
+#
+# This is a project Makefile. It is assumed the directory this Makefile resides in is a
+# project subdirectory.
+#
+
+PROJECT_NAME := mcpwm_basic_config
+
+include $(IDF_PATH)/make/project.mk
+
diff --git a/examples/peripherals/mcpwm/mcpwm_basic_config/README.md b/examples/peripherals/mcpwm/mcpwm_basic_config/README.md
new file mode 100644
index 000000000..4b9e7a426
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_basic_config/README.md
@@ -0,0 +1,32 @@
+# MCPWM basic config Example
+
+This example will show you how to use each submodule of MCPWM unit
+ 
+The example can't be used without modifying the code first
+ 
+Edit the macros at the top of mcpwm_example_basic_config.c to enable/disable the submodules which are used in the example
+
+
+## Step 1: Pin assignment
+* The gpio init function initializes:
+    * six MCPWM output pins
+    * three MCPWM fault input pins
+    * three MCPWM sync input pins
+    * three MCPWM capture input pins 
+
+	
+## Step 2: Connection
+* Six MCPWM output pins to motor driver input signals
+* Fault, sync, capture signals can be connected to respective signals
+
+
+## Step 3: Initialize MCPWM 
+* You need to set the frequency and duty cycle of each three MCPWM timer along with other parameters mentioned
+* You need to set the MCPWM channel you want to use, with these timers
+
+
+## Step 4: Testing
+* The deadtime module, set deadtime type and with value as time*100ns
+* The sync module, synchonizes all the timer pulses
+* The fault module when enabled takes action on MCPWM signals when fault occurs
+* The capture module captures input signal(digital i.e. hall sensor value, etc), timing between two rising/falling edge
diff --git a/examples/peripherals/mcpwm/mcpwm_basic_config/main/component.mk b/examples/peripherals/mcpwm/mcpwm_basic_config/main/component.mk
new file mode 100644
index 000000000..44bd2b527
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_basic_config/main/component.mk
@@ -0,0 +1,3 @@
+#
+# Main Makefile. This is basically the same as a component makefile.
+#
diff --git a/examples/peripherals/mcpwm/mcpwm_basic_config/main/mcpwm_basic_config_example.c b/examples/peripherals/mcpwm/mcpwm_basic_config/main/mcpwm_basic_config_example.c
new file mode 100644
index 000000000..f4ace70c0
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_basic_config/main/mcpwm_basic_config_example.c
@@ -0,0 +1,290 @@
+/* MCPWM basic config example
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+
+/*
+ * This example will show you how to use each submodule of MCPWM unit.
+ * The example can't be used without modifying the code first.
+ * Edit the macros at the top of mcpwm_example_basic_config.c to enable/disable the submodules which are used in the example.
+ */
+
+#include <stdio.h>
+#include "string.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "esp_attr.h"
+#include "soc/rtc.h"
+#include "driver/mcpwm.h"
+#include "soc/mcpwm_reg.h"
+#include "soc/mcpwm_struct.h"
+
+#define MCPWM_EN_CARRIER 0   //Make this 1 to test carrier submodule of mcpwm, set high frequency carrier parameters
+#define MCPWM_EN_DEADTIME 0  //Make this 1 to test deadtime submodule of mcpwm, set deadtime value and deadtime mode
+#define MCPWM_EN_FAULT 0     //Make this 1 to test fault submodule of mcpwm, set action on MCPWM signal on fault occurence like overcurrent, overvoltage, etc
+#define MCPWM_EN_SYNC 0      //Make this 1 to test sync submodule of mcpwm, sync timer signals
+#define MCPWM_EN_CAPTURE 0   //Make this 1 to test capture submodule of mcpwm, measure time between rising/falling edge of captured signal
+#define MCPWM_GPIO_INIT 0    //select which function to use to initialize gpio signals
+#define CAP_SIG_NUM 3   //Three capture signals
+
+#define CAP0_INT_EN BIT(27)  //Capture 0 interrupt bit
+#define CAP1_INT_EN BIT(28)  //Capture 1 interrupt bit
+#define CAP2_INT_EN BIT(29)  //Capture 2 interrupt bit
+
+
+#define GPIO_PWM0A_OUT 19   //Set GPIO 19 as PWM0A
+#define GPIO_PWM0B_OUT 18   //Set GPIO 18 as PWM0B
+#define GPIO_PWM1A_OUT 17   //Set GPIO 17 as PWM1A
+#define GPIO_PWM1B_OUT 16   //Set GPIO 16 as PWM1B
+#define GPIO_PWM2A_OUT 15   //Set GPIO 15 as PWM2A
+#define GPIO_PWM2B_OUT 14   //Set GPIO 14 as PWM2B
+#define GPIO_CAP0_IN   23   //Set GPIO 23 as  CAP0
+#define GPIO_CAP1_IN   25   //Set GPIO 25 as  CAP1
+#define GPIO_CAP2_IN   26   //Set GPIO 26 as  CAP2
+#define GPIO_SYNC0_IN   2   //Set GPIO 02 as SYNC0
+#define GPIO_SYNC1_IN   4   //Set GPIO 04 as SYNC1
+#define GPIO_SYNC2_IN   5   //Set GPIO 05 as SYNC2
+#define GPIO_FAULT0_IN 32   //Set GPIO 32 as FAULT0
+#define GPIO_FAULT1_IN 34   //Set GPIO 34 as FAULT1
+#define GPIO_FAULT2_IN 34   //Set GPIO 34 as FAULT2
+
+typedef struct {
+    uint32_t capture_signal;
+    mcpwm_capture_signal_t sel_cap_signal;
+} capture;
+
+xQueueHandle cap_queue;
+static mcpwm_dev_t *MCPWM[2] = {&MCPWM0, &MCPWM1};
+
+static void mcpwm_example_gpio_initialize()
+{
+    printf("initializing mcpwm gpio...\n");
+#if MCPWM_GPIO_INIT
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM0A, GPIO_PWM0A_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM0B, GPIO_PWM0B_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM1A, GPIO_PWM1A_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM1B, GPIO_PWM1B_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM2A, GPIO_PWM2A_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM2B, GPIO_PWM2B_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_CAP_0, GPIO_CAP0_IN);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_CAP_1, GPIO_CAP1_IN);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_CAP_2, GPIO_CAP2_IN);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_SYNC_0, GPIO_SYNC0_IN);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_SYNC_1, GPIO_SYNC1_IN);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_SYNC_2, GPIO_SYNC2_IN);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_FAULT_0, GPIO_FAULT0_IN);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_FAULT_1, GPIO_FAULT1_IN);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_FAULT_2, GPIO_FAULT2_IN);
+#else
+    mcpwm_pin_config_t pin_config = {
+        .mcpwm0a_out_num = GPIO_PWM0A_OUT,
+        .mcpwm0b_out_num = GPIO_PWM0B_OUT,
+        .mcpwm1a_out_num = GPIO_PWM1A_OUT,
+        .mcpwm1b_out_num = GPIO_PWM1B_OUT,
+        .mcpwm2a_out_num = GPIO_PWM2A_OUT,
+        .mcpwm2b_out_num = GPIO_PWM2B_OUT,
+        .mcpwm_sync0_in_num  = GPIO_SYNC0_IN,
+        .mcpwm_sync1_in_num  = GPIO_SYNC1_IN,
+        .mcpwm_sync2_in_num  = GPIO_SYNC2_IN,
+        .mcpwm_fault0_in_num = GPIO_FAULT0_IN,
+        .mcpwm_fault1_in_num = GPIO_FAULT1_IN,
+        .mcpwm_fault2_in_num = GPIO_FAULT2_IN,
+        .mcpwm_cap0_in_num   = GPIO_CAP0_IN,
+        .mcpwm_cap1_in_num   = GPIO_CAP1_IN,
+        .mcpwm_cap2_in_num   = GPIO_CAP2_IN
+    };
+    mcpwm_set_pin(MCPWM_UNIT_0, &pin_config);
+#endif
+    gpio_pulldown_en(GPIO_CAP0_IN);    //Enable pull down on CAP0   signal
+    gpio_pulldown_en(GPIO_CAP1_IN);    //Enable pull down on CAP1   signal
+    gpio_pulldown_en(GPIO_CAP2_IN);    //Enable pull down on CAP2   signal
+    gpio_pulldown_en(GPIO_SYNC0_IN);   //Enable pull down on SYNC0  signal
+    gpio_pulldown_en(GPIO_SYNC1_IN);   //Enable pull down on SYNC1  signal
+    gpio_pulldown_en(GPIO_SYNC2_IN);   //Enable pull down on SYNC2  signal
+    gpio_pulldown_en(GPIO_FAULT0_IN);  //Enable pull down on FAULT0 signal
+    gpio_pulldown_en(GPIO_FAULT1_IN);  //Enable pull down on FAULT1 signal
+    gpio_pulldown_en(GPIO_FAULT2_IN);  //Enable pull down on FAULT2 signal
+}
+
+/**
+ * @brief Set gpio 12 as our test signal that generates high-low waveform continuously, connect this gpio to capture pin.
+ */
+static void gpio_test_signal(void *arg)
+{
+    printf("intializing test signal...\n");
+    gpio_config_t gp;
+    gp.intr_type = GPIO_INTR_DISABLE;
+    gp.mode = GPIO_MODE_OUTPUT;
+    gp.pin_bit_mask = GPIO_SEL_12;
+    gpio_config(&gp);
+    while (1) {
+        //here the period of test signal is 20ms
+        gpio_set_level(GPIO_NUM_12, 1); //Set high
+        vTaskDelay(10);             //delay of 10ms
+        gpio_set_level(GPIO_NUM_12, 0); //Set low
+        vTaskDelay(10);         //delay of 10ms
+    }
+}
+
+/**
+ * @brief When interrupt occurs, we receive the counter value and display the time between two rising edge
+ */
+static void disp_captured_signal(void *arg)
+{
+    uint32_t *current_cap_value = (uint32_t *)malloc(sizeof(CAP_SIG_NUM));
+    uint32_t *previous_cap_value = (uint32_t *)malloc(sizeof(CAP_SIG_NUM));
+    capture evt;
+    while (1) {
+        xQueueReceive(cap_queue, &evt, portMAX_DELAY);
+        if (evt.sel_cap_signal == MCPWM_SELECT_CAP0) {
+            current_cap_value[0] = evt.capture_signal - previous_cap_value[0];
+            previous_cap_value[0] = evt.capture_signal;
+            current_cap_value[0] = (current_cap_value[0] / 10000) * (10000000000 / rtc_clk_apb_freq_get());
+            printf("CAP0 : %d us\n", current_cap_value[0]);
+        }
+        if (evt.sel_cap_signal == MCPWM_SELECT_CAP1) {
+            current_cap_value[1] = evt.capture_signal - previous_cap_value[1];
+            previous_cap_value[1] = evt.capture_signal;
+            current_cap_value[1] = (current_cap_value[1] / 10000) * (10000000000 / rtc_clk_apb_freq_get());
+            printf("CAP1 : %d us\n", current_cap_value[1]);
+        }
+        if (evt.sel_cap_signal == MCPWM_SELECT_CAP2) {
+            current_cap_value[2] = evt.capture_signal -  previous_cap_value[2];
+            previous_cap_value[2] = evt.capture_signal;
+            current_cap_value[2] = (current_cap_value[2] / 10000) * (10000000000 / rtc_clk_apb_freq_get());
+            printf("CAP2 : %d us\n", current_cap_value[2]);
+        }
+    }
+}
+
+/**
+ * @brief this is ISR handler function, here we check for interrupt that triggers rising edge on CAP0 signal and according take action
+ */
+static void IRAM_ATTR isr_handler()
+{
+    uint32_t mcpwm_intr_status;
+    capture evt;
+    mcpwm_intr_status = MCPWM[MCPWM_UNIT_0]->int_st.val; //Read interrupt status
+    if (mcpwm_intr_status & CAP0_INT_EN) { //Check for interrupt on rising edge on CAP0 signal
+        evt.capture_signal = mcpwm_capture_signal_get_value(MCPWM_UNIT_0, MCPWM_SELECT_CAP0); //get capture signal counter value
+        evt.sel_cap_signal = MCPWM_SELECT_CAP0;
+        xQueueSendFromISR(cap_queue, &evt, NULL);
+    }
+    if (mcpwm_intr_status & CAP1_INT_EN) { //Check for interrupt on rising edge on CAP0 signal
+        evt.capture_signal = mcpwm_capture_signal_get_value(MCPWM_UNIT_0, MCPWM_SELECT_CAP1); //get capture signal counter value
+        evt.sel_cap_signal = MCPWM_SELECT_CAP1;
+        xQueueSendFromISR(cap_queue, &evt, NULL);
+    }
+    if (mcpwm_intr_status & CAP2_INT_EN) { //Check for interrupt on rising edge on CAP0 signal
+        evt.capture_signal = mcpwm_capture_signal_get_value(MCPWM_UNIT_0, MCPWM_SELECT_CAP2); //get capture signal counter value
+        evt.sel_cap_signal = MCPWM_SELECT_CAP2;
+        xQueueSendFromISR(cap_queue, &evt, NULL);
+    }
+    MCPWM[MCPWM_UNIT_0]->int_clr.val = mcpwm_intr_status;
+}
+
+/**
+ * @brief Configure whole MCPWM module
+ */
+static void mcpwm_example_config(void *arg)
+{
+    //1. mcpwm gpio initialization
+    mcpwm_example_gpio_initialize();
+
+    //2. initialize mcpwm configuration
+    printf("Configuring Initial Parameters of mcpwm...\n");
+    mcpwm_config_t pwm_config;
+    pwm_config.frequency = 1000;    //frequency = 1000Hz
+    pwm_config.cmpr_a = 60.0;       //duty cycle of PWMxA = 60.0%
+    pwm_config.cmpr_b = 50.0;       //duty cycle of PWMxb = 50.0%
+    pwm_config.counter_mode = MCPWM_UP_COUNTER;
+    pwm_config.duty_mode = MCPWM_DUTY_MODE_0;
+    mcpwm_init(MCPWM_UNIT_0, MCPWM_TIMER_0, &pwm_config);   //Configure PWM0A & PWM0B with above settings
+    pwm_config.frequency = 500;     //frequency = 500Hz
+    pwm_config.cmpr_a = 45.9;       //duty cycle of PWMxA = 45.9%
+    pwm_config.cmpr_b = 7.0;    //duty cycle of PWMxb = 07.0%
+    pwm_config.counter_mode = MCPWM_UP_COUNTER;
+    pwm_config.duty_mode = MCPWM_DUTY_MODE_0;
+    mcpwm_init(MCPWM_UNIT_0, MCPWM_TIMER_1, &pwm_config);   //Configure PWM1A & PWM1B with above settings
+    pwm_config.frequency = 400;     //frequency = 400Hz
+    pwm_config.cmpr_a = 23.2;       //duty cycle of PWMxA = 23.2%
+    pwm_config.cmpr_b = 97.0;       //duty cycle of PWMxb = 97.0%
+    pwm_config.counter_mode = MCPWM_UP_DOWN_COUNTER; //frequency is half when up down count mode is set i.e. SYMMETRIC PWM
+    pwm_config.duty_mode = MCPWM_DUTY_MODE_1;
+    mcpwm_init(MCPWM_UNIT_0, MCPWM_TIMER_2, &pwm_config);   //Configure PWM2A & PWM2B with above settings
+
+#if MCPWM_EN_CARRIER
+    //3. carrier configuration
+    //comment if you don't want to use carrier mode
+    //in carrier mode very high frequency carrier signal is generated at mcpwm high level signal
+    mcpwm_carrier_config_t chop_config;
+    chop_config.carrier_period = 6;         //carrier period = (6 + 1)*800ns
+    chop_config.carrier_duty = 3;           //carrier duty = (3)*12.5%
+    chop_config.carrier_os_mode = MCPWM_ONESHOT_MODE_EN; //If one shot mode is enabled then set pulse width, if disabled no need to set pulse width
+    chop_config.pulse_width_in_os = 3;      //first pulse width = (3 + 1)*carrier_period
+    chop_config.carrier_ivt_mode = MCPWM_CARRIER_OUT_IVT_EN; //output signal inversion enable
+    mcpwm_carrier_init(MCPWM_UNIT_0, MCPWM_TIMER_2, &chop_config);  //Enable carrier on PWM2A and PWM2B with above settings
+    //use mcpwm_carrier_disable function to disable carrier on mcpwm timer on which it was enabled
+#endif
+
+#if MCPWM_EN_DEADTIME
+    //4. deadtime configuration
+    //comment if you don't want to use deadtime submodule
+    //add rising edge delay or falling edge delay. There are 8 different types, each explained in mcpwm_deadtime_type_t in mcpwm.h
+    mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_BYPASS_FED, 1000, 1000);   //Enable deadtime on PWM2A and PWM2B with red = (1000)*100ns on PWM2A
+    mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_BYPASS_RED, 300, 2000);        //Enable deadtime on PWM1A and PWM1B with fed = (2000)*100ns on PWM1B
+    mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_ACTIVE_RED_FED_FROM_PWMXA, 656, 67);  //Enable deadtime on PWM0A and PWM0B with red = (656)*100ns & fed = (67)*100ns on PWM0A and PWM0B generated from PWM0A
+    //use mcpwm_deadtime_disable function to disable deadtime on mcpwm timer on which it was enabled
+#endif
+
+#if MCPWM_EN_FAULT
+    //5. enable fault condition
+    //comment if you don't want to use fault submodule, also u can comment the fault gpio signals
+    //whenever fault occurs you can configure mcpwm signal to either force low, force high or toggle.
+    //in cycmode, as soon as fault condition is over, the mcpwm signal is resumed, whereas in oneshot mode you need to reset.
+    mcpwm_fault_init(MCPWM_UNIT_0, MCPWM_HIGH_LEVEL_TGR, MCPWM_SELECT_F0); //Enable FAULT, when high level occurs on FAULT0 signal
+    mcpwm_fault_init(MCPWM_UNIT_0, MCPWM_HIGH_LEVEL_TGR, MCPWM_SELECT_F1); //Enable FAULT, when high level occurs on FAULT1 signal
+    mcpwm_fault_init(MCPWM_UNIT_0, MCPWM_HIGH_LEVEL_TGR, MCPWM_SELECT_F2); //Enable FAULT, when high level occurs on FAULT2 signal
+    mcpwm_fault_set_oneshot_mode(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_SELECT_F0, MCPWM_FORCE_MCPWMXA_HIGH, MCPWM_FORCE_MCPWMXB_LOW); //Action taken on PWM1A and PWM1B, when FAULT0 occurs
+    mcpwm_fault_set_oneshot_mode(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_SELECT_F1, MCPWM_FORCE_MCPWMXA_LOW, MCPWM_FORCE_MCPWMXB_HIGH); //Action taken on PWM1A and PWM1B, when FAULT1 occurs
+    mcpwm_fault_set_oneshot_mode(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_SELECT_F2, MCPWM_FORCE_MCPWMXA_HIGH, MCPWM_FORCE_MCPWMXB_LOW); //Action taken on PWM0A and PWM0B, when FAULT2 occurs
+    mcpwm_fault_set_oneshot_mode(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_SELECT_F1, MCPWM_FORCE_MCPWMXA_LOW, MCPWM_FORCE_MCPWMXB_HIGH); //Action taken on PWM0A and PWM0B, when FAULT1 occurs
+#endif
+
+#if MCPWM_EN_SYNC
+    //6. Syncronization configuration
+    //comment if you don't want to use sync submodule, also u can comment the sync gpio signals
+    //here synchronization occurs on PWM1A and PWM1B
+    mcpwm_sync_enable(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_SELECT_SYNC0, 200);    //Load counter value with 20% of period counter of mcpwm timer 1 when sync 0 occurs
+#endif
+
+#if MCPWM_EN_CAPTURE
+    //7. Capture configuration
+    //comment if you don't want to use capture submodule, also u can comment the capture gpio signals
+    //configure CAP0, CAP1 and CAP2 signal to start capture counter on rising edge
+    //we generate a gpio_test_signal of 20ms on GPIO 12 and connect it to one of the capture signal, the disp_captured_function displays the time between rising edge
+    //In general practice you can connect Capture  to external signal, measure time between rising edge or falling edge and take action accordingly
+    mcpwm_capture_enable(MCPWM_UNIT_0, MCPWM_SELECT_CAP0, MCPWM_POS_EDGE, 0);  //capture signal on rising edge, prescale = 0 i.e. 800,000,000 counts is equal to one second
+    mcpwm_capture_enable(MCPWM_UNIT_0, MCPWM_SELECT_CAP2, MCPWM_POS_EDGE, 0);  //capture signal on rising edge, prescale = 0 i.e. 800,000,000 counts is equal to one second
+    mcpwm_capture_enable(MCPWM_UNIT_0, MCPWM_SELECT_CAP1, MCPWM_POS_EDGE, 0);  //capture signal on rising edge, prescale = 0 i.e. 800,000,000 counts is equal to one second
+    //enable interrupt, so each this a rising edge occurs interrupt is triggered
+    MCPWM[MCPWM_UNIT_0]->int_ena.val = CAP0_INT_EN | CAP1_INT_EN | CAP2_INT_EN;  //Enable interrupt on  CAP0, CAP1 and CAP2 signal
+    mcpwm_isr_register(MCPWM_UNIT_0, isr_handler, NULL, ESP_INTR_FLAG_IRAM, NULL);  //Set ISR Handler
+#endif
+    vTaskDelete(NULL);
+}
+
+void app_main()
+{
+    printf("Testing MCPWM...\n");
+    cap_queue = xQueueCreate(1, sizeof(capture)); //comment if you don't want to use capture module
+    xTaskCreate(disp_captured_signal, "mcpwm_config", 4096, NULL, 5, NULL);  //comment if you don't want to use capture module
+    xTaskCreate(gpio_test_signal, "gpio_test_signal", 4096, NULL, 5, NULL); //comment if you don't want to use capture module
+    xTaskCreate(mcpwm_example_config, "mcpwm_example_config", 4096, NULL, 5, NULL);
+}
+
diff --git a/examples/peripherals/mcpwm/mcpwm_bldc_control/Makefile b/examples/peripherals/mcpwm/mcpwm_bldc_control/Makefile
new file mode 100644
index 000000000..47e1065c6
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_bldc_control/Makefile
@@ -0,0 +1,9 @@
+#
+# This is a project Makefile. It is assumed the directory this Makefile resides in is a
+# project subdirectory.
+#
+
+PROJECT_NAME := mcpwm_bldc_control_hall_sensor
+
+include $(IDF_PATH)/make/project.mk
+
diff --git a/examples/peripherals/mcpwm/mcpwm_bldc_control/README.md b/examples/peripherals/mcpwm/mcpwm_bldc_control/README.md
new file mode 100644
index 000000000..bcdbb706e
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_bldc_control/README.md
@@ -0,0 +1,43 @@
+# MCPWM BLDC motor control(hall sensor feedback) Example
+
+This example will show you how to use MCPWM module to control bldc motor with hall sensor feedback
+ 
+The following examples uses MCPWM module to control bldc motor and vary its speed continuously
+
+The bldc motor used for testing this code had hall sensor capture sequence of 6-->4-->5-->1-->3-->2-->6-->4--> and so on
+
+IR2136 3-ph bridge driver is used for testing this example code
+
+User needs to make changes according to the motor and gate driver ic used
+
+ 
+## Step 1: Pin assignment
+* The gpio init function initializes:
+	* GPIO15 is assigned as the MCPWM signal for 1H(UH)
+	* GPIO02 is assigned as the MCPWM signal for 1L(UL)
+	* GPIO00 is assigned as the MCPWM signal for 2H(VH)
+	* GPIO04 is assigned as the MCPWM signal for 2L(VL)
+	* GPIO16 is assigned as the MCPWM signal for 3H(WH)
+	* GPIO17 is assigned as the MCPWM signal for 3L(WL)
+	* GPIO25 is assigned as the MCPWM capture signal for Hall A
+	* GPIO26 is assigned as the MCPWM capture signal for HALL B
+	* GPIO27 is assigned as the MCPWM capture signal for HALL C
+
+
+## Step 2: Connection
+* Connect GPIO15 with 1H/UH  of BLDC motor driver
+* Connect GPIO02 with 1L/UL  of BLDC motor driver
+* Connect GPIO00 with 2H/VH  of BLDC motor driver
+* Connect GPIO04 with 2L/VL  of BLDC motor driver
+* Connect GPIO16 with 3H/WH  of BLDC motor driver
+* Connect GPIO17 with 3L/WL  of BLDC motor driver
+* Connect GPIO25 to hall sensor A output
+* Connect GPIO26 to hall sensor B output
+* Connect GPIO27 to hall sensor C output
+
+
+## Step 3: Initialize MCPWM
+ * You need to set the frequency and duty cycle of MCPWM timer
+ * You need to set the MCPWM channel you want to use, and bind the channel with one of the timers
+ * You need to set the capture unit, for POS/NEG edge capture
+ * Also reversing the hall sensor BIT weight, will make bldc motor rotate CW or CCW
diff --git a/examples/peripherals/mcpwm/mcpwm_bldc_control/main/component.mk b/examples/peripherals/mcpwm/mcpwm_bldc_control/main/component.mk
new file mode 100644
index 000000000..44bd2b527
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_bldc_control/main/component.mk
@@ -0,0 +1,3 @@
+#
+# Main Makefile. This is basically the same as a component makefile.
+#
diff --git a/examples/peripherals/mcpwm/mcpwm_bldc_control/main/mcpwm_bldc_control_hall_sensor_example.c b/examples/peripherals/mcpwm/mcpwm_bldc_control/main/mcpwm_bldc_control_hall_sensor_example.c
new file mode 100644
index 000000000..772a39176
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_bldc_control/main/mcpwm_bldc_control_hall_sensor_example.c
@@ -0,0 +1,313 @@
+
+/* MCPWM BLDC control Test code
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+
+/*
+ * The following examples uses mcpwm module to control bldc motor vary its speed continiously
+ * The BLDC motor used for testing this code had sequence of 6-->4-->5-->1-->3-->2-->6-->4--> and so on
+ * IR2136 3-ph bridge driver is used for testing this example code
+ * User needs to make changes according to the motor and gate driver ic used
+ */
+
+#include <stdio.h>
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "esp_attr.h"
+#include "soc/rtc.h"
+#include "driver/mcpwm.h"
+#include "soc/mcpwm_reg.h"
+#include "soc/mcpwm_struct.h"
+
+#define INITIAL_DUTY 10.0   //initial duty cycle is 10.0%
+#define MCPWM_GPIO_INIT 0    //select which function to use to initialize gpio signals
+
+#define CAP_SIG_NUM 3   //three capture signals from HALL-A, HALL-B, HALL-C
+#define CAP0_INT_EN BIT(27)  //Capture 0 interrupt bit
+#define CAP1_INT_EN BIT(28)  //Capture 1 interrupt bit
+#define CAP2_INT_EN BIT(29)  //Capture 2 interrupt bit
+
+#define GPIO_PWM0A_OUT 15   //Set GPIO 15 as PWM0A
+#define GPIO_PWM0B_OUT 02   //Set GPIO 02 as PWM0B
+#define GPIO_PWM1A_OUT 00   //Set GPIO 00 as PWM1A
+#define GPIO_PWM1B_OUT 04   //Set GPIO 04 as PWM1B
+#define GPIO_PWM2A_OUT 16   //Set GPIO 16 as PWM2A
+#define GPIO_PWM2B_OUT 17   //Set GPIO 17 as PWM2B
+#define GPIO_CAP0_IN   25   //Set GPIO 25 as  CAP0
+#define GPIO_CAP1_IN   26   //Set GPIO 26 as  CAP1
+#define GPIO_CAP2_IN   27   //Set GPIO 27 as  CAP2
+
+typedef struct {
+    uint32_t capture_signal;
+    mcpwm_capture_signal_t sel_cap_signal;
+} capture;
+
+static uint32_t hall_sensor_value = 0;
+static uint32_t hall_sensor_previous = 0;
+
+xQueueHandle cap_queue;
+
+static mcpwm_dev_t *MCPWM[2] = {&MCPWM0, &MCPWM1};
+
+static void mcpwm_example_gpio_initialize()
+{
+    printf("initializing mcpwm bldc control gpio...\n");
+#if MCPWM_GPIO_INIT
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM0A, GPIO_PWM0A_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM0B, GPIO_PWM0B_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM1A, GPIO_PWM1A_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM1B, GPIO_PWM1B_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM2A, GPIO_PWM2A_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM2B, GPIO_PWM2B_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_CAP_0, GPIO_CAP0_IN);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_CAP_1, GPIO_CAP1_IN);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM_CAP_2, GPIO_CAP2_IN);
+#else
+    mcpwm_pin_config_t pin_config = {
+        .mcpwm0a_out_num = GPIO_PWM0A_OUT,
+        .mcpwm0b_out_num = GPIO_PWM0B_OUT,
+        .mcpwm1a_out_num = GPIO_PWM1A_OUT,
+        .mcpwm1b_out_num = GPIO_PWM1B_OUT,
+        .mcpwm2a_out_num = GPIO_PWM2A_OUT,
+        .mcpwm2b_out_num = GPIO_PWM2B_OUT,
+        .mcpwm_cap0_in_num   = GPIO_CAP0_IN,
+        .mcpwm_cap1_in_num   = GPIO_CAP1_IN,
+        .mcpwm_cap2_in_num   = GPIO_CAP2_IN,
+        .mcpwm_sync0_in_num  = -1,  //Not used
+        .mcpwm_sync1_in_num  = -1,  //Not used
+        .mcpwm_sync2_in_num  = -1,  //Not used
+        .mcpwm_fault0_in_num = -1,  //Not used
+        .mcpwm_fault1_in_num = -1,  //Not used
+        .mcpwm_fault2_in_num = -1   //Not used
+    };
+    mcpwm_set_pin(MCPWM_UNIT_0, &pin_config);
+#endif
+    gpio_pulldown_en(GPIO_CAP0_IN);    //Enable pull down on CAP0   signal
+    gpio_pulldown_en(GPIO_CAP1_IN);    //Enable pull down on CAP1   signal
+    gpio_pulldown_en(GPIO_CAP2_IN);    //Enable pull down on CAP2   signal
+}
+
+/**
+ * @brief Set gpio 13, 12, 14  as our test signal of hall sensors, that generates high-low waveform continuously
+ *        Attach this pins to GPIO 27, 26, 25 respectively for capture unit
+ */
+static void gpio_test_signal(void *arg)
+{
+    printf("intializing test signal...\n");
+    gpio_config_t gp;
+    gp.intr_type = GPIO_INTR_DISABLE;
+    gp.mode = GPIO_MODE_OUTPUT;
+    gp.pin_bit_mask = GPIO_SEL_13 | GPIO_SEL_12 | GPIO_SEL_14;
+    gpio_config(&gp);
+    while (1) {
+        gpio_set_level(GPIO_NUM_13, 1); //Set H1 high
+        gpio_set_level(GPIO_NUM_12, 0); //Set H2 low
+        gpio_set_level(GPIO_NUM_14, 1); //Set H3 high
+        vTaskDelay(1);
+        gpio_set_level(GPIO_NUM_14, 0); //Set H3 low
+        vTaskDelay(1);
+        gpio_set_level(GPIO_NUM_12, 1); //Set H2 high
+        vTaskDelay(1);
+        gpio_set_level(GPIO_NUM_13, 0); //Set H1 low
+        vTaskDelay(1);
+        gpio_set_level(GPIO_NUM_14, 1); //Set H3 high
+        vTaskDelay(1);
+        gpio_set_level(GPIO_NUM_12, 0); //Set H2 high
+        vTaskDelay(1);
+    }
+}
+
+/**
+ * @brief When interrupt occurs, we receive the counter value and display the time between two rising edge
+ */
+static void disp_captured_signal(void *arg)
+{
+    uint32_t *current_cap_value = (uint32_t *)malloc(sizeof(CAP_SIG_NUM));
+    uint32_t *previous_cap_value = (uint32_t *)malloc(sizeof(CAP_SIG_NUM));
+    capture evt;
+    while (1) {
+        xQueueReceive(cap_queue, &evt, portMAX_DELAY);
+        if (evt.sel_cap_signal == MCPWM_SELECT_CAP0) {
+            current_cap_value[0] = evt.capture_signal - previous_cap_value[0];
+            previous_cap_value[0] = evt.capture_signal;
+            current_cap_value[0] = (current_cap_value[0] / 10000) * (10000000000 / rtc_clk_apb_freq_get());
+            //printf("CAP0 : %d us\n", current_cap_value[0]);
+        }
+        if (evt.sel_cap_signal == MCPWM_SELECT_CAP1) {
+            current_cap_value[1] = evt.capture_signal - previous_cap_value[1];
+            previous_cap_value[1] = evt.capture_signal;
+            current_cap_value[1] = (current_cap_value[1] / 10000) * (10000000000 / rtc_clk_apb_freq_get());
+            //printf("CAP1 : %d us\n", current_cap_value[1]);
+        }
+        if (evt.sel_cap_signal == MCPWM_SELECT_CAP2) {
+            current_cap_value[2] = evt.capture_signal -  previous_cap_value[2];
+            previous_cap_value[2] = evt.capture_signal;
+            current_cap_value[2] = (current_cap_value[2] / 10000) * (10000000000 / rtc_clk_apb_freq_get());
+            //printf("CAP2 : %d us\n", current_cap_value[2]);
+        }
+    }
+}
+
+/**
+ * @brief this is ISR handler function, here we check for interrupt that triggers rising edge on CAP0 signal and according take action
+ */
+static void IRAM_ATTR isr_handler()
+{
+    uint32_t mcpwm_intr_status;
+    capture evt;
+    mcpwm_intr_status = MCPWM[MCPWM_UNIT_0]->int_st.val; //Read interrupt status
+    if (mcpwm_intr_status & CAP0_INT_EN) { //Check for interrupt on rising edge on CAP0 signal
+        evt.capture_signal = mcpwm_capture_signal_get_value(MCPWM_UNIT_0, MCPWM_SELECT_CAP0); //get capture signal counter value
+        evt.sel_cap_signal = MCPWM_SELECT_CAP0;
+        xQueueSendFromISR(cap_queue, &evt, NULL);
+    }
+    if (mcpwm_intr_status & CAP1_INT_EN) { //Check for interrupt on rising edge on CAP1 signal
+        evt.capture_signal = mcpwm_capture_signal_get_value(MCPWM_UNIT_0, MCPWM_SELECT_CAP1); //get capture signal counter value
+        evt.sel_cap_signal = MCPWM_SELECT_CAP1;
+        xQueueSendFromISR(cap_queue, &evt, NULL);
+    }
+    if (mcpwm_intr_status & CAP2_INT_EN) { //Check for interrupt on rising edge on CAP2 signal
+        evt.capture_signal = mcpwm_capture_signal_get_value(MCPWM_UNIT_0, MCPWM_SELECT_CAP2); //get capture signal counter value
+        evt.sel_cap_signal = MCPWM_SELECT_CAP2;
+        xQueueSendFromISR(cap_queue, &evt, NULL);
+    }
+    MCPWM[MCPWM_UNIT_0]->int_clr.val = mcpwm_intr_status;
+}
+
+static void change_duty(void *arg)
+{
+    int j;
+    while (1) {
+        for (j = 0; j < 18; j++) {
+            //printf("duty cycle: %d\n", (0 +j*50));
+            mcpwm_set_duty(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_A, (INITIAL_DUTY + j * 5.0));
+            mcpwm_set_duty(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_B, (INITIAL_DUTY + j * 5.0));
+            mcpwm_set_duty(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_A, (INITIAL_DUTY + j * 5.0));
+            mcpwm_set_duty(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_B, (INITIAL_DUTY + j * 5.0));
+            mcpwm_set_duty(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_A, (INITIAL_DUTY + j * 5.0));
+            mcpwm_set_duty(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_B, (INITIAL_DUTY + j * 5.0));
+            vTaskDelay(500 / portTICK_RATE_MS);
+        }
+    }
+}
+
+/**
+ * @brief Configure whole MCPWM module for bldc motor control
+ */
+static void mcpwm_example_bldc_control(void *arg)
+{
+    //1. mcpwm gpio initialization
+    mcpwm_example_gpio_initialize();
+
+    //2. initial mcpwm configuration
+    printf("Configuring Initial Parameters of mcpwm bldc control...\n");
+    mcpwm_config_t pwm_config;
+    pwm_config.frequency = 1000;    //frequency = 1000Hz
+    pwm_config.cmpr_a = 50.0;    //duty cycle of PWMxA = 50.0%
+    pwm_config.cmpr_b = 50.0;    //duty cycle of PWMxb = 50.0%
+    pwm_config.counter_mode = MCPWM_UP_COUNTER;
+    pwm_config.duty_mode = MCPWM_DUTY_MODE_1;
+    mcpwm_init(MCPWM_UNIT_0, MCPWM_TIMER_0, &pwm_config);    //Configure PWM0A & PWM0B with above settings
+    mcpwm_init(MCPWM_UNIT_0, MCPWM_TIMER_1, &pwm_config);    //Configure PWM1A & PWM1B with above settings
+    mcpwm_init(MCPWM_UNIT_0, MCPWM_TIMER_2, &pwm_config);    //Configure PWM2A & PWM2B with above settings
+
+    //3. Capture configuration
+    //configure CAP0, CAP1 and CAP2 signal to start capture counter on rising edge
+    //we generate a gpio_test_signal of 20ms on GPIO 12 and connect it to one of the capture signal, the disp_captured_function displays the time between rising edge
+    //In general practice you can connect Capture  to external signal, measure time between rising edge or falling edge and take action accordingly
+    mcpwm_capture_enable(MCPWM_UNIT_0, MCPWM_SELECT_CAP0, MCPWM_POS_EDGE, 0);  //capture signal on rising edge, pulse num = 0 i.e. 800,000,000 counts is equal to one second
+    mcpwm_capture_enable(MCPWM_UNIT_0, MCPWM_SELECT_CAP1, MCPWM_POS_EDGE, 0);  //capture signal on rising edge, pulse num = 0 i.e. 800,000,000 counts is equal to one second
+    mcpwm_capture_enable(MCPWM_UNIT_0, MCPWM_SELECT_CAP2, MCPWM_POS_EDGE, 0);  //capture signal on rising edge, pulse num = 0 i.e. 800,000,000 counts is equal to one second
+    //enable interrupt, so each this a rising edge occurs interrupt is triggered
+    MCPWM[MCPWM_UNIT_0]->int_ena.val = (CAP0_INT_EN | CAP1_INT_EN | CAP2_INT_EN);  //Enable interrupt on  CAP0, CAP1 and CAP2 signal
+    mcpwm_isr_register(MCPWM_UNIT_0, isr_handler, NULL, ESP_INTR_FLAG_IRAM, NULL);  //Set ISR Handler
+    //According to the hall sensor input value take action on PWM0A/0B/1A/1B/2A/2B
+    while (1) {
+        hall_sensor_value = (gpio_get_level(GPIO_NUM_27) * 1) + (gpio_get_level(GPIO_NUM_26) * 2) + (gpio_get_level(GPIO_NUM_25) * 4);
+        if (hall_sensor_value != hall_sensor_previous) {
+            //printf("hall_sen val: %d\n", hall_sensor_value);
+            if (hall_sensor_value == 2) {
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_A);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_B);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_A);
+                mcpwm_set_signal_high(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_B);
+                //MCPWMXA to duty mode 1 and MCPWMXB to duty mode 0 or vice versa will generate MCPWM compliment signal of each other, there are also other ways to do it
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_A, MCPWM_DUTY_MODE_1); //Set PWM0A to duty mode one
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_B, MCPWM_DUTY_MODE_0); //Set PWM0B back to duty mode zero
+                mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_BYPASS_FED, 100, 100);   //Deadtime of 10us
+            }
+            if (hall_sensor_value == 6) {
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_A);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_B);
+                mcpwm_deadtime_disable(MCPWM_UNIT_0, MCPWM_TIMER_0);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_A);
+                mcpwm_set_signal_high(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_B);
+                //MCPWMXA to duty mode 1 and MCPWMXB to duty mode 0 or vice versa will generate MCPWM compliment signal of each other, there are also other ways to do it
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_A, MCPWM_DUTY_MODE_1); //Set PWM2A to duty mode one
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_B, MCPWM_DUTY_MODE_0); //Set PWM2B back to duty mode zero
+                mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_BYPASS_FED, 100, 100);   //Deadtime of 10us
+            }
+            if (hall_sensor_value == 4) {
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_A);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_B);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_A);
+                mcpwm_set_signal_high(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_B);
+                //MCPWMXA to duty mode 1 and MCPWMXB to duty mode 0 or vice versa will generate MCPWM compliment signal of each other, there are also other ways to do it
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_A, MCPWM_DUTY_MODE_1); //Set PWM2A to duty mode one
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_B, MCPWM_DUTY_MODE_0); //Set PWM2B back to duty mode zero
+                mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_BYPASS_FED, 100, 100);   //Deadtime of 10us
+            }
+            if (hall_sensor_value == 5) {
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_A);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_B);
+                mcpwm_deadtime_disable(MCPWM_UNIT_0, MCPWM_TIMER_2);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_A);
+                mcpwm_set_signal_high(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_B);
+                //MCPWMXA to duty mode 1 and MCPWMXB to duty mode 0 or vice versa will generate MCPWM compliment signal of each other, there are also other ways to do it
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_A, MCPWM_DUTY_MODE_1); //Set PWM1A to duty mode one
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_B, MCPWM_DUTY_MODE_0); //Set PWM1B back to duty mode zero
+                mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_BYPASS_FED, 100, 100);   //Deadtime of 10uss
+            }
+            if (hall_sensor_value == 1) {
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_A);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_B);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_A);
+                mcpwm_set_signal_high(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_B);
+                //MCPWMXA to duty mode 1 and MCPWMXB to duty mode 0 or vice versa will generate MCPWM compliment signal of each other, there are also other ways to do it
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_A, MCPWM_DUTY_MODE_1); //Set PWM1A to duty mode one
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_B, MCPWM_DUTY_MODE_0); //Set PWM1B back to duty mode zero
+                mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_BYPASS_FED, 100, 100);   //Deadtime of 10uss
+            }
+            if (hall_sensor_value == 3) {
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_A);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_OPR_B);
+                mcpwm_deadtime_disable(MCPWM_UNIT_0, MCPWM_TIMER_1);
+                mcpwm_set_signal_low(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_A);
+                mcpwm_set_signal_high(MCPWM_UNIT_0, MCPWM_TIMER_2, MCPWM_OPR_B);
+                //MCPWMXA to duty mode 1 and MCPWMXB to duty mode 0 or vice versa will generate MCPWM compliment signal of each other, there are also other ways to do it
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_A, MCPWM_DUTY_MODE_1); //Set PWM0A to duty mode one
+                mcpwm_set_duty_type(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_B, MCPWM_DUTY_MODE_0); //Set PWM0B back to duty mode zero
+                mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_BYPASS_FED, 100, 100);   //Deadtime of 10us
+            }
+            hall_sensor_previous = hall_sensor_value;
+        }
+    }
+}
+
+void app_main()
+{
+    printf("Testing MCPWM BLDC Control...\n");
+    //xTaskCreate(change_duty, "change_duty", 2048, NULL, 2, NULL); //uncomment to change duty continuously
+    cap_queue = xQueueCreate(1, sizeof(capture)); //comment if you don't want to use capture module
+    //xTaskCreate(gpio_test_signal, "gpio_test_signal", 2048, NULL, 2, NULL);
+    xTaskCreate(disp_captured_signal, "mcpwm_config", 4096, NULL, 2, NULL);  //comment if you don't want to use capture module
+    xTaskCreate(mcpwm_example_bldc_control, "mcpwm_example_bldc_control", 4096, NULL, 2, NULL);
+}
+
diff --git a/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/Makefile b/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/Makefile
new file mode 100644
index 000000000..9dd14ffa7
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/Makefile
@@ -0,0 +1,9 @@
+#
+# This is a project Makefile. It is assumed the directory this Makefile resides in is a
+# project subdirectory.
+#
+
+PROJECT_NAME := mcpwm_brushed_dc_control
+
+include $(IDF_PATH)/make/project.mk
+
diff --git a/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/README.md b/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/README.md
new file mode 100644
index 000000000..9882c3a3b
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/README.md
@@ -0,0 +1,22 @@
+# MCPWM brushed dc motor control Example
+
+This example will show you how to use MCPWM module to control brushed dc motor, you need to make connection between ESP32 and motor driver
+ 
+This code is tested with L298 motor driver, user needs to make changes according to the driver they use
+ 
+Motor first moves forward, then backward and then stops for 2 Secs each countinuously
+
+
+## Step 1: Pin assignment
+* GPIO15 is assigned as the enable/input 1 for motor driver    
+* GPIO16 is assigned as the enable/input 2 for motor driver
+
+
+## Step 2: Connection
+* connect GPIO15 with input 1 of motor driver
+* connect GPIO16 with input 2 of motor driver
+
+
+## Step 3: Initialize MCPWM
+* You need to set the frequency and duty cycle of MCPWM timer
+* You need to set the MCPWM channel you want to use, and bind the channel with one of the timers
diff --git a/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/main/component.mk b/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/main/component.mk
new file mode 100644
index 000000000..44bd2b527
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/main/component.mk
@@ -0,0 +1,3 @@
+#
+# Main Makefile. This is basically the same as a component makefile.
+#
diff --git a/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/main/mcpwm_brushed_dc_control_example.c b/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/main/mcpwm_brushed_dc_control_example.c
new file mode 100644
index 000000000..00b5ddd06
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_brushed_dc_control/main/mcpwm_brushed_dc_control_example.c
@@ -0,0 +1,96 @@
+/* brushed dc motor control example
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+
+/*
+ * This example will show you how to use MCPWM module to control brushed dc motor.
+ * This code is tested with L298 motor driver.
+ * User may need to make changes according to the motor driver they use.
+*/
+
+#include <stdio.h>
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "esp_attr.h"
+
+#include "driver/mcpwm.h"
+#include "soc/mcpwm_reg.h"
+#include "soc/mcpwm_struct.h"
+
+#define GPIO_PWM0A_OUT 15   //Set GPIO 15 as PWM0A
+#define GPIO_PWM0B_OUT 16   //Set GPIO 16 as PWM0B
+
+static void mcpwm_example_gpio_initialize()
+{
+    printf("initializing mcpwm gpio...\n");
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM0A, GPIO_PWM0A_OUT);
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM0B, GPIO_PWM0B_OUT);
+}
+
+/**
+ * @brief motor moves in forward direction, with duty cycle = duty %
+ */
+static void brushed_motor_forward(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num , float duty_cycle)
+{
+    mcpwm_set_signal_low(mcpwm_num, timer_num, MCPWM_OPR_B);
+    mcpwm_set_duty(mcpwm_num, timer_num, MCPWM_OPR_A, duty_cycle);
+    mcpwm_set_duty_type(mcpwm_num, timer_num, MCPWM_OPR_A, MCPWM_DUTY_MODE_0); //call this each time, if operator was previously in low/high state
+}
+
+/**
+ * @brief motor moves in backward direction, with duty cycle = duty %
+ */
+static void brushed_motor_backward(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num , float duty_cycle)
+{
+    mcpwm_set_signal_low(mcpwm_num, timer_num, MCPWM_OPR_A);
+    mcpwm_set_duty(mcpwm_num, timer_num, MCPWM_OPR_B, duty_cycle);
+    mcpwm_set_duty_type(mcpwm_num, timer_num, MCPWM_OPR_B, MCPWM_DUTY_MODE_0);  //call this each time, if operator was previously in low/high state
+}
+
+/**
+ * @brief motor stop
+ */
+static void brushed_motor_stop(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
+{
+    mcpwm_set_signal_low(mcpwm_num, timer_num, MCPWM_OPR_A);
+    mcpwm_set_signal_low(mcpwm_num, timer_num, MCPWM_OPR_B);
+}
+
+/**
+ * @brief Configure MCPWM module for brushed dc motor
+ */
+static void mcpwm_example_brushed_motor_control(void *arg)
+{
+    //1. mcpwm gpio initialization
+    mcpwm_example_gpio_initialize();
+
+    //2. initial mcpwm configuration
+    printf("Configuring Initial Parameters of mcpwm...\n");
+    mcpwm_config_t pwm_config;
+    pwm_config.frequency = 1000;    //frequency = 500Hz,
+    pwm_config.cmpr_a = 0;    //duty cycle of PWMxA = 0
+    pwm_config.cmpr_b = 0;    //duty cycle of PWMxb = 0
+    pwm_config.counter_mode = MCPWM_UP_COUNTER;
+    pwm_config.duty_mode = MCPWM_DUTY_MODE_0;
+    mcpwm_init(MCPWM_UNIT_0, MCPWM_TIMER_0, &pwm_config);    //Configure PWM0A & PWM0B with above settings
+    while (1) {
+        brushed_motor_forward(MCPWM_UNIT_0, MCPWM_TIMER_0, 50.0);
+        vTaskDelay(2000 / portTICK_RATE_MS);
+        brushed_motor_backward(MCPWM_UNIT_0, MCPWM_TIMER_0, 30.0);
+        vTaskDelay(2000 / portTICK_RATE_MS);
+        brushed_motor_stop(MCPWM_UNIT_0, MCPWM_TIMER_0);
+        vTaskDelay(2000 / portTICK_RATE_MS);
+    }
+}
+
+void app_main()
+{
+    printf("Testing brushed motor...\n");
+    xTaskCreate(mcpwm_example_brushed_motor_control, "mcpwm_examlpe_brushed_motor_control", 4096, NULL, 5, NULL);
+}
\ No newline at end of file
diff --git a/examples/peripherals/mcpwm/mcpwm_servo_control/Makefile b/examples/peripherals/mcpwm/mcpwm_servo_control/Makefile
new file mode 100644
index 000000000..29edf7012
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_servo_control/Makefile
@@ -0,0 +1,9 @@
+#
+# This is a project Makefile. It is assumed the directory this Makefile resides in is a
+# project subdirectory.
+#
+
+PROJECT_NAME := mcpwm_servo_control
+
+include $(IDF_PATH)/make/project.mk
+
diff --git a/examples/peripherals/mcpwm/mcpwm_servo_control/README.md b/examples/peripherals/mcpwm/mcpwm_servo_control/README.md
new file mode 100644
index 000000000..cafab4d71
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_servo_control/README.md
@@ -0,0 +1,19 @@
+# MCPWM servo motor control Example
+
+This example will show you how to use MCPWM module to control servo motor
+ 
+Assign pulse width range and the maximum degree, accordingly the servo will move from 0 to maximum degree continuously
+ 
+
+## Step 1: Pin assignment
+* GPIO15 is assigned as the MCPWM signal for servo motor 
+
+
+## Step 2: Connection
+* connect GPIO15 with servo pwm signal
+* other two wires of servo motor are VCC and GND
+
+
+## Step 3: Initialize MCPWM
+* You need to set the frequency(generally 50 Hz) and duty cycle of MCPWM timer
+* You need to set the MCPWM channel you want to use, and bind the channel with one of the timers
diff --git a/examples/peripherals/mcpwm/mcpwm_servo_control/main/component.mk b/examples/peripherals/mcpwm/mcpwm_servo_control/main/component.mk
new file mode 100644
index 000000000..44bd2b527
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_servo_control/main/component.mk
@@ -0,0 +1,3 @@
+#
+# Main Makefile. This is basically the same as a component makefile.
+#
diff --git a/examples/peripherals/mcpwm/mcpwm_servo_control/main/mcpwm_servo_control_example.c b/examples/peripherals/mcpwm/mcpwm_servo_control/main/mcpwm_servo_control_example.c
new file mode 100644
index 000000000..cbc07e105
--- /dev/null
+++ b/examples/peripherals/mcpwm/mcpwm_servo_control/main/mcpwm_servo_control_example.c
@@ -0,0 +1,88 @@
+/* servo motor control example
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+#include <stdio.h>
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "esp_attr.h"
+
+#include "driver/mcpwm.h"
+#include "soc/mcpwm_reg.h"
+#include "soc/mcpwm_struct.h"
+
+//You can get these value from the datasheet of servo you use, in general pulse width varies between 1000 to 2000 mocrosecond
+#define SERVO_MIN_PULSEWIDTH 1000 //Minimum pulse width in microsecond
+#define SERVO_MAX_PULSEWIDTH 2000 //Maximum pulse width in microsecond
+#define SERVO_MAX_DEGREE 90 //Maximum angle in degree upto which servo can rotate
+
+static void mcpwm_example_gpio_initialize()
+{
+    printf("initializing mcpwm servo control gpio......\n");
+    mcpwm_gpio_init(MCPWM_UNIT_0, MCPWM0A, 18);    //Set GPIO 18 as PWM0A, to which servo is connected
+}
+
+/**
+ * @brief Use this function to calcute pulse width for per degree rotation
+ *
+ * @param  degree_of_rotation the angle in degree to which servo has to rotate
+ *
+ * @return
+ *     - calculated pulse width
+ */
+static uint32_t servo_per_degree_init(uint32_t degree_of_rotation)
+{
+    uint32_t cal_pulsewidth = 0;
+    cal_pulsewidth = (SERVO_MIN_PULSEWIDTH + (((SERVO_MAX_PULSEWIDTH - SERVO_MIN_PULSEWIDTH) * (degree_of_rotation)) / (SERVO_MAX_DEGREE)));
+    return cal_pulsewidth;
+}
+
+/**
+ * @brief directly set servo motor to a particular angle
+ */
+static void servo_set_angle(uint32_t angle_of_rotation)
+{
+    uint32_t angle_t;
+    angle_t = servo_per_degree_init(angle_of_rotation);
+    mcpwm_set_duty_in_us(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_A, angle_t);
+}
+
+/**
+ * @brief Configure MCPWM module
+ */
+void mcpwm_example_servo_control(void *arg)
+{
+    uint32_t angle, count;
+    //1. mcpwm gpio initialization
+    mcpwm_example_gpio_initialize();
+
+    //2. initial mcpwm configuration
+    printf("Configuring Initial Parameters of mcpwm......\n");
+    mcpwm_config_t pwm_config;
+    pwm_config.frequency = 50;    //frequency = 50Hz, i.e. for every servo motor time period should be 20ms
+    pwm_config.cmpr_a = 0;    //duty cycle of PWMxA = 0
+    pwm_config.cmpr_b = 0;    //duty cycle of PWMxb = 0
+    pwm_config.counter_mode = MCPWM_UP_COUNTER;
+    pwm_config.duty_mode = MCPWM_DUTY_MODE_0;
+    mcpwm_init(MCPWM_UNIT_0, MCPWM_TIMER_0, &pwm_config);    //Configure PWM0A & PWM0B with above settings
+    while (1) {
+        for (count = 0; count < SERVO_MAX_DEGREE; count++) {
+            printf("Angle of rotation: %d\n", count);
+            angle = servo_per_degree_init(count);
+            printf("pulse width: %dus\n", angle);
+            mcpwm_set_duty_in_us(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_OPR_A, angle);
+            vTaskDelay(10);     //Add delay, since it takes time for servo to rotate, generally 100ms/60degree rotation at 5V
+        }
+    }
+}
+
+void app_main()
+{
+    printf("Testing servo motor.......\n");
+    xTaskCreate(mcpwm_example_servo_control, "mcpwm_example_servo_control", 4096, NULL, 5, NULL);
+}
\ No newline at end of file