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esp32s2:remove unsupported xtal choice

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ESP32-S2 only supports 40MHz XTAL and doesn't have XTAL autodetection.
This commit is contained in:
suda-morris 2019-12-20 22:23:37 +08:00 committed by morris
parent da877bcc8f
commit 1ffb546135
5 changed files with 19 additions and 176 deletions
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2
components/bootloader_support/src/bootloader_clock.c
View file

@ -55,7 +55,7 @@ void bootloader_clock_configure(void)
clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
clk_cfg.xtal_freq = CONFIG_ESP32S2_XTAL_FREQ;
clk_cfg.xtal_freq = RTC_XTAL_FREQ_40M;
clk_cfg.cpu_freq = RTC_CPU_FREQ_80M;
#endif
clk_cfg.slow_freq = rtc_clk_slow_freq_get();

30
components/esp32s2beta/Kconfig
View file

@ -478,36 +478,6 @@ menu "ESP32S2-specific"
In case more value will help improve the definition of the launch of the crystal.
If the crystal could not start, it will be switched to internal RC.
choice ESP32S2_XTAL_FREQ_SEL
prompt "Main XTAL frequency"
default ESP32S2_XTAL_FREQ_40
help
ESP32 currently supports the following XTAL frequencies:
- 26 MHz
- 40 MHz
Startup code can automatically estimate XTAL frequency. This feature
uses the internal 8MHz oscillator as a reference. Because the internal
oscillator frequency is temperature dependent, it is not recommended
to use automatic XTAL frequency detection in applications which need
to work at high ambient temperatures and use high-temperature
qualified chips and modules.
config ESP32S2_XTAL_FREQ_40
bool "40 MHz"
config ESP32S2_XTAL_FREQ_26
bool "26 MHz"
config ESP32S2_XTAL_FREQ_AUTO
bool "Autodetect"
endchoice
# Keep these values in sync with rtc_xtal_freq_t enum in soc/rtc.h
config ESP32S2_XTAL_FREQ
int
default 0 if ESP32S2_XTAL_FREQ_AUTO
default 40 if ESP32S2_XTAL_FREQ_40
default 26 if ESP32S2_XTAL_FREQ_26
config ESP32S2_DISABLE_BASIC_ROM_CONSOLE
bool "Permanently disable BASIC ROM Console"
default n

2
components/esp32s2beta/clk.c
View file

@ -57,7 +57,7 @@ void esp_clk_init(void)
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
rtc_init(cfg);
assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);

17
components/soc/esp32s2beta/include/soc/rtc.h
View file

@ -58,10 +58,7 @@ extern "C" {
* Enum values should be equal to frequency in MHz.
*/
typedef enum {
RTC_XTAL_FREQ_AUTO = 0, //!< Automatic XTAL frequency detection
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
RTC_XTAL_FREQ_26M = 26, //!< 26 MHz XTAL
RTC_XTAL_FREQ_24M = 24, //!< 24 MHz XTAL
} rtc_xtal_freq_t;
/**
@ -124,7 +121,7 @@ typedef struct {
* Default initializer for rtc_clk_config_t
*/
#define RTC_CLK_CONFIG_DEFAULT() { \
.xtal_freq = RTC_XTAL_FREQ_AUTO, \
.xtal_freq = RTC_XTAL_FREQ_40M, \
.cpu_freq = RTC_CPU_FREQ_80M, \
.fast_freq = RTC_FAST_FREQ_8M, \
.slow_freq = RTC_SLOW_FREQ_RTC, \
@ -141,15 +138,6 @@ void rtc_clk_8m_divider_set(uint32_t div);
/**
* Initialize clocks and set CPU frequency
*
* If cfg.xtal_freq is set to RTC_XTAL_FREQ_AUTO, this function will attempt
* to auto detect XTAL frequency. Auto detection is performed by comparing
* XTAL frequency with the frequency of internal 8MHz oscillator. Note that at
* high temperatures the frequency of the internal 8MHz oscillator may drift
* enough for auto detection to be unreliable.
* Auto detection code will attempt to distinguish between 26MHz and 40MHz
* crystals. 24 MHz crystals are not supported by auto detection code.
* If XTAL frequency can not be auto detected, this 26MHz frequency will be used.
*
* @param cfg clock configuration as rtc_clk_config_t
*/
void rtc_clk_init(rtc_clk_config_t cfg);
@ -158,8 +146,7 @@ void rtc_clk_init(rtc_clk_config_t cfg);
* @brief Get main XTAL frequency
*
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
* rtc_clk_init function, or if the value was RTC_XTAL_FREQ_AUTO, the detected
* XTAL frequency.
* rtc_clk_init function
*
* @return XTAL frequency, one of rtc_xtal_freq_t
*/

120
components/soc/esp32s2beta/rtc_clk.c
View file

@ -351,6 +351,8 @@ void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_pll_t pll_freq)
uint8_t dchgp;
uint8_t dcur;
assert(xtal_freq == RTC_XTAL_FREQ_40M);
if (pll_freq == RTC_PLL_480M) {
/* Raise the voltage, if needed */
/* move to 240M logic */
@ -358,40 +360,12 @@ void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_pll_t pll_freq)
/* Set this register to let digital know pll is 480M */
SET_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
/* Configure 480M PLL */
switch (xtal_freq) {
case RTC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 4;
break;
case RTC_XTAL_FREQ_26M:
div_ref = 12;
div7_0 = 156;
dr1 = 3;
dr3 = 3;
dchgp = 4;
dcur = 1;
break;
case RTC_XTAL_FREQ_24M:
div_ref = 11;
div7_0 = 156;
dr1 = 3;
dr3 = 3;
dchgp = 4;
dcur = 1;
break;
default:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 4;
break;
}
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
} else {
/* Raise the voltage */
@ -399,40 +373,12 @@ void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_pll_t pll_freq)
//ets_delay_us(DELAY_PLL_DBIAS_RAISE);
CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
/* Configure 480M PLL */
switch (xtal_freq) {
case RTC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 4;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 5;
break;
case RTC_XTAL_FREQ_26M:
div_ref = 12;
div7_0 = 236;
dr1 = 3;
dr3 = 3;
dchgp = 0;
dcur = 2;
break;
case RTC_XTAL_FREQ_24M:
div_ref = 11;
div7_0 = 236;
dr1 = 3;
dr3 = 3;
dchgp = 0;
dcur = 2;
break;
default:
div_ref = 0;
div7_0 = 4;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 5;
break;
}
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
}
uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
@ -719,7 +665,7 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
if (!clk_val_is_valid(xtal_freq_reg)) {
SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
return RTC_XTAL_FREQ_AUTO;
return RTC_XTAL_FREQ_40M;
}
return reg_val_to_clk_val(xtal_freq_reg);
}
@ -729,42 +675,6 @@ void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
}
static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
{
/* Enable 8M/256 clock if needed */
const bool clk_8m_enabled = rtc_clk_8m_enabled();
const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
if (!clk_8md256_enabled) {
rtc_clk_8m_enable(true, true);
}
uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES);
/* cal_val contains period of 8M/256 clock in XTAL clock cycles
* (shifted by RTC_CLK_CAL_FRACT bits).
* Xtal frequency will be (cal_val * 8M / 256) / 2^19
*/
uint32_t freq_mhz = (cal_val * RTC_FAST_CLK_FREQ_APPROX / MHZ / 256 ) >> RTC_CLK_CAL_FRACT;
/* Guess the XTAL type. For now, only 40 and 26MHz are supported.
*/
switch (freq_mhz) {
case 21 ... 31:
return RTC_XTAL_FREQ_26M;
case 32 ... 33:
SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz);
return RTC_XTAL_FREQ_26M;
case 34 ... 35:
SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz);
return RTC_XTAL_FREQ_40M;
case 36 ... 45:
return RTC_XTAL_FREQ_40M;
default:
SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
return RTC_XTAL_FREQ_AUTO;
}
/* Restore 8M and 8md256 clocks to original state */
rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled);
}
void rtc_clk_apb_freq_update(uint32_t apb_freq)
{
WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
@ -829,31 +739,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
/* Estimate XTAL frequency */
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
/* XTAL frequency has already been set, use existing value */
xtal_freq = rtc_clk_xtal_freq_get();
} else {
/* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
xtal_freq = rtc_clk_xtal_freq_estimate();
if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
xtal_freq = RTC_XTAL_FREQ_26M;
}
}
} else if (!clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
/* Exact frequency was set in sdkconfig, but still warn if autodetected
* frequency is different. If autodetection failed, worst case we get a
* bit of garbage output.
*/
rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
if (est_xtal_freq != xtal_freq) {
SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32S2_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
xtal_freq, est_xtal_freq);
}
}
uart_tx_wait_idle(0);
rtc_clk_xtal_freq_update(xtal_freq);
rtc_clk_apb_freq_update(xtal_freq * MHZ);