component/esp32 : remove pm gpio dbg
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@ -188,7 +188,6 @@ esp_err_t esp_phy_rf_deinit(phy_rf_module_t module)
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}
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if (s_is_phy_rf_en == false) {
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gpio_set_level(15, 0); //G1, 15
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// Disable PHY and RF.
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phy_close_rf();
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// Disable WiFi/BT common peripheral clock. Do not disable clock for hardware RNG
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