Merge branch 'feature/esp32s2beta_gpio_rtcio_driver' into feature/esp32s2beta

components/driver/gpio.c

@@ -42,44 +42,60 @@ static portMUX_TYPE gpio_spinlock = portMUX_INITIALIZER_UNLOCKED;
 esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
+#if CONFIG_IDF_TARGET_ESP32
     if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
         rtc_gpio_pullup_en(gpio_num);
     } else {
         REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+#endif
     return ESP_OK;
 }
 
 esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
+#if CONFIG_IDF_TARGET_ESP32
     if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
         rtc_gpio_pullup_dis(gpio_num);
     } else {
         REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+#endif
     return ESP_OK;
 }
 
 esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
+#if CONFIG_IDF_TARGET_ESP32
     if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
         rtc_gpio_pulldown_en(gpio_num);
     } else {
         REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+#endif
     return ESP_OK;
 }
 
 esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
+#if CONFIG_IDF_TARGET_ESP32
     if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
         rtc_gpio_pulldown_dis(gpio_num);
     } else {
         REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+#endif
     return ESP_OK;
 }
 
@@ -104,11 +120,17 @@ static esp_err_t gpio_intr_enable_on_core (gpio_num_t gpio_num, uint32_t core_id
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
     gpio_intr_status_clr(gpio_num);
+#if CONFIG_IDF_TARGET_ESP32
     if (core_id == 0) {
         GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA;     //enable pro cpu intr
     } else {
         GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA;     //enable pro cpu intr
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    if (core_id == 0) {
+        GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+    }
+#endif
     return ESP_OK;
 }
 
@@ -255,6 +277,7 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
         ESP_LOGE(GPIO_TAG, "GPIO_PIN mask error ");
         return ESP_ERR_INVALID_ARG;
     }
+#if CONFIG_IDF_TARGET_ESP32
     if ((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) {
         //GPIO 34/35/36/37/38/39 can only be used as input mode;
         if ((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) {
@@ -262,6 +285,12 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
             return ESP_ERR_INVALID_ARG;
         }
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    if ( (pGPIOConfig->mode & GPIO_MODE_DEF_OUTPUT) && (gpio_pin_mask & GPIO_SEL_46) ) {
+        ESP_LOGE(GPIO_TAG, "GPIO46 can only be used as input mode");
+        return ESP_ERR_INVALID_ARG;
+    }
+#endif
     do {
         io_reg = GPIO_PIN_MUX_REG[io_num];
         if (((gpio_pin_mask >> io_num) & BIT(0))) {
@@ -456,12 +485,15 @@ esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t streng
 {
     GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
     GPIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG);
-
+#if CONFIG_IDF_TARGET_ESP32
     if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
         rtc_gpio_set_drive_capability(gpio_num, strength);
     } else {
         SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);
+#endif
     return ESP_OK;
 }
 
@@ -469,15 +501,19 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* stren
 {
     GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
     GPIO_CHECK(strength != NULL, "GPIO drive capability pointer error", ESP_ERR_INVALID_ARG);
-
+#if CONFIG_IDF_TARGET_ESP32
     if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
         return rtc_gpio_get_drive_capability(gpio_num, strength);
     } else {
         *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
+#endif
     return ESP_OK;
 }
 
+#if CONFIG_IDF_TARGET_ESP32
 static const uint32_t GPIO_HOLD_MASK[34] = {
     0,
     GPIO_SEL_1,
@@ -514,6 +550,7 @@ static const uint32_t GPIO_HOLD_MASK[34] = {
     0,
     0,
 };
+#endif
 
 esp_err_t gpio_hold_en(gpio_num_t gpio_num)
 {
@@ -521,15 +558,17 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num)
     esp_err_t r = ESP_OK;
     if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
         r = rtc_gpio_hold_en(gpio_num);
-    } else if (GPIO_HOLD_MASK[gpio_num]) {
 #if CONFIG_IDF_TARGET_ESP32
+    } else if (GPIO_HOLD_MASK[gpio_num]) {
         SET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
-#elif CONFIG_IDF_TARGET_ESP32S2BETA
-        SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
-#endif
     } else {
         r = ESP_ERR_NOT_SUPPORTED;
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    } else {
+        SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - RTC_GPIO_NUMBER));
+    }
+#endif
     return r == ESP_OK ? ESP_OK : ESP_ERR_NOT_SUPPORTED;
 }
 
@@ -539,15 +578,17 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num)
     esp_err_t r = ESP_OK;
     if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
         r = rtc_gpio_hold_dis(gpio_num);
-    } else if (GPIO_HOLD_MASK[gpio_num]) {
+#if CONFIG_IDF_TARGET_ESP32 
-#if CONFIG_IDF_TARGET_ESP32
+    }else if (GPIO_HOLD_MASK[gpio_num]) {
         CLEAR_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
-#elif CONFIG_IDF_TARGET_ESP32S2BETA
-        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
-#endif
     } else {
         r = ESP_ERR_NOT_SUPPORTED;
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - RTC_GPIO_NUMBER));
+    }
+#endif
     return r == ESP_OK ? ESP_OK : ESP_ERR_NOT_SUPPORTED;
 }
 
@@ -561,10 +602,35 @@ void gpio_deep_sleep_hold_en(void)
 void gpio_deep_sleep_hold_dis(void)
 {
     portENTER_CRITICAL(&gpio_spinlock);
+#if CONFIG_IDF_TARGET_ESP32
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
+#endif
     portEXIT_CRITICAL(&gpio_spinlock);
 }
 
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+
+esp_err_t gpio_force_hold_all()
+{
+    rtc_gpio_force_hold_all();
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
+    return ESP_OK;
+}
+
+esp_err_t gpio_force_unhold_all()
+{
+    rtc_gpio_force_hold_dis_all();
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
+    return ESP_OK;
+}
+
+#endif
+
 void gpio_iomux_in(uint32_t gpio, uint32_t signal_idx)
 {
     GPIO.func_in_sel_cfg[signal_idx].sig_in_sel = 0;

components/driver/include/driver/gpio.h

@@ -32,6 +32,7 @@
 extern "C" {
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32
 #define GPIO_SEL_0              (BIT(0))                         /*!< Pin 0 selected */
 #define GPIO_SEL_1              (BIT(1))                         /*!< Pin 1 selected */
 #define GPIO_SEL_2              (BIT(2))                         /*!< Pin 2 selected
@@ -76,6 +77,53 @@ extern "C" {
 #define GPIO_SEL_38             ((uint64_t)(((uint64_t)1)<<38))  /*!< Pin 38 selected */
 #define GPIO_SEL_39             ((uint64_t)(((uint64_t)1)<<39))  /*!< Pin 39 selected */
 
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#define GPIO_SEL_0              (BIT(0))                         /*!< Pin 0 selected */
+#define GPIO_SEL_1              (BIT(1))                         /*!< Pin 1 selected */
+#define GPIO_SEL_2              (BIT(2))                         /*!< Pin 2 selected */
+#define GPIO_SEL_3              (BIT(3))                         /*!< Pin 3 selected */
+#define GPIO_SEL_4              (BIT(4))                         /*!< Pin 4 selected */
+#define GPIO_SEL_5              (BIT(5))                         /*!< Pin 5 selected */
+#define GPIO_SEL_6              (BIT(6))                         /*!< Pin 6 selected */
+#define GPIO_SEL_7              (BIT(7))                         /*!< Pin 7 selected */
+#define GPIO_SEL_8              (BIT(8))                         /*!< Pin 8 selected */
+#define GPIO_SEL_9              (BIT(9))                         /*!< Pin 9 selected */
+#define GPIO_SEL_10             (BIT(10))                        /*!< Pin 10 selected */
+#define GPIO_SEL_11             (BIT(11))                        /*!< Pin 11 selected */
+#define GPIO_SEL_12             (BIT(12))                        /*!< Pin 12 selected */
+#define GPIO_SEL_13             (BIT(13))                        /*!< Pin 13 selected */
+#define GPIO_SEL_14             (BIT(14))                        /*!< Pin 14 selected */
+#define GPIO_SEL_15             (BIT(15))                        /*!< Pin 15 selected */
+#define GPIO_SEL_16             (BIT(16))                        /*!< Pin 16 selected */
+#define GPIO_SEL_17             (BIT(17))                        /*!< Pin 17 selected */
+#define GPIO_SEL_18             (BIT(18))                        /*!< Pin 18 selected */
+#define GPIO_SEL_19             (BIT(19))                        /*!< Pin 19 selected */
+#define GPIO_SEL_20             (BIT(20))                        /*!< Pin 20 selected */
+#define GPIO_SEL_21             (BIT(21))                        /*!< Pin 21 selected */
+
+#define GPIO_SEL_26             (BIT(26))                        /*!< Pin 26 selected */
+#define GPIO_SEL_27             (BIT(27))                        /*!< Pin 27 selected */
+#define GPIO_SEL_28             (BIT(28))                        /*!< Pin 28 selected */
+#define GPIO_SEL_29             (BIT(29))                        /*!< Pin 29 selected */
+#define GPIO_SEL_30             (BIT(30))                        /*!< Pin 30 selected */
+#define GPIO_SEL_31             (BIT(31))                        /*!< Pin 31 selected */
+#define GPIO_SEL_32             ((uint64_t)(((uint64_t)1)<<32))  /*!< Pin 32 selected */
+#define GPIO_SEL_33             ((uint64_t)(((uint64_t)1)<<33))  /*!< Pin 33 selected */
+#define GPIO_SEL_34             ((uint64_t)(((uint64_t)1)<<34))  /*!< Pin 34 selected */
+#define GPIO_SEL_35             ((uint64_t)(((uint64_t)1)<<35))  /*!< Pin 35 selected */
+#define GPIO_SEL_36             ((uint64_t)(((uint64_t)1)<<36))  /*!< Pin 36 selected */
+#define GPIO_SEL_37             ((uint64_t)(((uint64_t)1)<<37))  /*!< Pin 37 selected */
+#define GPIO_SEL_38             ((uint64_t)(((uint64_t)1)<<38))  /*!< Pin 38 selected */
+#define GPIO_SEL_39             ((uint64_t)(((uint64_t)1)<<39))  /*!< Pin 39 selected */
+#define GPIO_SEL_40             ((uint64_t)(((uint64_t)1)<<40))  /*!< Pin 40 selected */
+#define GPIO_SEL_41             ((uint64_t)(((uint64_t)1)<<41))  /*!< Pin 41 selected */
+#define GPIO_SEL_42             ((uint64_t)(((uint64_t)1)<<42))  /*!< Pin 42 selected */
+#define GPIO_SEL_43             ((uint64_t)(((uint64_t)1)<<43))  /*!< Pin 43 selected */
+#define GPIO_SEL_44             ((uint64_t)(((uint64_t)1)<<44))  /*!< Pin 44 selected */
+#define GPIO_SEL_45             ((uint64_t)(((uint64_t)1)<<45))  /*!< Pin 45 selected */
+#define GPIO_SEL_46             ((uint64_t)(((uint64_t)1)<<46))  /*!< Pin 46 selected */
+#endif
+
 #if CONFIG_IDF_TARGET_ESP32
 #define GPIO_PIN_REG_0          IO_MUX_GPIO0_REG
 #define GPIO_PIN_REG_1          IO_MUX_GPIO1_REG
@@ -163,11 +211,16 @@ extern "C" {
 #define GPIO_PIN_REG_47          IO_MUX_GPIO47_REG
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32
 #define GPIO_APP_CPU_INTR_ENA      (BIT(0))
 #define GPIO_APP_CPU_NMI_INTR_ENA  (BIT(1))
 #define GPIO_PRO_CPU_INTR_ENA      (BIT(2))
 #define GPIO_PRO_CPU_NMI_INTR_ENA  (BIT(3))
 #define GPIO_SDIO_EXT_INTR_ENA     (BIT(4))
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#define GPIO_PRO_CPU_INTR_ENA      (BIT(0))
+#define GPIO_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+#endif
 
 #define GPIO_MODE_DEF_DISABLE         (0)
 #define GPIO_MODE_DEF_INPUT           (BIT0)
@@ -184,6 +237,7 @@ extern "C" {
 #define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)      ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46))         /*!< Check whether it can be a valid GPIO number of output mode */
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32
 typedef enum {
     GPIO_NUM_NC = -1,    /*!< Use to signal not connected to S/W */
     GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
@@ -228,22 +282,60 @@ typedef enum {
     GPIO_NUM_37 = 37,   /*!< GPIO37, input mode only */
     GPIO_NUM_38 = 38,   /*!< GPIO38, input mode only */
     GPIO_NUM_39 = 39,   /*!< GPIO39, input mode only */
-#if CONFIG_IDF_TARGET_ESP32
     GPIO_NUM_MAX = 40,
-#elif CONFIG_IDF_TARGET_ESP32S2BETA
-    GPIO_NUM_40 = 40,   /*!< GPIO40, input mode only */
-    GPIO_NUM_41 = 41,   /*!< GPIO41, input mode only */
-    GPIO_NUM_42 = 42,   /*!< GPIO42, input mode only */
-    GPIO_NUM_43 = 43,   /*!< GPIO43, input mode only */
-    GPIO_NUM_44 = 44,   /*!< GPIO44, input mode only */
-    GPIO_NUM_45 = 45,   /*!< GPIO45, input mode only */
-    GPIO_NUM_46 = 46,   /*!< GPIO46, input mode only */
-    GPIO_NUM_47 = 47,   /*!< GPIO47, input mode only */
-    GPIO_NUM_MAX = 48,
-#endif
 /** @endcond */
 } gpio_num_t;
 
+
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+typedef enum {
+    GPIO_NUM_NC = -1,    /*!< Use to signal not connected to S/W */
+    GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
+    GPIO_NUM_1 = 1,     /*!< GPIO1, input and output */
+    GPIO_NUM_2 = 2,     /*!< GPIO2, input and output */
+    GPIO_NUM_3 = 3,     /*!< GPIO3, input and output */
+    GPIO_NUM_4 = 4,     /*!< GPIO4, input and output */
+    GPIO_NUM_5 = 5,     /*!< GPIO5, input and output */
+    GPIO_NUM_6 = 6,     /*!< GPIO6, input and output */
+    GPIO_NUM_7 = 7,     /*!< GPIO7, input and output */
+    GPIO_NUM_8 = 8,     /*!< GPIO8, input and output */
+    GPIO_NUM_9 = 9,     /*!< GPIO9, input and output */
+    GPIO_NUM_10 = 10,   /*!< GPIO10, input and output */
+    GPIO_NUM_11 = 11,   /*!< GPIO11, input and output */
+    GPIO_NUM_12 = 12,   /*!< GPIO12, input and output */
+    GPIO_NUM_13 = 13,   /*!< GPIO13, input and output */
+    GPIO_NUM_14 = 14,   /*!< GPIO14, input and output */
+    GPIO_NUM_15 = 15,   /*!< GPIO15, input and output */
+    GPIO_NUM_16 = 16,   /*!< GPIO16, input and output */
+    GPIO_NUM_17 = 17,   /*!< GPIO17, input and output */
+    GPIO_NUM_18 = 18,   /*!< GPIO18, input and output */
+    GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
+    GPIO_NUM_20 = 20,   /*!< GPIO20, input and output */
+    GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
+    /* Note: The missing IO is because it is used inside the chip. */
+    GPIO_NUM_26 = 26,   /*!< GPIO26, input and output */
+    GPIO_NUM_27 = 27,   /*!< GPIO27, input and output */
+    GPIO_NUM_28 = 28,   /*!< GPIO28, input and output */
+    GPIO_NUM_32 = 32,   /*!< GPIO32, input and output */
+    GPIO_NUM_33 = 33,   /*!< GPIO33, input and output */
+    GPIO_NUM_34 = 34,   /*!< GPIO34, input and output */
+    GPIO_NUM_35 = 35,   /*!< GPIO35, input and output */
+    GPIO_NUM_36 = 36,   /*!< GPIO36, input and output */
+    GPIO_NUM_37 = 37,   /*!< GPIO37, input and output */
+    GPIO_NUM_38 = 38,   /*!< GPIO38, input and output */
+    GPIO_NUM_39 = 39,   /*!< GPIO39, input and output */
+    GPIO_NUM_40 = 40,   /*!< GPIO40, input and output */
+    GPIO_NUM_41 = 41,   /*!< GPIO41, input and output */
+    GPIO_NUM_42 = 42,   /*!< GPIO42, input and output */
+    GPIO_NUM_43 = 43,   /*!< GPIO43, input and output */
+    GPIO_NUM_44 = 44,   /*!< GPIO44, input and output */
+    GPIO_NUM_45 = 45,   /*!< GPIO45, input and output */
+    GPIO_NUM_46 = 46,   /*!< GPIO46, input mode only */
+    GPIO_NUM_MAX = 47,
+/** @endcond */
+} gpio_num_t;
+#endif
+
 typedef enum {
     GPIO_INTR_DISABLE = 0,     /*!< Disable GPIO interrupt                             */
     GPIO_INTR_POSEDGE = 1,     /*!< GPIO interrupt type : rising edge                  */
@@ -680,6 +772,20 @@ void gpio_iomux_in(uint32_t gpio_num, uint32_t signal_idx);
   */
 void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv);
 
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+/**
+  * @brief Force hold digital and rtc gpio pad. 
+  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. 
+  * */
+esp_err_t gpio_force_hold_all(void);
+
+/**
+  * @brief Force unhold digital and rtc gpio pad. 
+  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. 
+  * */
+esp_err_t gpio_force_unhold_all(void);
+#endif
+
 #ifdef __cplusplus
 }
 #endif

components/driver/include/driver/rtc_io.h

@@ -24,12 +24,19 @@ extern "C" {
 #endif
 
 typedef enum {
-    RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad input */
+    RTC_GPIO_MODE_INPUT_ONLY ,  /*!< Pad input */
-    RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad output */
+    RTC_GPIO_MODE_OUTPUT_ONLY,  /*!< Pad output */
     RTC_GPIO_MODE_INPUT_OUTPUT, /*!< Pad pull input + output */
-    RTC_GPIO_MODE_DISABLED,    /*!< Pad (output + input) disable */
+    RTC_GPIO_MODE_DISABLED,     /*!< Pad (output + input) disable */
 } rtc_gpio_mode_t;
 
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+typedef enum {
+    RTCIO_MODE_OUTPUT = 0,      /*!< Pad output normal mode */
+    RTCIO_MODE_OUTPUT_OD = 1,   /*!< Pad output OD mode */
+} rtc_io_out_mode_t;
+#endif
+
 /**
  * @brief Determine if the specified GPIO is a valid RTC GPIO.
  *
@@ -38,8 +45,12 @@ typedef enum {
  */
 inline static bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num)
 {
+#if CONFIG_IDF_TARGET_ESP32
     return gpio_num < GPIO_PIN_COUNT
         && rtc_gpio_desc[gpio_num].reg != 0;
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    return (gpio_num < RTC_GPIO_NUMBER);
+#endif
 }
 
 #define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num) // Deprecated, use rtc_gpio_is_valid_gpio()
@@ -266,7 +277,71 @@ esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
  */
 esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num);
 
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+/**
+ * @brief  RTC IO set output mode
+ * @param  gpio_num  Configure GPIO pins number
+ * @param  mode GPIO output mode
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ *
+ */
+esp_err_t rtc_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode);
 
+/**
+ * @brief  RTC IO get output mode
+ * @param  gpio_num  Configure GPIO pins number
+ * @param  mode GPIO output mode
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ */
+esp_err_t rtc_gpio_get_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t *mode);
+
+/**
+ * @brief  Set RTC IO status in deep sleep
+ *         In some application scenarios, IO needs to have another states during deep sleep.
+ * @param  gpio_num  Configure GPIO pins number
+ * @param  input input mode. false: close; true: open;
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ */
+esp_err_t rtc_gpio_sleep_input_enable(gpio_num_t gpio_num, bool input);
+
+/**
+ * @brief  Set RTC IO status in deep sleep
+ *         In some application scenarios, IO needs to have another states during deep sleep.
+ * @param  gpio_num  Configure GPIO pins number
+ * @param  output output mode. false: close; true: open;
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ */
+esp_err_t rtc_gpio_sleep_output_enable(gpio_num_t gpio_num, bool output);
+
+/**
+ * @brief  Close RTC IO status in deep sleep
+ *         In some application scenarios, IO needs to have another states during deep sleep.
+ * @param  gpio_num  Configure GPIO pins number
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ */
+esp_err_t rtc_gpio_sleep_mode_disable(gpio_num_t gpio_num);
+
+/**
+ * @brief Enable force hold signal for all RTC IOs
+ *
+ * Each RTC pad has a "force hold" input signal from the RTC controller.
+ * If this signal is set, pad latches current values of input enable,
+ * function, output enable, and other signals which come from the RTC mux.
+ * Force hold signal is enabled before going into deep sleep for pins which
+ * are used for EXT1 wakeup.
+ */
+esp_err_t rtc_gpio_force_hold_all();
+#endif
 
 #ifdef __cplusplus
 }

components/driver/rtc_module.c

@@ -142,10 +142,15 @@ esp_err_t rtc_gpio_init(gpio_num_t gpio_num)
 {
     RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
     portENTER_CRITICAL(&rtc_spinlock);
+#if CONFIG_IDF_TARGET_ESP32
     // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
     SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, (rtc_gpio_desc[gpio_num].mux));
     //0:RTC FUNCIOTN 1,2,3:Reserved
     SET_PERI_REG_BITS(rtc_gpio_desc[gpio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, 0x0, rtc_gpio_desc[gpio_num].func);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    rtc_gpio_reg[gpio_num]->mux_sel = 0x1;
+    rtc_gpio_reg[gpio_num]->fun_sel = 0x0;
+#endif
     portEXIT_CRITICAL(&rtc_spinlock);
 
     return ESP_OK;
@@ -156,7 +161,11 @@ esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num)
     RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
     portENTER_CRITICAL(&rtc_spinlock);
     //Select Gpio as Digital Gpio
+#if CONFIG_IDF_TARGET_ESP32
     CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, (rtc_gpio_desc[gpio_num].mux));
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    rtc_gpio_reg[gpio_num]->mux_sel = 0x0;
+#endif
     portEXIT_CRITICAL(&rtc_spinlock);
 
     return ESP_OK;
@@ -167,8 +176,6 @@ static esp_err_t rtc_gpio_output_enable(gpio_num_t gpio_num)
     int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;
     RTC_MODULE_CHECK(rtc_gpio_num != -1, "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
     SET_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TS_REG, (1 << (rtc_gpio_num + RTC_GPIO_ENABLE_W1TS_S)));
-    CLEAR_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TC_REG, (1 << (rtc_gpio_num + RTC_GPIO_ENABLE_W1TC_S)));
-
     return ESP_OK;
 }
 
@@ -176,7 +183,6 @@ static esp_err_t rtc_gpio_output_disable(gpio_num_t gpio_num)
 {
     int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;
     RTC_MODULE_CHECK(rtc_gpio_num != -1, "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
-    CLEAR_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TS_REG, (1 << (rtc_gpio_num + RTC_GPIO_ENABLE_W1TS_S)));
     SET_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TC_REG, (1 << ( rtc_gpio_num + RTC_GPIO_ENABLE_W1TC_S)));
 
     return ESP_OK;
@@ -186,7 +192,11 @@ static esp_err_t rtc_gpio_input_enable(gpio_num_t gpio_num)
 {
     RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
     portENTER_CRITICAL(&rtc_spinlock);
+#if CONFIG_IDF_TARGET_ESP32
     SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].ie);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    rtc_gpio_reg[gpio_num]->fun_ie = 1;
+#endif
     portEXIT_CRITICAL(&rtc_spinlock);
 
     return ESP_OK;
@@ -196,12 +206,41 @@ static esp_err_t rtc_gpio_input_disable(gpio_num_t gpio_num)
 {
     RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
     portENTER_CRITICAL(&rtc_spinlock);
+#if CONFIG_IDF_TARGET_ESP32
     CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].ie);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    rtc_gpio_reg[gpio_num]->fun_ie = 0;
+#endif
     portEXIT_CRITICAL(&rtc_spinlock);
 
     return ESP_OK;
 }
 
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+esp_err_t rtc_gpio_sleep_output_enable(gpio_num_t gpio_num, bool output)
+{
+    RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    rtc_gpio_reg[gpio_num]->slp_sel = 1;
+    rtc_gpio_reg[gpio_num]->slp_oe = output;
+    return ESP_OK;
+}
+
+esp_err_t rtc_gpio_sleep_input_enable(gpio_num_t gpio_num, bool input)
+{
+    RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    rtc_gpio_reg[gpio_num]->slp_sel = 1;
+    rtc_gpio_reg[gpio_num]->slp_ie = input;
+    return ESP_OK;
+}
+
+esp_err_t rtc_gpio_sleep_mode_disable(gpio_num_t gpio_num)
+{
+    RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    rtc_gpio_reg[gpio_num]->slp_sel = 0;
+    return ESP_OK;
+}
+#endif
+
 esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level)
 {
     int rtc_gpio_num = rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;;
@@ -219,6 +258,7 @@ esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level)
 uint32_t rtc_gpio_get_level(gpio_num_t gpio_num)
 {
     uint32_t level = 0;
+#if CONFIG_IDF_TARGET_ESP32
     int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;
     RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
 
@@ -226,6 +266,13 @@ uint32_t rtc_gpio_get_level(gpio_num_t gpio_num)
     level = READ_PERI_REG(RTC_GPIO_IN_REG);
     portEXIT_CRITICAL(&rtc_spinlock);
     return ((level >> (RTC_GPIO_IN_NEXT_S + rtc_gpio_num)) & 0x01);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+    level = RTCIO.in_val.in;
+    portEXIT_CRITICAL(&rtc_spinlock);
+    return ((level >> gpio_num) & 0x1);
+#endif
 }
 
 esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength)
@@ -235,7 +282,11 @@ esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t st
     RTC_MODULE_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG);
 
     portENTER_CRITICAL(&rtc_spinlock);
+#if CONFIG_IDF_TARGET_ESP32
     SET_PERI_REG_BITS(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].drv_v, strength, rtc_gpio_desc[gpio_num].drv_s);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    rtc_gpio_reg[gpio_num]->drv = strength;
+#endif
     portEXIT_CRITICAL(&rtc_spinlock);
     return ESP_OK;
 }
@@ -245,8 +296,11 @@ esp_err_t rtc_gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* s
     RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
     RTC_MODULE_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Output pad only", ESP_ERR_INVALID_ARG);
     RTC_MODULE_CHECK(strength != NULL, "GPIO drive pointer error", ESP_ERR_INVALID_ARG);
-
+#if CONFIG_IDF_TARGET_ESP32
     *strength = GET_PERI_REG_BITS2(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].drv_v, rtc_gpio_desc[gpio_num].drv_s);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    *strength = rtc_gpio_reg[gpio_num]->drv;
+#endif
     return ESP_OK;
 }
 
@@ -278,21 +332,45 @@ esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode)
 
 esp_err_t rtc_gpio_pullup_en(gpio_num_t gpio_num)
 {
+#if CONFIG_IDF_TARGET_ESP32
     //this is a digital pad
     if (rtc_gpio_desc[gpio_num].pullup == 0) {
         return ESP_ERR_INVALID_ARG;
     }
-
+#endif
     //this is a rtc pad
     portENTER_CRITICAL(&rtc_spinlock);
+#if CONFIG_IDF_TARGET_ESP32
     SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pullup);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    rtc_gpio_reg[gpio_num]->rue = 0x1;
+#endif
     portEXIT_CRITICAL(&rtc_spinlock);
 
     return ESP_OK;
 }
 
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+esp_err_t rtc_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode)
+{
+    RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+    RTCIO.pin[gpio_num].pad_driver = mode;
+    portEXIT_CRITICAL(&rtc_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t rtc_gpio_get_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t *mode)
+{
+    RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    *mode = RTCIO.pin[gpio_num].pad_driver;
+    return ESP_OK;
+}
+#endif
+
 esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num)
 {
+#if CONFIG_IDF_TARGET_ESP32
     //this is a digital pad
     if (rtc_gpio_desc[gpio_num].pulldown == 0) {
         return ESP_ERR_INVALID_ARG;
@@ -302,12 +380,17 @@ esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num)
     portENTER_CRITICAL(&rtc_spinlock);
     SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pulldown);
     portEXIT_CRITICAL(&rtc_spinlock);
-
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    portENTER_CRITICAL(&rtc_spinlock);
+    rtc_gpio_reg[gpio_num]->rde = 0x1;
+    portEXIT_CRITICAL(&rtc_spinlock);
+#endif
     return ESP_OK;
 }
 
 esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num)
 {
+#if CONFIG_IDF_TARGET_ESP32
     //this is a digital pad
     if ( rtc_gpio_desc[gpio_num].pullup == 0 ) {
         return ESP_ERR_INVALID_ARG;
@@ -317,12 +400,17 @@ esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num)
     portENTER_CRITICAL(&rtc_spinlock);
     CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pullup);
     portEXIT_CRITICAL(&rtc_spinlock);
-
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    portENTER_CRITICAL(&rtc_spinlock);
+    rtc_gpio_reg[gpio_num]->rue = 0x0;
+    portEXIT_CRITICAL(&rtc_spinlock);
+#endif
     return ESP_OK;
 }
 
 esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num)
 {
+#if CONFIG_IDF_TARGET_ESP32
     //this is a digital pad
     if (rtc_gpio_desc[gpio_num].pulldown == 0) {
         return ESP_ERR_INVALID_ARG;
@@ -332,12 +420,17 @@ esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num)
     portENTER_CRITICAL(&rtc_spinlock);
     CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pulldown);
     portEXIT_CRITICAL(&rtc_spinlock);
-
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    portENTER_CRITICAL(&rtc_spinlock);
+    rtc_gpio_reg[gpio_num]->rde = 0x0;
+    portEXIT_CRITICAL(&rtc_spinlock);
+#endif
     return ESP_OK;
 }
 
 esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num)
 {
+#if CONFIG_IDF_TARGET_ESP32
     // check if an RTC IO
     if (rtc_gpio_desc[gpio_num].pullup == 0) {
         return ESP_ERR_INVALID_ARG;
@@ -345,11 +438,13 @@ esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num)
     portENTER_CRITICAL(&rtc_spinlock);
     SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].hold);
     portEXIT_CRITICAL(&rtc_spinlock);
+#endif
     return ESP_OK;
 }
 
 esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num)
 {
+#if CONFIG_IDF_TARGET_ESP32
     // check if an RTC IO
     if (rtc_gpio_desc[gpio_num].pullup == 0) {
         return ESP_ERR_INVALID_ARG;
@@ -357,6 +452,7 @@ esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num)
     portENTER_CRITICAL(&rtc_spinlock);
     CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].hold);
     portEXIT_CRITICAL(&rtc_spinlock);
+#endif
     return ESP_OK;
 }
 
@@ -376,18 +472,23 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num)
 
 void rtc_gpio_force_hold_dis_all()
 {
+#if CONFIG_IDF_TARGET_ESP32
     for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
         const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio];
         if (desc->hold_force != 0) {
-#if CONFIG_IDF_TARGET_ESP32
             REG_CLR_BIT(RTC_CNTL_HOLD_FORCE_REG, desc->hold_force);
-#endif
         }
     }
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    portENTER_CRITICAL(&rtc_spinlock);
+    RTCCNTL.rtc_pwc.rtc_pad_force_hold = 0;
+    portEXIT_CRITICAL(&rtc_spinlock);
+#endif
 }
 
 esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
+#if CONFIG_IDF_TARGET_ESP32
     int rtc_num = rtc_gpio_desc[gpio_num].rtc_num;
     if (rtc_num < 0) {
         return ESP_ERR_INVALID_ARG;
@@ -400,11 +501,21 @@ esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
     /* each pin has its own register, spinlock not needed */
     REG_SET_BIT(reg, RTC_GPIO_PIN0_WAKEUP_ENABLE);
     REG_SET_FIELD(reg, RTC_GPIO_PIN0_INT_TYPE, intr_type);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    if (( intr_type != GPIO_INTR_LOW_LEVEL ) && ( intr_type != GPIO_INTR_HIGH_LEVEL )) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    /* each pin has its own register, spinlock not needed */
+    RTCIO.pin[gpio_num].wakeup_enable = 1;
+    RTCIO.pin[gpio_num].int_type = intr_type;
+#endif
     return ESP_OK;
 }
 
 esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num)
 {
+#if CONFIG_IDF_TARGET_ESP32
     int rtc_num = rtc_gpio_desc[gpio_num].rtc_num;
     if (rtc_num < 0) {
         return ESP_ERR_INVALID_ARG;
@@ -414,9 +525,24 @@ esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num)
     /* each pin has its own register, spinlock not needed */
     REG_CLR_BIT(reg, RTC_GPIO_PIN0_WAKEUP_ENABLE);
     REG_SET_FIELD(reg, RTC_GPIO_PIN0_INT_TYPE, 0);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    /* each pin has its own register, spinlock not needed */
+    RTCIO.pin[gpio_num].wakeup_enable = 0;
+    RTCIO.pin[gpio_num].int_type = 0;
+#endif
     return ESP_OK;
 }
 
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+esp_err_t rtc_gpio_force_hold_all()
+{
+    portENTER_CRITICAL(&rtc_spinlock);
+    RTCCNTL.rtc_pwc.rtc_pad_force_hold = 1;
+    portEXIT_CRITICAL(&rtc_spinlock);
+    return ESP_OK;
+}
+#endif
 
 /*---------------------------------------------------------------
                     Touch Pad
@@ -1739,7 +1865,9 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int*
 
 esp_err_t adc2_vref_to_gpio(gpio_num_t gpio)
 {
+#if CONFIG_IDF_TARGET_ESP32
     int channel;
+
     if(gpio == GPIO_NUM_25){
         channel = 8;    //Channel 8 bit
     }else if (gpio == GPIO_NUM_26){
@@ -1770,7 +1898,7 @@ esp_err_t adc2_vref_to_gpio(gpio_num_t gpio)
     SENS.sar_meas_start2.sar2_en_pad_force = 1;      //Pad bitmap controlled by SW
     //set en_pad for channels 7,8,9 (bits 0x380)
     SENS.sar_meas_start2.sar2_en_pad = 1<<channel;
-
+#endif
     return ESP_OK;
 }
 

components/soc/esp32s2beta/include/soc/gpio_struct.h

@@ -151,23 +151,14 @@ typedef volatile struct {
         };
         uint32_t val;
     } pin[54];
+    uint32_t status_next;                             /**/
     union {
         struct {
-            uint32_t rtc_max:     10;
+            uint32_t intr_st_next:         22;
-            uint32_t reserved10:  21;
+            uint32_t reserved22:           10;
-            uint32_t start:        1;
         };
         uint32_t val;
-    } cali_conf;
+    } status_next1;
-    union {
-        struct {
-            uint32_t value_sync2:     20;
-            uint32_t reserved20:      10;
-            uint32_t rdy_real:         1;
-            uint32_t rdy_sync2:        1;
-        };
-        uint32_t val;
-    } cali_data;
     union {
         struct {
             uint32_t func_sel:         6;
@@ -187,6 +178,71 @@ typedef volatile struct {
         };
         uint32_t val;
     } func_out_sel_cfg[54];
+    union {
+        struct {
+            uint32_t clk_en:     1;
+            uint32_t reserved1: 31;
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    union {
+        struct {
+            uint32_t date:      28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
 } gpio_dev_t;
 extern gpio_dev_t GPIO;
 #ifdef __cplusplus

components/soc/esp32s2beta/include/soc/rtc_gpio_channel.h

@@ -13,61 +13,75 @@
 // limitations under the License.
 
 #ifndef _SOC_RTC_GPIO_CHANNEL_H
-#define _SOC_RTC_GPIO_CHANNEL_H
+#define _SOC_RTC_GPIO_CHANNEL_H        
+
+#define RTC_GPIO_NUMBER             22
 
 //RTC GPIO channels
-#define RTCIO_GPIO36_CHANNEL        0   //RTCIO_CHANNEL_0
+#define RTCIO_GPIO0_CHANNEL         0   //RTCIO_CHANNEL_0
-#define RTCIO_CHANNEL_0_GPIO_NUM    36
+#define RTCIO_CHANNEL_0_GPIO_NUM    0
 
-#define RTCIO_GPIO37_CHANNEL        1   //RTCIO_CHANNEL_1
+#define RTCIO_GPIO1_CHANNEL         1   //RTCIO_CHANNEL_1
-#define RTCIO_CHANNEL_1_GPIO_NUM    37
+#define RTCIO_CHANNEL_1_GPIO_NUM    1
 
-#define RTCIO_GPIO38_CHANNEL        2   //RTCIO_CHANNEL_2
+#define RTCIO_GPIO2_CHANNEL         2   //RTCIO_CHANNEL_2
-#define RTCIO_CHANNEL_2_GPIO_NUM    38
+#define RTCIO_CHANNEL_2_GPIO_NUM    2
 
-#define RTCIO_GPIO39_CHANNEL        3   //RTCIO_CHANNEL_3
+#define RTCIO_GPIO3_CHANNEL         3   //RTCIO_CHANNEL_3
-#define RTCIO_CHANNEL_3_GPIO_NUM    39
+#define RTCIO_CHANNEL_3_GPIO_NUM    3
 
-#define RTCIO_GPIO34_CHANNEL        4   //RTCIO_CHANNEL_4
+#define RTCIO_GPIO4_CHANNEL         4   //RTCIO_CHANNEL_4
-#define RTCIO_CHANNEL_4_GPIO_NUM    34
+#define RTCIO_CHANNEL_4_GPIO_NUM    4
 
-#define RTCIO_GPIO35_CHANNEL        5   //RTCIO_CHANNEL_5
+#define RTCIO_GPIO5_CHANNEL         5   //RTCIO_CHANNEL_5
-#define RTCIO_CHANNEL_5_GPIO_NUM    35
+#define RTCIO_CHANNEL_5_GPIO_NUM    5
 
-#define RTCIO_GPIO25_CHANNEL        6   //RTCIO_CHANNEL_6
+#define RTCIO_GPIO6_CHANNEL         6   //RTCIO_CHANNEL_6
-#define RTCIO_CHANNEL_6_GPIO_NUM    25
+#define RTCIO_CHANNEL_6_GPIO_NUM    6
 
-#define RTCIO_GPIO26_CHANNEL        7   //RTCIO_CHANNEL_7
+#define RTCIO_GPIO7_CHANNEL         7   //RTCIO_CHANNEL_7
-#define RTCIO_CHANNEL_7_GPIO_NUM    26
+#define RTCIO_CHANNEL_7_GPIO_NUM    7
 
-#define RTCIO_GPIO33_CHANNEL        8   //RTCIO_CHANNEL_8
+#define RTCIO_GPIO8_CHANNEL         8   //RTCIO_CHANNEL_8
-#define RTCIO_CHANNEL_8_GPIO_NUM    33
+#define RTCIO_CHANNEL_8_GPIO_NUM    8
 
-#define RTCIO_GPIO32_CHANNEL        9   //RTCIO_CHANNEL_9
+#define RTCIO_GPIO9_CHANNEL         9   //RTCIO_CHANNEL_9
-#define RTCIO_CHANNEL_9_GPIO_NUM    32
+#define RTCIO_CHANNEL_9_GPIO_NUM    9
 
-#define RTCIO_GPIO4_CHANNEL         10   //RTCIO_CHANNEL_10
+#define RTCIO_GPIO10_CHANNEL        10   //RTCIO_CHANNEL_10
-#define RTCIO_CHANNEL_10_GPIO_NUM   4
+#define RTCIO_CHANNEL_10_GPIO_NUM   10
 
-#define RTCIO_GPIO0_CHANNEL         11   //RTCIO_CHANNEL_11
+#define RTCIO_GPIO11_CHANNEL        11   //RTCIO_CHANNEL_11
-#define RTCIO_CHANNEL_11_GPIO_NUM   0
+#define RTCIO_CHANNEL_11_GPIO_NUM   11
 
-#define RTCIO_GPIO2_CHANNEL         12   //RTCIO_CHANNEL_12
+#define RTCIO_GPIO12_CHANNEL        12   //RTCIO_CHANNEL_12
-#define RTCIO_CHANNEL_12_GPIO_NUM   2
+#define RTCIO_CHANNEL_12_GPIO_NUM   12
 
-#define RTCIO_GPIO15_CHANNEL        13   //RTCIO_CHANNEL_13
+#define RTCIO_GPIO13_CHANNEL        13   //RTCIO_CHANNEL_13
-#define RTCIO_CHANNEL_13_GPIO_NUM   15
+#define RTCIO_CHANNEL_13_GPIO_NUM   13
 
-#define RTCIO_GPIO13_CHANNEL        14   //RTCIO_CHANNEL_14
+#define RTCIO_GPIO14_CHANNEL        14   //RTCIO_CHANNEL_14
-#define RTCIO_CHANNEL_14_GPIO_NUM   13
+#define RTCIO_CHANNEL_14_GPIO_NUM   14
 
-#define RTCIO_GPIO12_CHANNEL        15   //RTCIO_CHANNEL_15
+#define RTCIO_GPIO15_CHANNEL        15   //RTCIO_CHANNEL_15
-#define RTCIO_CHANNEL_15_GPIO_NUM   12
+#define RTCIO_CHANNEL_15_GPIO_NUM   15
 
-#define RTCIO_GPIO14_CHANNEL        16   //RTCIO_CHANNEL_16
+#define RTCIO_GPIO16_CHANNEL        16   //RTCIO_CHANNEL_16
-#define RTCIO_CHANNEL_16_GPIO_NUM   14
+#define RTCIO_CHANNEL_16_GPIO_NUM   16
 
-#define RTCIO_GPIO27_CHANNEL        17   //RTCIO_CHANNEL_17
+#define RTCIO_GPIO17_CHANNEL        17   //RTCIO_CHANNEL_17
-#define RTCIO_CHANNEL_17_GPIO_NUM   27
+#define RTCIO_CHANNEL_17_GPIO_NUM   17
+
+#define RTCIO_GPIO18_CHANNEL        18   //RTCIO_CHANNEL_18
+#define RTCIO_CHANNEL_18_GPIO_NUM   18
+
+#define RTCIO_GPIO19_CHANNEL        19   //RTCIO_CHANNEL_19
+#define RTCIO_CHANNEL_19_GPIO_NUM   19
+
+#define RTCIO_GPIO20_CHANNEL        20   //RTCIO_CHANNEL_20
+#define RTCIO_CHANNEL_20_GPIO_NUM   20
+
+#define RTCIO_GPIO21_CHANNEL        21   //RTCIO_CHANNEL_21
+#define RTCIO_CHANNEL_21_GPIO_NUM   21
 
 #endif

components/soc/esp32s2beta/include/soc/rtc_io_reg.h

@@ -27,7 +27,7 @@ extern "C" {
 #define RTC_GPIO_OUT_DATA_V  0x3FFFFF
 #define RTC_GPIO_OUT_DATA_S  10
 
-#define RTC_GPIO_OUT_W1TS_REG          (DR_REG_RTCIO_BASE + 0x10)
+#define RTC_GPIO_OUT_W1TS_REG          (DR_REG_RTCIO_BASE + 0x4)
 /* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */
 /*description: RTC GPIO 0 ~ 21 output data write 1 to set*/
 #define RTC_GPIO_OUT_DATA_W1TS  0x003FFFFF
@@ -35,7 +35,7 @@ extern "C" {
 #define RTC_GPIO_OUT_DATA_W1TS_V  0x3FFFFF
 #define RTC_GPIO_OUT_DATA_W1TS_S  10
 
-#define RTC_GPIO_OUT_W1TC_REG          (DR_REG_RTCIO_BASE + 0x20)
+#define RTC_GPIO_OUT_W1TC_REG          (DR_REG_RTCIO_BASE + 0x8)
 /* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */
 /*description: RTC GPIO 0 ~ 21 output data write 1 to clear*/
 #define RTC_GPIO_OUT_DATA_W1TC  0x003FFFFF
@@ -43,7 +43,7 @@ extern "C" {
 #define RTC_GPIO_OUT_DATA_W1TC_V  0x3FFFFF
 #define RTC_GPIO_OUT_DATA_W1TC_S  10
 
-#define RTC_GPIO_ENABLE_REG          (DR_REG_RTCIO_BASE + 0x30)
+#define RTC_GPIO_ENABLE_REG          (DR_REG_RTCIO_BASE + 0xC)
 /* RTC_GPIO_ENABLE : R/W ;bitpos:[31:10] ;default: 0 ; */
 /*description: RTC GPIO 0 ~ 21 enable*/
 #define RTC_GPIO_ENABLE  0x003FFFFF
@@ -51,7 +51,7 @@ extern "C" {
 #define RTC_GPIO_ENABLE_V  0x3FFFFF
 #define RTC_GPIO_ENABLE_S  10
 
-#define RTC_GPIO_ENABLE_W1TS_REG          (DR_REG_RTCIO_BASE + 0x40)
+#define RTC_GPIO_ENABLE_W1TS_REG          (DR_REG_RTCIO_BASE + 0x10)
 /* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */
 /*description: RTC GPIO 0 ~ 21 enable write 1 to set*/
 #define RTC_GPIO_ENABLE_W1TS  0x003FFFFF
@@ -59,7 +59,7 @@ extern "C" {
 #define RTC_GPIO_ENABLE_W1TS_V  0x3FFFFF
 #define RTC_GPIO_ENABLE_W1TS_S  10
 
-#define RTC_GPIO_ENABLE_W1TC_REG          (DR_REG_RTCIO_BASE + 0x50)
+#define RTC_GPIO_ENABLE_W1TC_REG          (DR_REG_RTCIO_BASE + 0x14)
 /* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */
 /*description: RTC GPIO 0 ~ 21 enable write 1 to clear*/
 #define RTC_GPIO_ENABLE_W1TC  0x003FFFFF
@@ -67,7 +67,7 @@ extern "C" {
 #define RTC_GPIO_ENABLE_W1TC_V  0x3FFFFF
 #define RTC_GPIO_ENABLE_W1TC_S  10
 
-#define RTC_GPIO_STATUS_REG          (DR_REG_RTCIO_BASE + 0x60)
+#define RTC_GPIO_STATUS_REG          (DR_REG_RTCIO_BASE + 0x18)
 /* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:10] ;default: 0 ; */
 /*description: RTC GPIO 0 ~ 21 interrupt status*/
 #define RTC_GPIO_STATUS_INT  0x003FFFFF
@@ -75,7 +75,7 @@ extern "C" {
 #define RTC_GPIO_STATUS_INT_V  0x3FFFFF
 #define RTC_GPIO_STATUS_INT_S  10
 
-#define RTC_GPIO_STATUS_W1TS_REG          (DR_REG_RTCIO_BASE + 0x70)
+#define RTC_GPIO_STATUS_W1TS_REG          (DR_REG_RTCIO_BASE + 0x1C)
 /* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */
 /*description: RTC GPIO 0 ~ 21 interrupt status write 1 to set*/
 #define RTC_GPIO_STATUS_INT_W1TS  0x003FFFFF
@@ -83,7 +83,7 @@ extern "C" {
 #define RTC_GPIO_STATUS_INT_W1TS_V  0x3FFFFF
 #define RTC_GPIO_STATUS_INT_W1TS_S  10
 
-#define RTC_GPIO_STATUS_W1TC_REG          (DR_REG_RTCIO_BASE + 0x80)
+#define RTC_GPIO_STATUS_W1TC_REG          (DR_REG_RTCIO_BASE + 0x20)
 /* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */
 /*description: RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/
 #define RTC_GPIO_STATUS_INT_W1TC  0x003FFFFF
@@ -91,7 +91,7 @@ extern "C" {
 #define RTC_GPIO_STATUS_INT_W1TC_V  0x3FFFFF
 #define RTC_GPIO_STATUS_INT_W1TC_S  10
 
-#define RTC_GPIO_IN_REG          (DR_REG_RTCIO_BASE + 0x90)
+#define RTC_GPIO_IN_REG          (DR_REG_RTCIO_BASE + 0x24)
 /* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:10] ;default:  ; */
 /*description: RTC GPIO input data*/
 #define RTC_GPIO_IN_NEXT  0x003FFFFF
@@ -99,7 +99,7 @@ extern "C" {
 #define RTC_GPIO_IN_NEXT_V  0x3FFFFF
 #define RTC_GPIO_IN_NEXT_S  10
 
-#define RTC_GPIO_PIN0_REG          (DR_REG_RTCIO_BASE + 0xa0)
+#define RTC_GPIO_PIN0_REG          (DR_REG_RTCIO_BASE + 0x28)
 /* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))
@@ -120,7 +120,7 @@ extern "C" {
 #define RTC_GPIO_PIN0_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN0_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN1_REG          (DR_REG_RTCIO_BASE + 0xb0)
+#define RTC_GPIO_PIN1_REG          (DR_REG_RTCIO_BASE + 0x2C)
 /* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))
@@ -141,7 +141,7 @@ extern "C" {
 #define RTC_GPIO_PIN1_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN1_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN2_REG          (DR_REG_RTCIO_BASE + 0xc0)
+#define RTC_GPIO_PIN2_REG          (DR_REG_RTCIO_BASE + 0x30)
 /* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))
@@ -162,7 +162,7 @@ extern "C" {
 #define RTC_GPIO_PIN2_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN2_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN3_REG          (DR_REG_RTCIO_BASE + 0xd0)
+#define RTC_GPIO_PIN3_REG          (DR_REG_RTCIO_BASE + 0x34)
 /* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))
@@ -183,7 +183,7 @@ extern "C" {
 #define RTC_GPIO_PIN3_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN3_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN4_REG          (DR_REG_RTCIO_BASE + 0xe0)
+#define RTC_GPIO_PIN4_REG          (DR_REG_RTCIO_BASE + 0x38)
 /* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))
@@ -204,7 +204,7 @@ extern "C" {
 #define RTC_GPIO_PIN4_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN4_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN5_REG          (DR_REG_RTCIO_BASE + 0xf0)
+#define RTC_GPIO_PIN5_REG          (DR_REG_RTCIO_BASE + 0x3C)
 /* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))
@@ -225,7 +225,7 @@ extern "C" {
 #define RTC_GPIO_PIN5_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN5_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN6_REG          (DR_REG_RTCIO_BASE + 0x100)
+#define RTC_GPIO_PIN6_REG          (DR_REG_RTCIO_BASE + 0x40)
 /* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))
@@ -246,7 +246,7 @@ extern "C" {
 #define RTC_GPIO_PIN6_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN6_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN7_REG          (DR_REG_RTCIO_BASE + 0x110)
+#define RTC_GPIO_PIN7_REG          (DR_REG_RTCIO_BASE + 0x44)
 /* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))
@@ -267,7 +267,7 @@ extern "C" {
 #define RTC_GPIO_PIN7_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN7_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN8_REG          (DR_REG_RTCIO_BASE + 0x120)
+#define RTC_GPIO_PIN8_REG          (DR_REG_RTCIO_BASE + 0x48)
 /* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))
@@ -288,7 +288,7 @@ extern "C" {
 #define RTC_GPIO_PIN8_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN8_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN9_REG          (DR_REG_RTCIO_BASE + 0x130)
+#define RTC_GPIO_PIN9_REG          (DR_REG_RTCIO_BASE + 0x4C)
 /* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))
@@ -309,7 +309,7 @@ extern "C" {
 #define RTC_GPIO_PIN9_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN9_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN10_REG          (DR_REG_RTCIO_BASE + 0x140)
+#define RTC_GPIO_PIN10_REG          (DR_REG_RTCIO_BASE + 0x50)
 /* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))
@@ -330,7 +330,7 @@ extern "C" {
 #define RTC_GPIO_PIN10_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN10_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN11_REG          (DR_REG_RTCIO_BASE + 0x150)
+#define RTC_GPIO_PIN11_REG          (DR_REG_RTCIO_BASE + 0x54)
 /* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))
@@ -351,7 +351,7 @@ extern "C" {
 #define RTC_GPIO_PIN11_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN11_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN12_REG          (DR_REG_RTCIO_BASE + 0x160)
+#define RTC_GPIO_PIN12_REG          (DR_REG_RTCIO_BASE + 0x58)
 /* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))
@@ -372,7 +372,7 @@ extern "C" {
 #define RTC_GPIO_PIN12_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN12_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN13_REG          (DR_REG_RTCIO_BASE + 0x170)
+#define RTC_GPIO_PIN13_REG          (DR_REG_RTCIO_BASE + 0x5C)
 /* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))
@@ -393,7 +393,7 @@ extern "C" {
 #define RTC_GPIO_PIN13_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN13_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN14_REG          (DR_REG_RTCIO_BASE + 0x180)
+#define RTC_GPIO_PIN14_REG          (DR_REG_RTCIO_BASE + 0x60)
 /* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))
@@ -414,7 +414,7 @@ extern "C" {
 #define RTC_GPIO_PIN14_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN14_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN15_REG          (DR_REG_RTCIO_BASE + 0x190)
+#define RTC_GPIO_PIN15_REG          (DR_REG_RTCIO_BASE + 0x64)
 /* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))
@@ -435,7 +435,7 @@ extern "C" {
 #define RTC_GPIO_PIN15_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN15_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN16_REG          (DR_REG_RTCIO_BASE + 0x1a0)
+#define RTC_GPIO_PIN16_REG          (DR_REG_RTCIO_BASE + 0x68)
 /* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))
@@ -456,7 +456,7 @@ extern "C" {
 #define RTC_GPIO_PIN16_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN16_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN17_REG          (DR_REG_RTCIO_BASE + 0x1b0)
+#define RTC_GPIO_PIN17_REG          (DR_REG_RTCIO_BASE + 0x6C)
 /* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))
@@ -477,7 +477,7 @@ extern "C" {
 #define RTC_GPIO_PIN17_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN17_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN18_REG          (DR_REG_RTCIO_BASE + 0x1c0)
+#define RTC_GPIO_PIN18_REG          (DR_REG_RTCIO_BASE + 0x70)
 /* RTC_GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN18_WAKEUP_ENABLE  (BIT(10))
@@ -498,7 +498,7 @@ extern "C" {
 #define RTC_GPIO_PIN18_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN18_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN19_REG          (DR_REG_RTCIO_BASE + 0x1d0)
+#define RTC_GPIO_PIN19_REG          (DR_REG_RTCIO_BASE + 0x74)
 /* RTC_GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN19_WAKEUP_ENABLE  (BIT(10))
@@ -519,7 +519,7 @@ extern "C" {
 #define RTC_GPIO_PIN19_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN19_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN20_REG          (DR_REG_RTCIO_BASE + 0x1e0)
+#define RTC_GPIO_PIN20_REG          (DR_REG_RTCIO_BASE + 0x78)
 /* RTC_GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN20_WAKEUP_ENABLE  (BIT(10))
@@ -540,7 +540,7 @@ extern "C" {
 #define RTC_GPIO_PIN20_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN20_PAD_DRIVER_S  2
 
-#define RTC_GPIO_PIN21_REG          (DR_REG_RTCIO_BASE + 0x1f0)
+#define RTC_GPIO_PIN21_REG          (DR_REG_RTCIO_BASE + 0x7C)
 /* RTC_GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
 /*description: RTC GPIO wakeup enable bit*/
 #define RTC_GPIO_PIN21_WAKEUP_ENABLE  (BIT(10))
@@ -561,7 +561,7 @@ extern "C" {
 #define RTC_GPIO_PIN21_PAD_DRIVER_V  0x1
 #define RTC_GPIO_PIN21_PAD_DRIVER_S  2
 
-#define RTC_IO_RTC_DEBUG_SEL_REG          (DR_REG_RTCIO_BASE + 0x200)
+#define RTC_IO_RTC_DEBUG_SEL_REG          (DR_REG_RTCIO_BASE + 0x80)
 /* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */
 /*description: */
 #define RTC_IO_DEBUG_12M_NO_GATING  (BIT(25))
@@ -599,7 +599,7 @@ extern "C" {
 #define RTC_IO_DEBUG_SEL0_V  0x1F
 #define RTC_IO_DEBUG_SEL0_S  0
 
-#define RTC_IO_TOUCH_PAD0_REG          (DR_REG_RTCIO_BASE + 0x210)
+#define RTC_IO_TOUCH_PAD0_REG          (DR_REG_RTCIO_BASE + 0x84)
 /* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD0_DRV  0x00000003
@@ -679,7 +679,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD0_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD0_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD1_REG          (DR_REG_RTCIO_BASE + 0x220)
+#define RTC_IO_TOUCH_PAD1_REG          (DR_REG_RTCIO_BASE + 0x88)
 /* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD1_DRV  0x00000003
@@ -759,7 +759,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD1_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD1_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD2_REG          (DR_REG_RTCIO_BASE + 0x230)
+#define RTC_IO_TOUCH_PAD2_REG          (DR_REG_RTCIO_BASE + 0x8C)
 /* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD2_DRV  0x00000003
@@ -839,7 +839,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD2_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD2_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD3_REG          (DR_REG_RTCIO_BASE + 0x240)
+#define RTC_IO_TOUCH_PAD3_REG          (DR_REG_RTCIO_BASE + 0x90)
 /* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD3_DRV  0x00000003
@@ -919,7 +919,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD3_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD3_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD4_REG          (DR_REG_RTCIO_BASE + 0x250)
+#define RTC_IO_TOUCH_PAD4_REG          (DR_REG_RTCIO_BASE + 0x94)
 /* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD4_DRV  0x00000003
@@ -999,7 +999,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD4_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD4_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD5_REG          (DR_REG_RTCIO_BASE + 0x260)
+#define RTC_IO_TOUCH_PAD5_REG          (DR_REG_RTCIO_BASE + 0x98)
 /* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD5_DRV  0x00000003
@@ -1079,7 +1079,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD5_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD5_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD6_REG          (DR_REG_RTCIO_BASE + 0x270)
+#define RTC_IO_TOUCH_PAD6_REG          (DR_REG_RTCIO_BASE + 0x9C)
 /* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD6_DRV  0x00000003
@@ -1159,7 +1159,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD6_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD6_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD7_REG          (DR_REG_RTCIO_BASE + 0x280)
+#define RTC_IO_TOUCH_PAD7_REG          (DR_REG_RTCIO_BASE + 0xA0)
 /* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD7_DRV  0x00000003
@@ -1239,7 +1239,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD7_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD7_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD8_REG          (DR_REG_RTCIO_BASE + 0x290)
+#define RTC_IO_TOUCH_PAD8_REG          (DR_REG_RTCIO_BASE + 0xA4)
 /* RTC_IO_TOUCH_PAD8_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD8_DRV  0x00000003
@@ -1319,7 +1319,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD8_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD8_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD9_REG          (DR_REG_RTCIO_BASE + 0x2a0)
+#define RTC_IO_TOUCH_PAD9_REG          (DR_REG_RTCIO_BASE + 0xA8)
 /* RTC_IO_TOUCH_PAD9_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD9_DRV  0x00000003
@@ -1399,7 +1399,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD9_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD9_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD10_REG          (DR_REG_RTCIO_BASE + 0x2b0)
+#define RTC_IO_TOUCH_PAD10_REG          (DR_REG_RTCIO_BASE + 0xAC)
 /* RTC_IO_TOUCH_PAD10_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD10_DRV  0x00000003
@@ -1479,7 +1479,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD10_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD10_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD11_REG          (DR_REG_RTCIO_BASE + 0x2c0)
+#define RTC_IO_TOUCH_PAD11_REG          (DR_REG_RTCIO_BASE + 0xB0)
 /* RTC_IO_TOUCH_PAD11_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD11_DRV  0x00000003
@@ -1559,7 +1559,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD11_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD11_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD12_REG          (DR_REG_RTCIO_BASE + 0x2d0)
+#define RTC_IO_TOUCH_PAD12_REG          (DR_REG_RTCIO_BASE + 0xB4)
 /* RTC_IO_TOUCH_PAD12_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD12_DRV  0x00000003
@@ -1639,7 +1639,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD12_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD12_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD13_REG          (DR_REG_RTCIO_BASE + 0x2e0)
+#define RTC_IO_TOUCH_PAD13_REG          (DR_REG_RTCIO_BASE + 0xB8)
 /* RTC_IO_TOUCH_PAD13_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD13_DRV  0x00000003
@@ -1719,7 +1719,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD13_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD13_FUN_IE_S  13
 
-#define RTC_IO_TOUCH_PAD14_REG          (DR_REG_RTCIO_BASE + 0x2f0)
+#define RTC_IO_TOUCH_PAD14_REG          (DR_REG_RTCIO_BASE + 0xBC)
 /* RTC_IO_TOUCH_PAD14_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_TOUCH_PAD14_DRV  0x00000003
@@ -1799,7 +1799,7 @@ extern "C" {
 #define RTC_IO_TOUCH_PAD14_FUN_IE_V  0x1
 #define RTC_IO_TOUCH_PAD14_FUN_IE_S  13
 
-#define RTC_IO_XTAL_32P_PAD_REG          (DR_REG_RTCIO_BASE + 0x300)
+#define RTC_IO_XTAL_32P_PAD_REG          (DR_REG_RTCIO_BASE + 0xC0)
 /* RTC_IO_X32P_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_X32P_DRV  0x00000003
@@ -1855,7 +1855,7 @@ extern "C" {
 #define RTC_IO_X32P_FUN_IE_V  0x1
 #define RTC_IO_X32P_FUN_IE_S  13
 
-#define RTC_IO_XTAL_32N_PAD_REG          (DR_REG_RTCIO_BASE + 0x310)
+#define RTC_IO_XTAL_32N_PAD_REG          (DR_REG_RTCIO_BASE + 0xC4)
 /* RTC_IO_X32N_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_X32N_DRV  0x00000003
@@ -1911,7 +1911,7 @@ extern "C" {
 #define RTC_IO_X32N_FUN_IE_V  0x1
 #define RTC_IO_X32N_FUN_IE_S  13
 
-#define RTC_IO_PAD_DAC1_REG          (DR_REG_RTCIO_BASE + 0x320)
+#define RTC_IO_PAD_DAC1_REG          (DR_REG_RTCIO_BASE + 0xC8)
 /* RTC_IO_PDAC1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: PDAC1_DRV*/
 #define RTC_IO_PDAC1_DRV  0x00000003
@@ -1986,7 +1986,7 @@ extern "C" {
 #define RTC_IO_PDAC1_DAC_V  0xFF
 #define RTC_IO_PDAC1_DAC_S  3
 
-#define RTC_IO_PAD_DAC2_REG          (DR_REG_RTCIO_BASE + 0x330)
+#define RTC_IO_PAD_DAC2_REG          (DR_REG_RTCIO_BASE + 0xCC)
 /* RTC_IO_PDAC2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: PDAC2_DRV*/
 #define RTC_IO_PDAC2_DRV  0x00000003
@@ -2061,7 +2061,7 @@ extern "C" {
 #define RTC_IO_PDAC2_DAC_V  0xFF
 #define RTC_IO_PDAC2_DAC_S  3
 
-#define RTC_IO_RTC_PAD19_REG          (DR_REG_RTCIO_BASE + 0x340)
+#define RTC_IO_RTC_PAD19_REG          (DR_REG_RTCIO_BASE + 0xD0)
 /* RTC_IO_PAD19_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_PAD19_DRV  0x00000003
@@ -2117,7 +2117,7 @@ extern "C" {
 #define RTC_IO_PAD19_FUN_IE_V  0x1
 #define RTC_IO_PAD19_FUN_IE_S  13
 
-#define RTC_IO_RTC_PAD20_REG          (DR_REG_RTCIO_BASE + 0x350)
+#define RTC_IO_RTC_PAD20_REG          (DR_REG_RTCIO_BASE + 0xD4)
 /* RTC_IO_PAD20_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_PAD20_DRV  0x00000003
@@ -2173,7 +2173,7 @@ extern "C" {
 #define RTC_IO_PAD20_FUN_IE_V  0x1
 #define RTC_IO_PAD20_FUN_IE_S  13
 
-#define RTC_IO_RTC_PAD21_REG          (DR_REG_RTCIO_BASE + 0x360)
+#define RTC_IO_RTC_PAD21_REG          (DR_REG_RTCIO_BASE + 0xD8)
 /* RTC_IO_PAD21_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
 /*description: DRV*/
 #define RTC_IO_PAD21_DRV  0x00000003
@@ -2229,7 +2229,7 @@ extern "C" {
 #define RTC_IO_PAD21_FUN_IE_V  0x1
 #define RTC_IO_PAD21_FUN_IE_S  13
 
-#define RTC_IO_EXT_WAKEUP0_REG          (DR_REG_RTCIO_BASE + 0x370)
+#define RTC_IO_EXT_WAKEUP0_REG          (DR_REG_RTCIO_BASE + 0xDC)
 /* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
 /*description: */
 #define RTC_IO_EXT_WAKEUP0_SEL  0x0000001F
@@ -2237,7 +2237,7 @@ extern "C" {
 #define RTC_IO_EXT_WAKEUP0_SEL_V  0x1F
 #define RTC_IO_EXT_WAKEUP0_SEL_S  27
 
-#define RTC_IO_XTL_EXT_CTR_REG          (DR_REG_RTCIO_BASE + 0x380)
+#define RTC_IO_XTL_EXT_CTR_REG          (DR_REG_RTCIO_BASE + 0xE0)
 /* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
 /*description: select RTC GPIO 0 ~ 17 to control XTAL*/
 #define RTC_IO_XTL_EXT_CTR_SEL  0x0000001F
@@ -2245,7 +2245,7 @@ extern "C" {
 #define RTC_IO_XTL_EXT_CTR_SEL_V  0x1F
 #define RTC_IO_XTL_EXT_CTR_SEL_S  27
 
-#define RTC_IO_SAR_I2C_IO_REG          (DR_REG_RTCIO_BASE + 0x390)
+#define RTC_IO_SAR_I2C_IO_REG          (DR_REG_RTCIO_BASE + 0xE4)
 /* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
 /*description: */
 #define RTC_IO_SAR_I2C_SDA_SEL  0x00000003
@@ -2265,8 +2265,8 @@ extern "C" {
 #define RTC_IO_SAR_DEBUG_BIT_SEL_V  0x1F
 #define RTC_IO_SAR_DEBUG_BIT_SEL_S  23
 
-#define RTC_IO_DATE_REG          (DR_REG_RTCIO_BASE + 0x7f0)
+#define RTC_IO_DATE_REG          (DR_REG_RTCIO_BASE + 0x1FC)
-/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1808030 ; */
+/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1903170 ; */
 /*description: */
 #define RTC_IO_IO_DATE  0x0FFFFFFF
 #define RTC_IO_IO_DATE_M  ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S))

components/soc/esp32s2beta/include/soc/rtc_io_struct.h

@@ -98,18 +98,7 @@ typedef volatile struct {
             uint32_t reserved11:                 21;
         };
         uint32_t val;
-    } pin[21];
+    } pin[22];
-    union {
-        struct {
-            uint32_t reserved0:                    2;
-            uint32_t rtc_gpio_pin21_pad_driver:    1;   /*if set to 0: normal output  if set to 1: open drain*/
-            uint32_t reserved3:                    4;
-            uint32_t rtc_gpio_pin21_int_type:      3;   /*if set to 0: GPIO interrupt disable   if set to 1: rising edge trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
-            uint32_t rtc_gpio_pin21_wakeup_enable: 1;   /*RTC GPIO wakeup enable bit*/
-            uint32_t reserved11:                  21;
-        };
-        uint32_t val;
-    } pin21;
     union {
         struct {
             uint32_t sel0:                    5;

components/soc/esp32s2beta/rtc_periph.c

@@ -14,7 +14,28 @@
 
 #include "soc/rtc_periph.h"
 
-//Reg,Mux,Fun,IE,Up,Down,Rtc_number
+/* Reg,Mux,Fun,IE,Up,Down,Rtc_number */
-const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT] = {
+rtc_gpio_info_t* rtc_gpio_reg[RTC_GPIO_NUMBER] = {
-    0
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[0].val,
-};
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[1].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[2].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[3].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[4].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[5].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[6].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[7].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[8].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[9].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[10].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[11].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[12].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[13].val,
+    (rtc_gpio_info_t*)&RTCIO.touch_pad[14].val,
+    (rtc_gpio_info_t*)&RTCIO.xtal_32p_pad.val,
+    (rtc_gpio_info_t*)&RTCIO.xtal_32n_pad.val,
+    (rtc_gpio_info_t*)&RTCIO.pad_dac[0].val,
+    (rtc_gpio_info_t*)&RTCIO.pad_dac[1].val,
+    (rtc_gpio_info_t*)&RTCIO.rtc_pad19.val,
+    (rtc_gpio_info_t*)&RTCIO.rtc_pad20.val,
+    (rtc_gpio_info_t*)&RTCIO.rtc_pad21.val
+};

components/soc/esp32s2beta/sources.cmake

@@ -5,7 +5,9 @@ set(SOC_SRCS    "cpu_util.c"
                 "rtc_sleep.c"
                 "rtc_time.c"
                 "soc_memory_layout.c"
-                "spi_periph.c")
+                "spi_periph.c"
+                "gpio_periph.c"
+                "rtc_periph.c")
 
 if(NOT CMAKE_BUILD_EARLY_EXPANSION)
     set_source_files_properties("esp32s2beta/rtc_clk.c" PROPERTIES

components/soc/include/soc/rtc_periph.h

@@ -57,6 +57,23 @@ typedef struct {
  */
 extern const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT];
 
+typedef volatile struct {
+    uint32_t reserved0:         13;
+    uint32_t fun_ie:             1;             /*input enable in work mode*/
+    uint32_t slp_oe:             1;             /*output enable in sleep mode*/
+    uint32_t slp_ie:             1;             /*input enable in sleep mode*/
+    uint32_t slp_sel:            1;             /*1: enable sleep mode during sleep 0: no sleep mode*/
+    uint32_t fun_sel:            2;             /*function sel*/
+    uint32_t mux_sel:            1;             /*1: use RTC GPIO 0: use digital GPIO*/
+    uint32_t reserved20:         7;
+    uint32_t rue:                1;             /*RUE*/
+    uint32_t rde:                1;             /*RDE*/
+    uint32_t drv:                2;             /*DRV*/
+    uint32_t reserved31:         1;
+} rtc_gpio_info_t;
+
+extern rtc_gpio_info_t* rtc_gpio_reg[RTC_GPIO_NUMBER];
+
 #ifdef __cplusplus
 }
 #endif