heap: add rtc fast memory region to dynamic pool
- for ESP32 only enabled in case of unicore config - capability wise this region (8K) is same as DRAM, except non-DMA capable - also fixed small issue in reserved memory region processing when (start == end)
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4091d44cda
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6 changed files with 64 additions and 5 deletions
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@ -739,6 +739,18 @@ menu "ESP32-specific"
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This is possible due to handling of exceptions `LoadStoreError (3)` and `LoadStoreAlignmentError (9)`
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This is possible due to handling of exceptions `LoadStoreError (3)` and `LoadStoreAlignmentError (9)`
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Each unaligned read/write access will incur a penalty of maximum of 167 CPU cycles.
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Each unaligned read/write access will incur a penalty of maximum of 167 CPU cycles.
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config ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP
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bool "Enable RTC fast memory for dynamic allocations"
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default y
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depends on FREERTOS_UNICORE
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help
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This config option allows to add RTC fast memory region to system heap with capability
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similar to that of DRAM region but without DMA. This memory will be consumed first per
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heap initialization order by early startup services and scheduler related code. Speed
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wise RTC fast memory operates on APB clock and hence does not have much performance impact.
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RTC fast memory is accessible to PRO cpu only and hence this is allowed for single core
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configuration only for ESP32.
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endmenu # ESP32-Specific
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endmenu # ESP32-Specific
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menu "Power Management"
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menu "Power Management"
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@ -498,6 +498,16 @@ menu "ESP32S2-specific"
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If enabled, this disables the linking of binary libraries in the application build. Note
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If enabled, this disables the linking of binary libraries in the application build. Note
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that after enabling this Wi-Fi/Bluetooth will not work.
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that after enabling this Wi-Fi/Bluetooth will not work.
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config ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP
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bool "Enable RTC fast memory for dynamic allocations"
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depends on !ESP32S2_MEMPROT_FEATURE
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default y
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help
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This config option allows to add RTC fast memory region to system heap with capability
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similar to that of DRAM region but without DMA. This memory will be consumed first per
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heap initialization order by early startup services and scheduler related code. Speed
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wise RTC fast memory operates on APB clock and hence does not have much performance impact.
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endmenu # ESP32S2-Specific
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endmenu # ESP32S2-Specific
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menu "Power Management"
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menu "Power Management"
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@ -176,6 +176,12 @@ inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
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intptr_t ip = (intptr_t) p;
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intptr_t ip = (intptr_t) p;
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bool r;
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bool r;
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r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH);
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r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH);
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#if CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP
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/* For ESP32 case, RTC fast memory is accessible to PRO cpu only and hence
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* for single core configuration (where it gets added to system heap) following
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* additional check is required */
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r |= (ip >= SOC_RTC_DRAM_LOW && ip < SOC_RTC_DRAM_HIGH);
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#endif
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#if CONFIG_SPIRAM
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#if CONFIG_SPIRAM
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#if CONFIG_SPIRAM_SIZE != -1 // Fixed size, can be more accurate
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#if CONFIG_SPIRAM_SIZE != -1 // Fixed size, can be more accurate
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r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE));
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r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE));
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@ -190,6 +196,12 @@ inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
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bool r;
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bool r;
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r = ((intptr_t)p >= SOC_MEM_INTERNAL_LOW && (intptr_t)p < SOC_MEM_INTERNAL_HIGH);
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r = ((intptr_t)p >= SOC_MEM_INTERNAL_LOW && (intptr_t)p < SOC_MEM_INTERNAL_HIGH);
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r |= ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
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r |= ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
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#if CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP
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/* For ESP32 case, RTC fast memory is accessible to PRO cpu only and hence
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* for single core configuration (where it gets added to system heap) following
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* additional check is required */
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r |= ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH);
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#endif
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return r;
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return r;
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}
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}
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@ -66,10 +66,10 @@ const soc_memory_type_desc_t soc_memory_types[] = {
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{ "PID5DRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID5DRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID6DRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID6DRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID7DRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID7DRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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#ifdef CONFIG_SPIRAM
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//Type 15: SPI SRAM data
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//Type 15: SPI SRAM data
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{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
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{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
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#endif
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//Type 16: RTC Fast RAM
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{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false},
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};
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};
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const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
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const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
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@ -88,6 +88,9 @@ Because of requirements in the coalescing code which merges adjacent regions, th
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from low to high start address.
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from low to high start address.
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*/
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*/
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const soc_memory_region_t soc_memory_regions[] = {
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const soc_memory_region_t soc_memory_regions[] = {
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#ifdef CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP
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{ SOC_RTC_DRAM_LOW, 0x2000, 16, 0}, //RTC Fast Memory
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#endif
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#ifdef CONFIG_SPIRAM
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#ifdef CONFIG_SPIRAM
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{ SOC_EXTRAM_DATA_LOW, RESERVE_SPIRAM_SIZE, 15, 0}, //SPI SRAM, if available
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{ SOC_EXTRAM_DATA_LOW, RESERVE_SPIRAM_SIZE, 15, 0}, //SPI SRAM, if available
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#endif
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#endif
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@ -183,7 +186,7 @@ SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace me
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SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_LOW + RESERVE_SPIRAM_SIZE, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
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SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_LOW + RESERVE_SPIRAM_SIZE, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
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#endif
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#endif
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extern int _data_start, _heap_start, _iram_start, _iram_end;
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extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end;
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// Static data region. DRAM used by data+bss and possibly rodata
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// Static data region. DRAM used by data+bss and possibly rodata
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
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@ -191,5 +194,13 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_d
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// ESP32 has an IRAM-only region 0x4008_0000 - 0x4009_FFFF, reserve the used part
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// ESP32 has an IRAM-only region 0x4008_0000 - 0x4009_FFFF, reserve the used part
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
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// RTC Fast RAM region
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#ifdef CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP
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#ifdef CONFIG_ESP32_RTCDATA_IN_FAST_MEM
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SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_noinit_end, rtcram_data);
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#else
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SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_fast_end, rtcram_data);
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#endif
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#endif
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#endif /* BOOTLOADER_BUILD */
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#endif /* BOOTLOADER_BUILD */
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@ -51,6 +51,8 @@ const soc_memory_type_desc_t soc_memory_types[] = {
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//Type 4: SPI SRAM data
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//Type 4: SPI SRAM data
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//TODO, in fact, part of them support EDMA, to be supported.
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//TODO, in fact, part of them support EDMA, to be supported.
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{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
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{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
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//Type 5: RTC Fast RAM
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{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false},
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};
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};
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#ifdef CONFIG_ESP32S2_MEMPROT_FEATURE
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#ifdef CONFIG_ESP32S2_MEMPROT_FEATURE
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@ -68,6 +70,9 @@ Because of requirements in the coalescing code which merges adjacent regions, th
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from low to high start address.
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from low to high start address.
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*/
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*/
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const soc_memory_region_t soc_memory_regions[] = {
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const soc_memory_region_t soc_memory_regions[] = {
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#ifdef CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP
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{ SOC_RTC_DRAM_LOW, 0x2000, 5, 0}, //RTC Fast Memory
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#endif
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#ifdef CONFIG_SPIRAM
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#ifdef CONFIG_SPIRAM
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{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW, 4, 0}, //SPI SRAM, if available
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{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW, 4, 0}, //SPI SRAM, if available
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#endif
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#endif
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@ -115,7 +120,7 @@ const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_mem
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extern int _dram0_rtos_reserved_start;
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extern int _dram0_rtos_reserved_start;
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extern int _data_start, _heap_start, _iram_start, _iram_end;
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extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end;
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/* Reserved memory regions
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/* Reserved memory regions
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@ -141,4 +146,13 @@ SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_dat
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SOC_RESERVE_MEMORY_REGION(0x3fffc000 - CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM, 0x3fffc000, trace_mem);
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SOC_RESERVE_MEMORY_REGION(0x3fffc000 - CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM, 0x3fffc000, trace_mem);
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#endif
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#endif
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// RTC Fast RAM region
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#ifdef CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP
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#ifdef CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM
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SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_noinit_end, rtcram_data);
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#else
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SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_fast_end, rtcram_data);
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#endif
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#endif
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#endif // BOOTLOADER_BUILD
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#endif // BOOTLOADER_BUILD
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@ -68,7 +68,7 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c
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reserved[i].start, reserved[i].end);
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reserved[i].start, reserved[i].end);
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reserved[i].start = reserved[i].start & ~3; /* expand all reserved areas to word boundaries */
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reserved[i].start = reserved[i].start & ~3; /* expand all reserved areas to word boundaries */
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reserved[i].end = (reserved[i].end + 3) & ~3;
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reserved[i].end = (reserved[i].end + 3) & ~3;
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assert(reserved[i].start < reserved[i].end);
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assert(reserved[i].start <= reserved[i].end);
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if (i < count - 1) {
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if (i < count - 1) {
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assert(reserved[i + 1].start > reserved[i].start);
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assert(reserved[i + 1].start > reserved[i].start);
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if (reserved[i].end > reserved[i + 1].start) {
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if (reserved[i].end > reserved[i + 1].start) {
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