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Fixed a typo according to DOC-216

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Wang Ning 2020-06-28 18:22:29 +08:00 committed by Krzysztof Budzynski
parent 02a53166b6
commit 1658838efb
1 changed files with 3 additions and 9 deletions
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12
docs/en/api-reference/peripherals/spi_master.rst
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@ -316,16 +316,10 @@ speed a lot if small transactions are used.
from the cost of FreeRTOS queues and the time switching between tasks and from the cost of FreeRTOS queues and the time switching between tasks and
the ISR. the ISR.
1. For **interrupt transactions**, the CPU can switched to other 1. For **interrupt transactions**, the CPU can switch to other tasks when a transaction is in progress. This saves the CPU time but increases the interval. See :ref:`interrupt_transactions`.
tasks when the transaction is in flight. This save the cpu time For **polling transactions**, it does not block the task but allows to do polling when the transaction is in progress. For more information, see :ref:`polling_transactions`.
but increase the interval (See :ref:`interrupt_transactions`).
For
**polling transactions**, it does not block the task but do
polling when the transaction is in flight. (See
:ref:`polling_transactions`).
2. When the DMA is enabled, it needs about 2us per transaction to setup the linked list. When the master is 2. When the DMA is enabled, it needs about 2us per transaction to setup the linked list. When the master is transferring, it automatically read data from the linked list. If the DMA is not enabled,
transferring, it automatically read data from the linked list. If the DMA is not enabled,
CPU has to write/read each byte to/from the FIFO by itself. Usually this is faster than 2us, but the CPU has to write/read each byte to/from the FIFO by itself. Usually this is faster than 2us, but the
transaction length is limited to 64 bytes for both write and read. transaction length is limited to 64 bytes for both write and read.