From 1618dbc9a559044dd36f8c2fdb50352e3729072c Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 20 Mar 2018 18:27:32 +0800 Subject: [PATCH] soc/rtc: wait for frequency switch to complete The fast path of CPU frequency switch function, used in DFS, was not waiting for the frequency switch to complete when switching from XTAL to PLL. This resulted in incorrect reads from peripherals on APB, where two consecutive reads could return the same value. For example, in esp_timer, read of FRC_COUNT_REG would return same value as the preceding read of FRC_ALARM_REG, causing time to jump by the value of FRC_ALARM_REG / apb_freq_mhz. --- components/soc/esp32/rtc_clk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index 54dea84c5..eb72da2ce 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -402,6 +402,7 @@ void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq) rtc_clk_cpu_freq_to_xtal(); } else if (cpu_freq > RTC_CPU_FREQ_XTAL) { rtc_clk_cpu_freq_to_pll(cpu_freq); + rtc_clk_wait_for_slow_cycle(); } }