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Fix rebooting when PSRAM is active

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This commit is contained in:
Jeroen Domburg 2017-09-04 19:00:47 +08:00
parent f487bb19d7
commit 0e74ec67be
1 changed files with 12 additions and 0 deletions
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12
components/esp32/system_api.c
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@ -24,6 +24,7 @@
#include "rom/cache.h" #include "rom/cache.h"
#include "rom/uart.h" #include "rom/uart.h"
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#include "soc/gpio_reg.h"
#include "soc/efuse_reg.h" #include "soc/efuse_reg.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "soc/timer_group_reg.h" #include "soc/timer_group_reg.h"
@ -298,6 +299,17 @@ void IRAM_ATTR esp_restart_noos()
Cache_Read_Disable(0); Cache_Read_Disable(0);
Cache_Read_Disable(1); Cache_Read_Disable(1);
#ifdef CONFIG_SPIRAM_SUPPORT
//External SPI RAM reconfigures some GPIO functions in a way that is not entirely undone in the boot rom.
//Undo them manually so we reboot correctly.
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
#endif
// Flush any data left in UART FIFOs // Flush any data left in UART FIFOs
uart_tx_wait_idle(0); uart_tx_wait_idle(0);
uart_tx_wait_idle(1); uart_tx_wait_idle(1);