From 0c2bf7c8bc01ed21b89ed69ab2d3f22366923b25 Mon Sep 17 00:00:00 2001 From: fuzhibo Date: Thu, 25 Jul 2019 23:11:31 +0800 Subject: [PATCH] rtcio: add hal for driver --- components/driver/CMakeLists.txt | 1 + components/driver/Kconfig | 13 + components/driver/include/driver/gpio.h | 103 +--- components/driver/include/driver/rtc_io.h | 131 ++--- components/driver/rtc_io.c | 228 +++++++++ components/driver/rtc_module.c | 453 +----------------- components/driver/test/test_rtcio.c | 216 +++++++++ components/esp32/sleep_modes.c | 25 +- components/esp32/test/test_pm.c | 8 +- components/esp32s2beta/sleep_modes.c | 40 +- components/soc/CMakeLists.txt | 1 + components/soc/esp32/include/hal/rtc_io_ll.h | 348 ++++++++++++++ .../soc/esp32/include/soc/rtc_io_caps.h | 21 + .../{rtc_gpio_channel.h => rtc_io_channel.h} | 4 +- components/soc/esp32/rtc_io_periph.c | 128 +++++ components/soc/esp32/rtc_periph.c | 59 --- components/soc/esp32/sources.cmake | 1 + .../soc/esp32s2beta/include/hal/rtc_io_ll.h | 348 ++++++++++++++ .../soc/esp32s2beta/include/soc/rtc_io_caps.h | 18 + .../{rtc_gpio_channel.h => rtc_io_channel.h} | 2 +- components/soc/esp32s2beta/rtc_io_periph.c | 93 ++++ components/soc/esp32s2beta/rtc_periph.c | 26 - components/soc/esp32s2beta/sources.cmake | 1 + components/soc/include/hal/gpio_types.h | 51 ++ components/soc/include/hal/rtc_io_hal.h | 239 +++++++++ components/soc/include/hal/rtc_io_types.h | 25 + components/soc/include/soc/rtc_io_periph.h | 109 +++++ components/soc/include/soc/rtc_periph.h | 54 +-- components/soc/src/hal/rtc_io_hal.c | 92 ++++ docs/Doxyfile | 3 +- examples/system/ulp/main/ulp_example_main.c | 5 +- 31 files changed, 2022 insertions(+), 824 deletions(-) create mode 100644 components/driver/rtc_io.c create mode 100644 components/driver/test/test_rtcio.c create mode 100644 components/soc/esp32/include/hal/rtc_io_ll.h create mode 100644 components/soc/esp32/include/soc/rtc_io_caps.h rename components/soc/esp32/include/soc/{rtc_gpio_channel.h => rtc_io_channel.h} (97%) create mode 100644 components/soc/esp32/rtc_io_periph.c create mode 100644 components/soc/esp32s2beta/include/hal/rtc_io_ll.h create mode 100644 components/soc/esp32s2beta/include/soc/rtc_io_caps.h rename components/soc/esp32s2beta/include/soc/{rtc_gpio_channel.h => rtc_io_channel.h} (98%) create mode 100644 components/soc/esp32s2beta/rtc_io_periph.c create mode 100644 components/soc/include/hal/gpio_types.h create mode 100644 components/soc/include/hal/rtc_io_hal.h create mode 100644 components/soc/include/hal/rtc_io_types.h create mode 100644 components/soc/include/soc/rtc_io_periph.h create mode 100644 components/soc/src/hal/rtc_io_hal.c diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index d667cd4d4..1f8d7865e 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -7,6 +7,7 @@ set(srcs "pcnt.c" "periph_ctrl.c" "rmt.c" + "rtc_io.c" "rtc_module.c" "sdspi_crc.c" "sdspi_host.c" diff --git a/components/driver/Kconfig b/components/driver/Kconfig index 65431bf5e..d30966f3e 100644 --- a/components/driver/Kconfig +++ b/components/driver/Kconfig @@ -82,4 +82,17 @@ menu "Driver configurations" endmenu # UART Configuration + menu "RTCIO configuration" + + config RTCIO_SUPPORT_RTC_GPIO_DESC + bool "Support array `rtc_gpio_desc` for ESP32" + depends on IDF_TARGET_ESP32 + default n + help + The the array `rtc_gpio_desc` will don't compile by default. + If this option is selected, the array `rtc_gpio_desc` can be compile. + If user use this array, please enable this configuration. + + endmenu # RTCIO Configuration + endmenu # Driver configurations diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h index 7223d6f46..1e923ec5e 100644 --- a/components/driver/include/driver/gpio.h +++ b/components/driver/include/driver/gpio.h @@ -21,6 +21,7 @@ #include "esp_attr.h" #include "esp_intr_alloc.h" #include "soc/gpio_periph.h" +#include "hal/gpio_types.h" #include "sdkconfig.h" @@ -237,108 +238,6 @@ extern "C" { #define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */ #endif -#if CONFIG_IDF_TARGET_ESP32 -typedef enum { - GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ - GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ - GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ - GPIO_NUM_2 = 2, /*!< GPIO2, input and output - @note There are more enumerations like that - up to GPIO39, excluding GPIO20, GPIO24 and GPIO28..31. - They are not shown here to reduce redundant information. - @note GPIO34..39 are input mode only. */ -/** @cond */ - GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ - GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ - GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ - GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ - GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ - GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ - GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ - GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ - GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ - GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ - GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ - GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ - GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ - GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ - GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ - GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ - GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ - - GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ - GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ - GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ - - GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ - GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ - GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ - - GPIO_NUM_32 = 32, /*!< GPIO32, input and output */ - GPIO_NUM_33 = 33, /*!< GPIO33, input and output */ - GPIO_NUM_34 = 34, /*!< GPIO34, input mode only */ - GPIO_NUM_35 = 35, /*!< GPIO35, input mode only */ - GPIO_NUM_36 = 36, /*!< GPIO36, input mode only */ - GPIO_NUM_37 = 37, /*!< GPIO37, input mode only */ - GPIO_NUM_38 = 38, /*!< GPIO38, input mode only */ - GPIO_NUM_39 = 39, /*!< GPIO39, input mode only */ - GPIO_NUM_MAX = 40, -/** @endcond */ -} gpio_num_t; - - -#elif CONFIG_IDF_TARGET_ESP32S2BETA -typedef enum { - GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ - GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ - GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ - GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ - GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ - GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ - GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ - GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ - GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ - GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ - GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ - GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ - GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ - GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ - GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ - GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ - GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ - GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ - GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ - GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ - GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ - GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ - GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ - /* Note: The missing IO is because it is used inside the chip. */ - GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ - GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ - GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ - GPIO_NUM_29 = 29, /*!< GPIO29, input and output */ - GPIO_NUM_30 = 30, /*!< GPIO30, input and output */ - GPIO_NUM_31 = 31, /*!< GPIO31, input and output */ - GPIO_NUM_32 = 32, /*!< GPIO32, input and output */ - GPIO_NUM_33 = 33, /*!< GPIO33, input and output */ - GPIO_NUM_34 = 34, /*!< GPIO34, input and output */ - GPIO_NUM_35 = 35, /*!< GPIO35, input and output */ - GPIO_NUM_36 = 36, /*!< GPIO36, input and output */ - GPIO_NUM_37 = 37, /*!< GPIO37, input and output */ - GPIO_NUM_38 = 38, /*!< GPIO38, input and output */ - GPIO_NUM_39 = 39, /*!< GPIO39, input and output */ - GPIO_NUM_40 = 40, /*!< GPIO40, input and output */ - GPIO_NUM_41 = 41, /*!< GPIO41, input and output */ - GPIO_NUM_42 = 42, /*!< GPIO42, input and output */ - GPIO_NUM_43 = 43, /*!< GPIO43, input and output */ - GPIO_NUM_44 = 44, /*!< GPIO44, input and output */ - GPIO_NUM_45 = 45, /*!< GPIO45, input and output */ - GPIO_NUM_46 = 46, /*!< GPIO46, input mode only */ - GPIO_NUM_MAX = 47, -/** @endcond */ -} gpio_num_t; -#endif - typedef enum { GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */ GPIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */ diff --git a/components/driver/include/driver/rtc_io.h b/components/driver/include/driver/rtc_io.h index 73ede4341..c6127e666 100644 --- a/components/driver/include/driver/rtc_io.h +++ b/components/driver/include/driver/rtc_io.h @@ -18,43 +18,39 @@ #include #include "esp_err.h" #include "driver/gpio.h" -#include "soc/rtc_periph.h" +#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_types.h" #ifdef __cplusplus extern "C" { #endif -typedef enum { - RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad input */ - RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad output */ - RTC_GPIO_MODE_INPUT_OUTPUT, /*!< Pad pull input + output */ - RTC_GPIO_MODE_DISABLED, /*!< Pad (output + input) disable */ -} rtc_gpio_mode_t; - -#if CONFIG_IDF_TARGET_ESP32S2BETA -typedef enum { - RTCIO_MODE_OUTPUT = 0, /*!< Pad output normal mode */ - RTCIO_MODE_OUTPUT_OD = 1, /*!< Pad output OD mode */ -} rtc_io_out_mode_t; -#endif - /** * @brief Determine if the specified GPIO is a valid RTC GPIO. * * @param gpio_num GPIO number * @return true if GPIO is valid for RTC GPIO use. false otherwise. */ -inline static bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num) +static inline bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num) { -#if CONFIG_IDF_TARGET_ESP32 - return gpio_num < GPIO_PIN_COUNT - && rtc_gpio_desc[gpio_num].reg != 0; -#elif CONFIG_IDF_TARGET_ESP32S2BETA - return (gpio_num < RTC_GPIO_NUMBER); -#endif + return (gpio_num < GPIO_PIN_COUNT + && rtc_io_num_map[gpio_num] >= 0); } #define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num) // Deprecated, use rtc_gpio_is_valid_gpio() +/** + * @brief Get RTC IO index number by gpio number. + * + * @param gpio_num GPIO number + * @return + * >=0: Index of rtcio. + * -1 : The gpio is not rtcio. + */ +static inline int rtc_io_number_get(gpio_num_t gpio_num) +{ + return rtc_io_num_map[gpio_num]; +} + /** * @brief Init a GPIO as RTC GPIO * @@ -118,6 +114,22 @@ esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level); */ esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode); +/** + * @brief RTC GPIO set direction in deep sleep mode or disable sleep status (default). + * In some application scenarios, IO needs to have another states during deep sleep. + * + * NOTE: ESP32 support INPUT_ONLY mode. + * ESP32S2 support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode. + * + * @param gpio_num GPIO number (e.g. GPIO_NUM_12) + * @param mode GPIO direction + * + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG GPIO is not an RTC IO + */ +esp_err_t rtc_gpio_set_direction_in_sleep(gpio_num_t gpio_num, rtc_gpio_mode_t mode); + /** * @brief RTC GPIO pullup enable * @@ -222,7 +234,7 @@ esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num); esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num); /** - * @brief Disable force hold signal for all RTC IOs + * @brief Enable force hold signal for all RTC IOs * * Each RTC pad has a "force hold" input signal from the RTC controller. * If this signal is set, pad latches current values of input enable, @@ -230,7 +242,12 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num); * Force hold signal is enabled before going into deep sleep for pins which * are used for EXT1 wakeup. */ -void rtc_gpio_force_hold_dis_all(void); +esp_err_t rtc_gpio_force_hold_all(void); + +/** + * @brief Disable force hold signal for all RTC IOs + */ +esp_err_t rtc_gpio_force_hold_dis_all(void); /** * @brief Set RTC GPIO pad drive capability @@ -277,72 +294,6 @@ esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) */ esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num); -#if CONFIG_IDF_TARGET_ESP32S2BETA -/** - * @brief RTC IO set output mode - * @param gpio_num Configure GPIO pins number - * @param mode GPIO output mode - * @return - * - ESP_OK Success - * - ESP_ERR_INVALID_ARG GPIO error - * - */ -esp_err_t rtc_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode); - -/** - * @brief RTC IO get output mode - * @param gpio_num Configure GPIO pins number - * @param mode GPIO output mode - * @return - * - ESP_OK Success - * - ESP_ERR_INVALID_ARG GPIO error - */ -esp_err_t rtc_gpio_get_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t *mode); - -/** - * @brief Set RTC IO status in deep sleep - * In some application scenarios, IO needs to have another states during deep sleep. - * @param gpio_num Configure GPIO pins number - * @param input input mode. false: close; true: open; - * @return - * - ESP_OK Success - * - ESP_ERR_INVALID_ARG GPIO error - */ -esp_err_t rtc_gpio_sleep_input_enable(gpio_num_t gpio_num, bool input); - -/** - * @brief Set RTC IO status in deep sleep - * In some application scenarios, IO needs to have another states during deep sleep. - * @param gpio_num Configure GPIO pins number - * @param output output mode. false: close; true: open; - * @return - * - ESP_OK Success - * - ESP_ERR_INVALID_ARG GPIO error - */ -esp_err_t rtc_gpio_sleep_output_enable(gpio_num_t gpio_num, bool output); - -/** - * @brief Close RTC IO status in deep sleep - * In some application scenarios, IO needs to have another states during deep sleep. - * @param gpio_num Configure GPIO pins number - * @return - * - ESP_OK Success - * - ESP_ERR_INVALID_ARG GPIO error - */ -esp_err_t rtc_gpio_sleep_mode_disable(gpio_num_t gpio_num); - -/** - * @brief Enable force hold signal for all RTC IOs - * - * Each RTC pad has a "force hold" input signal from the RTC controller. - * If this signal is set, pad latches current values of input enable, - * function, output enable, and other signals which come from the RTC mux. - * Force hold signal is enabled before going into deep sleep for pins which - * are used for EXT1 wakeup. - */ -esp_err_t rtc_gpio_force_hold_all(void); -#endif - #ifdef __cplusplus } #endif diff --git a/components/driver/rtc_io.c b/components/driver/rtc_io.c new file mode 100644 index 000000000..f851129f2 --- /dev/null +++ b/components/driver/rtc_io.c @@ -0,0 +1,228 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "esp_log.h" +#include "esp_err.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "freertos/timers.h" +#include "driver/rtc_io.h" +#include "hal/rtc_io_hal.h" + +static const char *RTCIO_TAG = "RTCIO"; + +#define RTCIO_CHECK(a, str, ret_val) ({ \ + if (!(a)) { \ + ESP_LOGE(RTCIO_TAG,"%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, str); \ + return (ret_val); \ + } \ +}) + +extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished. +#define RTCIO_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock) +#define RTCIO_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock) + +/*--------------------------------------------------------------- + RTC IO +---------------------------------------------------------------*/ +esp_err_t rtc_gpio_init(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_FUNC_RTC); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + // Select Gpio as Digital Gpio + rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_FUNC_DIGITAL); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_set_level(rtc_io_number_get(gpio_num), level); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +uint32_t rtc_gpio_get_level(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + return rtcio_hal_get_level(rtc_io_number_get(gpio_num)); +} + +esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Output pad only", ESP_ERR_INVALID_ARG); + RTCIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "RTCIO drive capability error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_set_drive_capability(rtc_io_number_get(gpio_num), strength); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *strength) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Output pad only", ESP_ERR_INVALID_ARG); + RTCIO_CHECK(strength != NULL, "GPIO drive pointer error", ESP_ERR_INVALID_ARG); + *strength = (gpio_drive_cap_t)rtcio_hal_get_drive_capability(rtc_io_number_get(gpio_num)); + + return ESP_OK; +} + +esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_set_direction(rtc_io_number_get(gpio_num), mode); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_set_direction_in_sleep(gpio_num_t gpio_num, rtc_gpio_mode_t mode) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_set_direction_in_sleep(rtc_io_number_get(gpio_num), mode); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_pullup_en(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_pullup_enable(rtc_io_number_get(gpio_num)); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_pullup_disable(rtc_io_number_get(gpio_num)); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_pulldown_enable(rtc_io_number_get(gpio_num)); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_pulldown_disable(rtc_io_number_get(gpio_num)); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_hold_enable(rtc_io_number_get(gpio_num)); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_hold_disable(rtc_io_number_get(gpio_num)); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_isolate(rtc_io_number_get(gpio_num)); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_force_hold_en_all(void) +{ + RTCIO_ENTER_CRITICAL(); + rtcio_hal_hold_all(); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_force_hold_dis_all(void) +{ + RTCIO_ENTER_CRITICAL(); + rtcio_hal_unhold_all(); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + if (intr_type == GPIO_INTR_POSEDGE || intr_type == GPIO_INTR_NEGEDGE || intr_type == GPIO_INTR_ANYEDGE) { + return ESP_ERR_INVALID_ARG; // Dont support this mode. + } + RTCIO_ENTER_CRITICAL(); + rtcio_hal_wakeup_enable(rtc_io_number_get(gpio_num), intr_type); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} + +esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num) +{ + RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG); + RTCIO_ENTER_CRITICAL(); + rtcio_hal_wakeup_disable(rtc_io_number_get(gpio_num)); + RTCIO_EXIT_CRITICAL(); + + return ESP_OK; +} diff --git a/components/driver/rtc_module.c b/components/driver/rtc_module.c index a27c7c57a..5ef71e760 100644 --- a/components/driver/rtc_module.c +++ b/components/driver/rtc_module.c @@ -33,6 +33,7 @@ #include "sys/lock.h" #include "driver/rtc_cntl.h" #include "driver/gpio.h" +#include "driver/rtc_io.h" #include "adc1_i2s_private.h" #include "sdkconfig.h" #if CONFIG_IDF_TARGET_ESP32 @@ -138,445 +139,6 @@ static const char TAG[] = "adc"; static inline void dac_output_set_enable(dac_channel_t channel, bool enable); static inline void adc1_hall_enable(bool enable); - -/*--------------------------------------------------------------- - RTC IO ----------------------------------------------------------------*/ -esp_err_t rtc_gpio_init(gpio_num_t gpio_num) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&rtc_spinlock); -#if CONFIG_IDF_TARGET_ESP32 - // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. - SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, (rtc_gpio_desc[gpio_num].mux)); - //0:RTC FUNCIOTN 1,2,3:Reserved - SET_PERI_REG_BITS(rtc_gpio_desc[gpio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, 0x0, rtc_gpio_desc[gpio_num].func); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - rtc_gpio_reg[gpio_num]->mux_sel = 0x1; - rtc_gpio_reg[gpio_num]->fun_sel = 0x0; -#endif - portEXIT_CRITICAL(&rtc_spinlock); - - return ESP_OK; -} - -esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&rtc_spinlock); - //Select Gpio as Digital Gpio -#if CONFIG_IDF_TARGET_ESP32 - CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, (rtc_gpio_desc[gpio_num].mux)); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - rtc_gpio_reg[gpio_num]->mux_sel = 0x0; -#endif - portEXIT_CRITICAL(&rtc_spinlock); - - return ESP_OK; -} - -static esp_err_t rtc_gpio_output_enable(gpio_num_t gpio_num) -{ -#if CONFIG_IDF_TARGET_ESP32 - int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num; - RTC_MODULE_CHECK(rtc_gpio_num != -1, "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - SET_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TS_REG, (1 << (rtc_gpio_num + RTC_GPIO_ENABLE_W1TS_S))); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - SET_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TS_REG, (1 << ( gpio_num + RTC_GPIO_ENABLE_W1TS_S))); -#endif - return ESP_OK; -} - -static esp_err_t rtc_gpio_output_disable(gpio_num_t gpio_num) -{ -#if CONFIG_IDF_TARGET_ESP32 - int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num; - RTC_MODULE_CHECK(rtc_gpio_num != -1, "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - SET_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TC_REG, (1 << ( rtc_gpio_num + RTC_GPIO_ENABLE_W1TC_S))); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - SET_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TC_REG, (1 << ( gpio_num + RTC_GPIO_ENABLE_W1TC_S))); -#endif - return ESP_OK; -} - -static esp_err_t rtc_gpio_input_enable(gpio_num_t gpio_num) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&rtc_spinlock); -#if CONFIG_IDF_TARGET_ESP32 - SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].ie); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - rtc_gpio_reg[gpio_num]->fun_ie = 1; -#endif - portEXIT_CRITICAL(&rtc_spinlock); - - return ESP_OK; -} - -static esp_err_t rtc_gpio_input_disable(gpio_num_t gpio_num) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&rtc_spinlock); -#if CONFIG_IDF_TARGET_ESP32 - CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].ie); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - rtc_gpio_reg[gpio_num]->fun_ie = 0; -#endif - portEXIT_CRITICAL(&rtc_spinlock); - - return ESP_OK; -} - -#if CONFIG_IDF_TARGET_ESP32S2BETA -esp_err_t rtc_gpio_sleep_output_enable(gpio_num_t gpio_num, bool output) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - rtc_gpio_reg[gpio_num]->slp_sel = 1; - rtc_gpio_reg[gpio_num]->slp_oe = output; - return ESP_OK; -} - -esp_err_t rtc_gpio_sleep_input_enable(gpio_num_t gpio_num, bool input) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - rtc_gpio_reg[gpio_num]->slp_sel = 1; - rtc_gpio_reg[gpio_num]->slp_ie = input; - return ESP_OK; -} - -esp_err_t rtc_gpio_sleep_mode_disable(gpio_num_t gpio_num) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - rtc_gpio_reg[gpio_num]->slp_sel = 0; - return ESP_OK; -} -#endif - -esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level) -{ -#if CONFIG_IDF_TARGET_ESP32 - int rtc_gpio_num = rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;; - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - - if (level) { - WRITE_PERI_REG(RTC_GPIO_OUT_W1TS_REG, (1 << (rtc_gpio_num + RTC_GPIO_OUT_DATA_W1TS_S))); - } else { - WRITE_PERI_REG(RTC_GPIO_OUT_W1TC_REG, (1 << (rtc_gpio_num + RTC_GPIO_OUT_DATA_W1TC_S))); - } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - if (level) { - WRITE_PERI_REG(RTC_GPIO_OUT_W1TS_REG, (1 << (gpio_num + RTC_GPIO_OUT_DATA_W1TS_S))); - } else { - WRITE_PERI_REG(RTC_GPIO_OUT_W1TC_REG, (1 << (gpio_num + RTC_GPIO_OUT_DATA_W1TC_S))); - } -#endif - return ESP_OK; -} - -uint32_t rtc_gpio_get_level(gpio_num_t gpio_num) -{ - uint32_t level = 0; -#if CONFIG_IDF_TARGET_ESP32 - int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num; - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - - portENTER_CRITICAL(&rtc_spinlock); - level = READ_PERI_REG(RTC_GPIO_IN_REG); - portEXIT_CRITICAL(&rtc_spinlock); - return ((level >> (RTC_GPIO_IN_NEXT_S + rtc_gpio_num)) & 0x01); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&rtc_spinlock); - level = RTCIO.in_val.in; - portEXIT_CRITICAL(&rtc_spinlock); - return ((level >> gpio_num) & 0x1); -#endif -} - -esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - RTC_MODULE_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Output pad only", ESP_ERR_INVALID_ARG); - RTC_MODULE_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG); - - portENTER_CRITICAL(&rtc_spinlock); -#if CONFIG_IDF_TARGET_ESP32 - SET_PERI_REG_BITS(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].drv_v, strength, rtc_gpio_desc[gpio_num].drv_s); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - rtc_gpio_reg[gpio_num]->drv = strength; -#endif - portEXIT_CRITICAL(&rtc_spinlock); - return ESP_OK; -} - -esp_err_t rtc_gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - RTC_MODULE_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Output pad only", ESP_ERR_INVALID_ARG); - RTC_MODULE_CHECK(strength != NULL, "GPIO drive pointer error", ESP_ERR_INVALID_ARG); -#if CONFIG_IDF_TARGET_ESP32 - *strength = GET_PERI_REG_BITS2(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].drv_v, rtc_gpio_desc[gpio_num].drv_s); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - *strength = rtc_gpio_reg[gpio_num]->drv; -#endif - return ESP_OK; -} - -esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - - switch (mode) { - case RTC_GPIO_MODE_INPUT_ONLY: - rtc_gpio_output_disable(gpio_num); - rtc_gpio_input_enable(gpio_num); - break; - case RTC_GPIO_MODE_OUTPUT_ONLY: - rtc_gpio_output_enable(gpio_num); - rtc_gpio_input_disable(gpio_num); - break; - case RTC_GPIO_MODE_INPUT_OUTPUT: - rtc_gpio_output_enable(gpio_num); - rtc_gpio_input_enable(gpio_num); - break; - case RTC_GPIO_MODE_DISABLED: - rtc_gpio_output_disable(gpio_num); - rtc_gpio_input_disable(gpio_num); - break; - } - - return ESP_OK; -} - -esp_err_t rtc_gpio_pullup_en(gpio_num_t gpio_num) -{ -#if CONFIG_IDF_TARGET_ESP32 - //this is a digital pad - if (rtc_gpio_desc[gpio_num].pullup == 0) { - return ESP_ERR_INVALID_ARG; - } -#endif - //this is a rtc pad - portENTER_CRITICAL(&rtc_spinlock); -#if CONFIG_IDF_TARGET_ESP32 - SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pullup); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - rtc_gpio_reg[gpio_num]->rue = 0x1; -#endif - portEXIT_CRITICAL(&rtc_spinlock); - - return ESP_OK; -} - -#if CONFIG_IDF_TARGET_ESP32S2BETA -esp_err_t rtc_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&rtc_spinlock); - RTCIO.pin[gpio_num].pad_driver = mode; - portEXIT_CRITICAL(&rtc_spinlock); - return ESP_OK; -} - -esp_err_t rtc_gpio_get_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t *mode) -{ - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - *mode = RTCIO.pin[gpio_num].pad_driver; - return ESP_OK; -} -#endif - -esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num) -{ -#if CONFIG_IDF_TARGET_ESP32 - //this is a digital pad - if (rtc_gpio_desc[gpio_num].pulldown == 0) { - return ESP_ERR_INVALID_ARG; - } - - //this is a rtc pad - portENTER_CRITICAL(&rtc_spinlock); - SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pulldown); - portEXIT_CRITICAL(&rtc_spinlock); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - portENTER_CRITICAL(&rtc_spinlock); - rtc_gpio_reg[gpio_num]->rde = 0x1; - portEXIT_CRITICAL(&rtc_spinlock); -#endif - return ESP_OK; -} - -esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num) -{ -#if CONFIG_IDF_TARGET_ESP32 - //this is a digital pad - if ( rtc_gpio_desc[gpio_num].pullup == 0 ) { - return ESP_ERR_INVALID_ARG; - } - - //this is a rtc pad - portENTER_CRITICAL(&rtc_spinlock); - CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pullup); - portEXIT_CRITICAL(&rtc_spinlock); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - portENTER_CRITICAL(&rtc_spinlock); - rtc_gpio_reg[gpio_num]->rue = 0x0; - portEXIT_CRITICAL(&rtc_spinlock); -#endif - return ESP_OK; -} - -esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num) -{ -#if CONFIG_IDF_TARGET_ESP32 - //this is a digital pad - if (rtc_gpio_desc[gpio_num].pulldown == 0) { - return ESP_ERR_INVALID_ARG; - } - - //this is a rtc pad - portENTER_CRITICAL(&rtc_spinlock); - CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pulldown); - portEXIT_CRITICAL(&rtc_spinlock); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - portENTER_CRITICAL(&rtc_spinlock); - rtc_gpio_reg[gpio_num]->rde = 0x0; - portEXIT_CRITICAL(&rtc_spinlock); -#endif - return ESP_OK; -} - -esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num) -{ -#if CONFIG_IDF_TARGET_ESP32 - // check if an RTC IO - if (rtc_gpio_desc[gpio_num].pullup == 0) { - return ESP_ERR_INVALID_ARG; - } - portENTER_CRITICAL(&rtc_spinlock); - SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].hold); - portEXIT_CRITICAL(&rtc_spinlock); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&rtc_spinlock); - RTCCNTL.pad_hold.val |= BIT(gpio_num); - portEXIT_CRITICAL(&rtc_spinlock); -#endif - return ESP_OK; -} - -esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num) -{ -#if CONFIG_IDF_TARGET_ESP32 - // check if an RTC IO - if (rtc_gpio_desc[gpio_num].pullup == 0) { - return ESP_ERR_INVALID_ARG; - } - portENTER_CRITICAL(&rtc_spinlock); - CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].hold); - portEXIT_CRITICAL(&rtc_spinlock); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&rtc_spinlock); - RTCCNTL.pad_hold.val &= ~(BIT(gpio_num)); - portEXIT_CRITICAL(&rtc_spinlock); -#endif - return ESP_OK; -} - -esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num) -{ -#if CONFIG_IDF_TARGET_ESP32 - if (rtc_gpio_desc[gpio_num].reg == 0) { - return ESP_ERR_INVALID_ARG; - } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); -#endif - rtc_gpio_pullup_dis(gpio_num); - rtc_gpio_pulldown_dis(gpio_num); - rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED); - rtc_gpio_hold_en(gpio_num); - - return ESP_OK; -} - -void rtc_gpio_force_hold_dis_all(void) -{ -#if CONFIG_IDF_TARGET_ESP32 - for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) { - const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio]; - if (desc->hold_force != 0) { - REG_CLR_BIT(RTC_CNTL_HOLD_FORCE_REG, desc->hold_force); - } - } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - portENTER_CRITICAL(&rtc_spinlock); - RTCCNTL.rtc_pwc.rtc_pad_force_hold = 0; - portEXIT_CRITICAL(&rtc_spinlock); -#endif -} - -esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) -{ -#if CONFIG_IDF_TARGET_ESP32 - int rtc_num = rtc_gpio_desc[gpio_num].rtc_num; - if (rtc_num < 0) { - return ESP_ERR_INVALID_ARG; - } - if (( intr_type != GPIO_INTR_LOW_LEVEL ) && ( intr_type != GPIO_INTR_HIGH_LEVEL )) { - return ESP_ERR_INVALID_ARG; - } - - uint32_t reg = RTC_GPIO_PIN0_REG + rtc_num * sizeof(uint32_t); - /* each pin has its own register, spinlock not needed */ - REG_SET_BIT(reg, RTC_GPIO_PIN0_WAKEUP_ENABLE); - REG_SET_FIELD(reg, RTC_GPIO_PIN0_INT_TYPE, intr_type); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - if (( intr_type != GPIO_INTR_LOW_LEVEL ) && ( intr_type != GPIO_INTR_HIGH_LEVEL )) { - return ESP_ERR_INVALID_ARG; - } - /* each pin has its own register, spinlock not needed */ - RTCIO.pin[gpio_num].wakeup_enable = 1; - RTCIO.pin[gpio_num].int_type = intr_type; -#endif - return ESP_OK; -} - -esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num) -{ -#if CONFIG_IDF_TARGET_ESP32 - int rtc_num = rtc_gpio_desc[gpio_num].rtc_num; - if (rtc_num < 0) { - return ESP_ERR_INVALID_ARG; - } - - uint32_t reg = RTC_GPIO_PIN0_REG + rtc_num * sizeof(uint32_t); - /* each pin has its own register, spinlock not needed */ - REG_CLR_BIT(reg, RTC_GPIO_PIN0_WAKEUP_ENABLE); - REG_SET_FIELD(reg, RTC_GPIO_PIN0_INT_TYPE, 0); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG); - /* each pin has its own register, spinlock not needed */ - RTCIO.pin[gpio_num].wakeup_enable = 0; - RTCIO.pin[gpio_num].int_type = 0; -#endif - return ESP_OK; -} - -#if CONFIG_IDF_TARGET_ESP32S2BETA -esp_err_t rtc_gpio_force_hold_all() -{ - portENTER_CRITICAL(&rtc_spinlock); - RTCCNTL.rtc_pwc.rtc_pad_force_hold = 1; - portEXIT_CRITICAL(&rtc_spinlock); - return ESP_OK; -} -#endif #if CONFIG_IDF_TARGET_ESP32 /*--------------------------------------------------------------- Touch Pad @@ -1227,6 +789,7 @@ esp_err_t touch_pad_get_wakeup_status(touch_pad_t *pad_num) return ESP_OK; } #endif + /*--------------------------------------------------------------- ADC Common ---------------------------------------------------------------*/ @@ -1434,8 +997,7 @@ esp_err_t adc_gpio_init(adc_unit_t adc_unit, adc_channel_t channel) RTC_MODULE_CHECK((adc1_channel_t) channel < ADC1_CHANNEL_MAX, "ADC1 channel error", ESP_ERR_INVALID_ARG); ADC1_CHECK_FUNCTION_RET(adc1_pad_get_io_num((adc1_channel_t) channel, &gpio_num)); ADC1_CHECK_FUNCTION_RET(rtc_gpio_init(gpio_num)); - ADC1_CHECK_FUNCTION_RET(rtc_gpio_output_disable(gpio_num)); - ADC1_CHECK_FUNCTION_RET(rtc_gpio_input_disable(gpio_num)); + ADC1_CHECK_FUNCTION_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED)); ADC1_CHECK_FUNCTION_RET(gpio_set_pull_mode(gpio_num, GPIO_FLOATING)); } return ESP_OK; @@ -1982,8 +1544,7 @@ static esp_err_t adc2_pad_init(adc2_channel_t channel) gpio_num_t gpio_num = 0; ADC2_CHECK_FUNCTION_RET(adc2_pad_get_io_num(channel, &gpio_num)); ADC2_CHECK_FUNCTION_RET(rtc_gpio_init(gpio_num)); - ADC2_CHECK_FUNCTION_RET(rtc_gpio_output_disable(gpio_num)); - ADC2_CHECK_FUNCTION_RET(rtc_gpio_input_disable(gpio_num)); + ADC1_CHECK_FUNCTION_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED)); ADC2_CHECK_FUNCTION_RET(gpio_set_pull_mode(gpio_num, GPIO_FLOATING)); return ESP_OK; } @@ -2107,8 +1668,7 @@ esp_err_t adc2_vref_to_gpio(gpio_num_t gpio) //Configure RTC gpio rtc_gpio_init(gpio); - rtc_gpio_output_disable(gpio); - rtc_gpio_input_disable(gpio); + rtc_gpio_set_direction(gpio, RTC_GPIO_MODE_DISABLED); rtc_gpio_pullup_dis(gpio); rtc_gpio_pulldown_dis(gpio); //force fsm @@ -2157,8 +1717,7 @@ static esp_err_t dac_rtc_pad_init(dac_channel_t channel) gpio_num_t gpio_num = 0; dac_pad_get_io_num(channel, &gpio_num); rtc_gpio_init(gpio_num); - rtc_gpio_output_disable(gpio_num); - rtc_gpio_input_disable(gpio_num); + rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED); rtc_gpio_pullup_dis(gpio_num); rtc_gpio_pulldown_dis(gpio_num); diff --git a/components/driver/test/test_rtcio.c b/components/driver/test/test_rtcio.c new file mode 100644 index 000000000..42b9c69d5 --- /dev/null +++ b/components/driver/test/test_rtcio.c @@ -0,0 +1,216 @@ +/** + * About test environment UT_T1_GPIO: + * Please connect GPIO18 and GPIO19 + */ +#include +#include +#include "esp_system.h" +#include "esp_sleep.h" +#include "unity.h" +#include "driver/gpio.h" +#include "driver/rtc_io.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/queue.h" +#include "esp_err.h" +#include "esp_log.h" +#include "soc/rtc_io_periph.h" + +#define RTCIO_CHECK(condition) TEST_ASSERT_MESSAGE((condition == ESP_OK), "ret is not ESP_OK") +#define RTCIO_VERIFY(condition, msg) TEST_ASSERT_MESSAGE((condition), msg) + +#define TEST_COUNT 10 +static const char *TAG = "rtcio_test"; + +/* + * Test output/input function. + */ +TEST_CASE("RTCIO input/output test", "[rtcio]") +{ + ESP_LOGI(TAG, "RTCIO input/output test"); + // init rtcio + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { + RTCIO_CHECK( rtc_gpio_init(i) ); + RTCIO_CHECK( rtc_gpio_set_direction(i, RTC_GPIO_MODE_INPUT_OUTPUT) ); + RTCIO_CHECK( rtc_gpio_pullup_dis(i) ); + RTCIO_CHECK( rtc_gpio_pulldown_dis(i) ); + ESP_LOGI(TAG, "gpio %d init", i); + } + } + + for (int cnt = 0; cnt < TEST_COUNT; cnt++) { + uint32_t level = cnt % 2; + ESP_LOGI(TAG, "RTCIO output level %d", level); + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { + RTCIO_CHECK( rtc_gpio_set_level(i, level) ); + vTaskDelay(10 / portTICK_RATE_MS); + if (rtc_gpio_get_level(i) != level) { + ESP_LOGE(TAG, "RTCIO input/output test err, gpio%d", i); + } + } + } + vTaskDelay(100 / portTICK_RATE_MS); + } + + // Deinit rtcio + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { + RTCIO_CHECK( rtc_gpio_deinit(i) ); + } + } + ESP_LOGI(TAG, "RTCIO input/output test over"); +} + +/* + * Test pullup/pulldown function. + * Note: extern circuit should not connect. + */ +TEST_CASE("RTCIO pullup/pulldown test", "[rtcio]") +{ + ESP_LOGI(TAG, "RTCIO pullup/pulldown test"); + // init rtcio + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + int num = rtc_io_number_get(i); + if (rtc_gpio_is_valid_gpio(i) && num > 0 && rtc_io_desc[num].pullup != 0) { + RTCIO_CHECK( rtc_gpio_init(i) ); + RTCIO_CHECK( rtc_gpio_set_direction(i, RTC_GPIO_MODE_INPUT_ONLY) ); + RTCIO_CHECK( rtc_gpio_pullup_dis(i) ); + RTCIO_CHECK( rtc_gpio_pulldown_dis(i) ); + ESP_LOGI(TAG, "gpio %d init", i); + } + } + + for (int cnt = 0; cnt < TEST_COUNT; cnt++) { + uint32_t level = cnt % 2; + ESP_LOGI(TAG, "RTCIO pull level %d", level); + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + int num = rtc_io_number_get(i); + if (rtc_gpio_is_valid_gpio(i) && num > 0 && rtc_io_desc[num].pullup != 0) { + if (level) { + RTCIO_CHECK( rtc_gpio_pulldown_dis(i) ); + RTCIO_CHECK( rtc_gpio_pullup_en(i) ); + } else { + RTCIO_CHECK( rtc_gpio_pullup_dis(i) ); + RTCIO_CHECK( rtc_gpio_pulldown_en(i) ); + } + vTaskDelay(20 / portTICK_RATE_MS); + if (rtc_gpio_get_level(i) != level) { + ESP_LOGE(TAG, "RTCIO pullup/pulldown test err, gpio%d", i); + } + } + } + vTaskDelay(100 / portTICK_RATE_MS); + } + + // Deinit rtcio + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + int num = rtc_io_number_get(i); + if (rtc_gpio_is_valid_gpio(i) && num > 0 && rtc_io_desc[num].pullup != 0) { + RTCIO_CHECK( rtc_gpio_deinit(i) ); + } + } + ESP_LOGI(TAG, "RTCIO pullup/pulldown test over"); +} + +/* + * Test output OD function. + */ +TEST_CASE("RTCIO output OD test", "[rtcio]") +{ + ESP_LOGI(TAG, "RTCIO output OD test"); + // init rtcio + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { + RTCIO_CHECK( rtc_gpio_init(i) ); + RTCIO_CHECK( rtc_gpio_set_direction(i, RTC_GPIO_MODE_INPUT_OUTPUT_OD) ); + RTCIO_CHECK( rtc_gpio_pullup_en(i) ); + RTCIO_CHECK( rtc_gpio_pulldown_dis(i) ); + ESP_LOGI(TAG, "gpio %d init", i); + } + } + + for (int cnt = 0; cnt < TEST_COUNT; cnt++) { + uint32_t level = cnt % 2; + ESP_LOGI(TAG, "RTCIO output level %d", level); + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { + RTCIO_CHECK( rtc_gpio_set_level(i, level) ); + vTaskDelay(10 / portTICK_RATE_MS); + if (rtc_gpio_get_level(i) != level) { + ESP_LOGE(TAG, "RTCIO output OD test err, gpio%d", i); + } + } + } + vTaskDelay(100 / portTICK_RATE_MS); + } + + // Deinit rtcio + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { + RTCIO_CHECK( rtc_gpio_deinit(i) ); + } + } + ESP_LOGI(TAG, "RTCIO output OD test over"); +} + +/* + * Test rtcio hold function. + */ +TEST_CASE("RTCIO output hold test", "[rtcio]") +{ + ESP_LOGI(TAG, "RTCIO output hold test"); + // init rtcio + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { + RTCIO_CHECK( rtc_gpio_init(i) ); + RTCIO_CHECK( rtc_gpio_set_direction(i, RTC_GPIO_MODE_INPUT_OUTPUT_OD) ); + RTCIO_CHECK( rtc_gpio_pullup_en(i) ); + RTCIO_CHECK( rtc_gpio_pulldown_dis(i) ); + RTCIO_CHECK( rtc_gpio_set_level(i, 1) ); + ESP_LOGI(TAG, "gpio %d init, level 1", i); + } + } + + // hold all output rtcio. + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { + RTCIO_CHECK( rtc_gpio_hold_en(i) ); + vTaskDelay(10 / portTICK_RATE_MS); + RTCIO_CHECK( rtc_gpio_set_level(i, 0) ); + ESP_LOGI(TAG, "RTCIO output pin hold, then set level 0"); + vTaskDelay(10 / portTICK_RATE_MS); + if (rtc_gpio_get_level(i) == 0) { + ESP_LOGE(TAG, "RTCIO hold test err, gpio%d", i); + } + } + } + + //unhold all rtcio. + rtc_gpio_force_hold_dis_all(); + + // check the unhold status + for (int cnt = 0; cnt < 4; cnt++) { + uint32_t level = cnt % 2; + ESP_LOGI(TAG, "RTCIO output level %d", level); + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { + RTCIO_CHECK( rtc_gpio_set_level(i, level) ); + vTaskDelay(10 / portTICK_RATE_MS); + if (rtc_gpio_get_level(i) != level) { + ESP_LOGE(TAG, "RTCIO output OD test err, gpio%d", i); + } + } + } + vTaskDelay(100 / portTICK_RATE_MS); + } + + // Deinit rtcio + for (int i = 0; i < GPIO_PIN_COUNT; i++) { + if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { + RTCIO_CHECK( rtc_gpio_deinit(i) ); + } + } + ESP_LOGI(TAG, "RTCIO hold test over"); +} \ No newline at end of file diff --git a/components/esp32/sleep_modes.c b/components/esp32/sleep_modes.c index 86c209162..f280396b0 100644 --- a/components/esp32/sleep_modes.c +++ b/components/esp32/sleep_modes.c @@ -469,7 +469,7 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level) ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP"); return ESP_ERR_INVALID_STATE; } - s_config.ext0_rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num; + s_config.ext0_rtc_gpio_num = rtc_io_number_get(gpio_num); s_config.ext0_trigger_level = level; s_config.wakeup_triggers |= RTC_EXT0_TRIG_EN; return ESP_OK; @@ -483,16 +483,11 @@ static void ext0_wakeup_prepare(void) // Set level which will trigger wakeup SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, s_config.ext0_trigger_level, RTC_CNTL_EXT_WAKEUP0_LV_S); - // Find GPIO descriptor in the rtc_gpio_desc table and configure the pad - for (size_t gpio_num = 0; gpio_num < GPIO_PIN_COUNT; ++gpio_num) { - const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio_num]; - if (desc->rtc_num == rtc_gpio_num) { - REG_SET_BIT(desc->reg, desc->mux); - SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func); - REG_SET_BIT(desc->reg, desc->ie); - break; - } - } + // Find GPIO descriptor in the rtc_io_desc table and configure the pad + const rtc_io_desc_t* desc = &rtc_io_desc[rtc_gpio_num]; + REG_SET_BIT(desc->reg, desc->mux); + SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func); + REG_SET_BIT(desc->reg, desc->ie); } esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode_t mode) @@ -510,7 +505,7 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode ESP_LOGE(TAG, "Not an RTC IO: GPIO%d", gpio); return ESP_ERR_INVALID_ARG; } - rtc_gpio_mask |= BIT(rtc_gpio_desc[gpio].rtc_num); + rtc_gpio_mask |= BIT(rtc_io_number_get(gpio)); } s_config.ext1_rtc_gpio_mask = rtc_gpio_mask; s_config.ext1_trigger_mode = mode; @@ -523,11 +518,11 @@ static void ext1_wakeup_prepare(void) // Configure all RTC IOs selected as ext1 wakeup inputs uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask; for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) { - int rtc_pin = rtc_gpio_desc[gpio].rtc_num; + int rtc_pin = rtc_io_number_get(gpio); if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) { continue; } - const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio]; + const rtc_io_desc_t* desc = &rtc_io_desc[rtc_pin]; // Route pad to RTC REG_SET_BIT(desc->reg, desc->mux); SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func); @@ -566,7 +561,7 @@ uint64_t esp_sleep_get_ext1_wakeup_status(void) if (!RTC_GPIO_IS_VALID_GPIO(gpio)) { continue; } - int rtc_pin = rtc_gpio_desc[gpio].rtc_num; + int rtc_pin = rtc_io_number_get(gpio); if ((status & BIT(rtc_pin)) == 0) { continue; } diff --git a/components/esp32/test/test_pm.c b/components/esp32/test/test_pm.c index 2f17202f1..1f929185c 100644 --- a/components/esp32/test/test_pm.c +++ b/components/esp32/test/test_pm.c @@ -155,12 +155,12 @@ TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm]") TEST_ESP_OK(ulp_process_macros_and_load(0, ulp_code, &size)); light_sleep_enable(); - + int rtcio_num = rtc_io_number_get(ext1_wakeup_gpio); for (int i = 0; i < 10; ++i) { /* Set GPIO low */ - REG_CLR_BIT(rtc_gpio_desc[ext1_wakeup_gpio].reg, rtc_gpio_desc[ext1_wakeup_gpio].hold_force); + REG_CLR_BIT(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].hold_force); rtc_gpio_set_level(ext1_wakeup_gpio, 0); - REG_SET_BIT(rtc_gpio_desc[ext1_wakeup_gpio].reg, rtc_gpio_desc[ext1_wakeup_gpio].hold_force); + REG_SET_BIT(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].hold_force); /* Wait for the next tick */ vTaskDelay(1); @@ -186,7 +186,7 @@ TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm]") TEST_ASSERT_INT32_WITHIN(2 * portTICK_PERIOD_MS * 1000, delay_ms * 1000, end_hs - start_hs); TEST_ASSERT_INT32_WITHIN(2 * portTICK_PERIOD_MS * 1000, delay_ms * 1000, end_rtc - start_rtc); } - REG_CLR_BIT(rtc_gpio_desc[ext1_wakeup_gpio].reg, rtc_gpio_desc[ext1_wakeup_gpio].hold_force); + REG_CLR_BIT(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].hold_force); rtc_gpio_deinit(ext1_wakeup_gpio); light_sleep_disable(); diff --git a/components/esp32s2beta/sleep_modes.c b/components/esp32s2beta/sleep_modes.c index f0c5bd24d..bfad81f15 100644 --- a/components/esp32s2beta/sleep_modes.c +++ b/components/esp32s2beta/sleep_modes.c @@ -416,7 +416,7 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level) ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP"); return ESP_ERR_INVALID_STATE; } - s_config.ext0_rtc_gpio_num = gpio_num; + s_config.ext0_rtc_gpio_num = rtc_io_number_get(gpio_num); s_config.ext0_trigger_level = level; s_config.wakeup_triggers |= RTC_EXT0_TRIG_EN; return ESP_OK; @@ -430,15 +430,11 @@ static void ext0_wakeup_prepare(void) // Set level which will trigger wakeup SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, s_config.ext0_trigger_level, RTC_CNTL_EXT_WAKEUP0_LV_S); - // Find GPIO descriptor in the rtc_gpio_reg table and configure the pad - for (size_t gpio_num = 0; gpio_num < GPIO_PIN_COUNT; ++gpio_num) { - if (gpio_num == rtc_gpio_num && RTC_GPIO_IS_VALID_GPIO(gpio_num)) { - rtc_gpio_reg[gpio_num]->mux_sel = 1; - rtc_gpio_reg[gpio_num]->fun_sel = 0; - rtc_gpio_reg[gpio_num]->fun_ie = 1; - break; - } - } + // Find GPIO descriptor in the rtc_io_desc table and configure the pad + const rtc_io_desc_t* desc = &rtc_io_desc[rtc_gpio_num]; + REG_SET_BIT(desc->reg, desc->mux); + SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func); + REG_SET_BIT(desc->reg, desc->ie); } esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode_t mode) @@ -456,7 +452,7 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode ESP_LOGE(TAG, "Not an RTC IO: GPIO%d", gpio); return ESP_ERR_INVALID_ARG; } - rtc_gpio_mask |= BIT(gpio); + rtc_gpio_mask |= BIT(rtc_io_number_get(gpio)); } s_config.ext1_rtc_gpio_mask = rtc_gpio_mask; s_config.ext1_trigger_mode = mode; @@ -469,27 +465,27 @@ static void ext1_wakeup_prepare(void) // Configure all RTC IOs selected as ext1 wakeup inputs uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask; for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) { - if(!RTC_GPIO_IS_VALID_GPIO(gpio)) { - continue; - } - if ((rtc_gpio_mask & BIT(gpio)) == 0) { + int rtc_pin = rtc_io_number_get(gpio); + if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) { continue; } + const rtc_io_desc_t* desc = &rtc_io_desc[rtc_pin]; // Route pad to RTC - rtc_gpio_reg[gpio]->mux_sel = 1; - rtc_gpio_reg[gpio]->fun_sel = 0; + REG_SET_BIT(desc->reg, desc->mux); + SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func); // set input enable in sleep mode - rtc_gpio_reg[gpio]->fun_ie = 1; + REG_SET_BIT(desc->reg, desc->ie); // Pad configuration depends on RTC_PERIPH state in sleep mode if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) { // RTC_PERIPH will be powered down, so RTC_IO_ registers will // loose their state. Lock pad configuration. // Pullups/pulldowns also need to be disabled. - rtc_gpio_reg[gpio]->rue = 0; - rtc_gpio_reg[gpio]->rde = 0; + REG_CLR_BIT(desc->reg, desc->pulldown); + REG_CLR_BIT(desc->reg, desc->pullup); + REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, desc->hold_force); } // Keep track of pins which are processed to bail out early - rtc_gpio_mask &= ~BIT(gpio); + rtc_gpio_mask &= ~BIT(rtc_pin); } // Clear state from previous wakeup REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); @@ -512,7 +508,7 @@ uint64_t esp_sleep_get_ext1_wakeup_status(void) if (!RTC_GPIO_IS_VALID_GPIO(gpio)) { continue; } - int rtc_pin = gpio; + int rtc_pin = rtc_io_number_get(gpio); if ((status & BIT(rtc_pin)) == 0) { continue; } diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 245b84342..dff818fbb 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -13,6 +13,7 @@ list(APPEND srcs "src/memory_layout_utils.c" "src/lldesc.c" "src/hal/rmt_hal.c" + "src/hal/rtc_io_hal.c" "src/hal/spi_hal.c" "src/hal/spi_hal_iram.c" "src/hal/spi_slave_hal.c" diff --git a/components/soc/esp32/include/hal/rtc_io_ll.h b/components/soc/esp32/include/hal/rtc_io_ll.h new file mode 100644 index 000000000..760c1d90c --- /dev/null +++ b/components/soc/esp32/include/hal/rtc_io_ll.h @@ -0,0 +1,348 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include +#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_types.h" + +typedef enum { + RTCIO_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */ + RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ +} rtcio_ll_func_t; + +typedef enum { + RTCIO_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */ + RTCIO_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */ + RTCIO_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */ +} rtcio_ll_wake_type_t; + +typedef enum { + RTCIO_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */ + RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */ +} rtcio_ll_out_mode_t; + +/** + * @brief Select the rtcio function. + * + * @note The RTC function must be selected before the pad analog function is enabled. + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param func Select pin function. + */ +static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) +{ + if (func == RTCIO_FUNC_RTC) { + // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. + SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux)); + //0:RTC FUNCTION 1,2,3:Reserved + SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[rtcio_num].func); + } else if (func == RTCIO_FUNC_DIGITAL) { + CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux)); + } +} + +/** + * Enable rtcio output. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_output_enable(int rtcio_num) +{ + RTCIO.enable_w1ts.w1ts = (1U << rtcio_num); +} + +/** + * Disable rtcio output. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_output_disable(int rtcio_num) +{ + RTCIO.enable_w1tc.w1tc = (1U << rtcio_num); +} + +/** + * Set RTCIO output level. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param level 0: output low; ~0: output high. + */ +static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) +{ + if (level) { + RTCIO.out_w1ts.w1ts = (1U << rtcio_num); + } else { + RTCIO.out_w1tc.w1tc = (1U << rtcio_num); + } +} + +/** + * Enable rtcio input. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_input_enable(int rtcio_num) +{ + SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].ie); +} + +/** + * Disable rtcio input. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_input_disable(int rtcio_num) +{ + CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].ie); +} + +/** + * Get RTCIO input level. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return 0: input low; ~0: input high. + */ +static inline uint32_t rtcio_ll_get_level(int rtcio_num) +{ + return (uint32_t)(RTCIO.in_val.in >> rtcio_num) & 0x1; +} + +/** + * @brief Set RTC GPIO pad drive capability + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param strength Drive capability of the pad. Range: 0 ~ 3. + */ +static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strength) +{ + if (rtc_io_desc[rtcio_num].drv_v) { + SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].drv_v, strength, rtc_io_desc[rtcio_num].drv_s); + } +} + +/** + * @brief Get RTC GPIO pad drive capability. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Drive capability of the pad. Range: 0 ~ 3. + */ +static inline uint32_t rtcio_ll_get_drive_capability(int rtcio_num) +{ + return GET_PERI_REG_BITS2(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].drv_v, rtc_io_desc[rtcio_num].drv_s); +} + +/** + * @brief Set RTC GPIO pad output mode. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return mode Output mode. + */ +static inline void rtcio_ll_output_mode_set(int rtcio_num, rtcio_ll_out_mode_t mode) +{ + RTCIO.pin[rtcio_num].pad_driver = mode; +} + +/** + * RTC GPIO pullup enable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pullup_enable(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pullup) { + SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup); + } +} + +/** + * RTC GPIO pullup disable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pullup_disable(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pullup) { + CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup); + } +} + +/** + * RTC GPIO pulldown enable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pulldown_enable(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pulldown) { + SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pulldown); + } +} + +/** + * RTC GPIO pulldown disable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pulldown_disable(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pulldown) { + CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pulldown); + } +} + +/** + * Enable force hold function for RTC IO pad. + * + * Enabling HOLD function will cause the pad to lock current status, such as, + * input/output enable, input/output value, function, drive strength values. + * This function is useful when going into light or deep sleep mode to prevent + * the pin configuration from changing. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_force_hold_enable(int rtcio_num) +{ + REG_SET_BIT(RTC_CNTL_HOLD_FORCE_REG, rtc_io_desc[rtcio_num].hold_force); +} + +/** + * Disable hold function on an RTC IO pad + * + * @note If disable the pad hold, the status of pad maybe changed in sleep mode. + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_force_hold_disable(int rtcio_num) +{ + REG_CLR_BIT(RTC_CNTL_HOLD_FORCE_REG, rtc_io_desc[rtcio_num].hold_force); +} + +/** + * Enable force hold function for RTC IO pad. + * + * Enabling HOLD function will cause the pad to lock current status, such as, + * input/output enable, input/output value, function, drive strength values. + * This function is useful when going into light or deep sleep mode to prevent + * the pin configuration from changing. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_force_hold_all(void) +{ + SET_PERI_REG_BITS(RTC_CNTL_HOLD_FORCE_REG, 0x3FFFF, 0x3FFFF, 0); +} + +/** + * Disable hold function on an RTC IO pad + * + * @note If disable the pad hold, the status of pad maybe changed in sleep mode. + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_force_unhold_all(void) +{ + SET_PERI_REG_BITS(RTC_CNTL_HOLD_FORCE_REG, 0x3FFFF, 0, 0); +} + +/** + * Enable wakeup function and set wakeup type from light sleep status for rtcio. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param type Wakeup on high level or low level. + */ +static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type) +{ + RTCIO.pin[rtcio_num].wakeup_enable = 0x1; + RTCIO.pin[rtcio_num].int_type = type; +} + +/** + * Disable wakeup function from light sleep status for rtcio. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_wakeup_disable(int rtcio_num) +{ + RTCIO.pin[rtcio_num].wakeup_enable = 0; + RTCIO.pin[rtcio_num].int_type = RTCIO_WAKEUP_DISABLE; +} + +/** + * Enable rtc io output in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num) +{ + if (rtc_io_desc[gpio_num].slpoe) { + SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe); + } +} + +/** + * Disable rtc io output in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_in_sleep_disable_output(gpio_num_t gpio_num) +{ + if (rtc_io_desc[gpio_num].slpoe) { + CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe); + } +} + +/** + * Enable rtc io input in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_in_sleep_enable_input(gpio_num_t gpio_num) +{ + SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie); +} + +/** + * Disable rtc io input in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_in_sleep_disable_input(gpio_num_t gpio_num) +{ + CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie); +} + +/** + * Enable rtc io keep another setting in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num) +{ + SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel); +} + +/** + * Disable rtc io keep another setting in deep sleep. (Default) + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num) +{ + CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel); +} \ No newline at end of file diff --git a/components/soc/esp32/include/soc/rtc_io_caps.h b/components/soc/esp32/include/soc/rtc_io_caps.h new file mode 100644 index 000000000..29d4ec645 --- /dev/null +++ b/components/soc/esp32/include/soc/rtc_io_caps.h @@ -0,0 +1,21 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_RTC_IO_CAPS_H_ +#define _SOC_RTC_IO_CAPS_H_ + +#define SOC_RTC_IO_PIN_COUNT 18 +#define SOC_PIN_FUNC_RTC_IO 0 + +#endif \ No newline at end of file diff --git a/components/soc/esp32/include/soc/rtc_gpio_channel.h b/components/soc/esp32/include/soc/rtc_io_channel.h similarity index 97% rename from components/soc/esp32/include/soc/rtc_gpio_channel.h rename to components/soc/esp32/include/soc/rtc_io_channel.h index 2a87209e1..2a5b42586 100644 --- a/components/soc/esp32/include/soc/rtc_gpio_channel.h +++ b/components/soc/esp32/include/soc/rtc_io_channel.h @@ -12,8 +12,8 @@ // See the License for the specific language governing permissions and // limitations under the License. -#ifndef _SOC_RTC_GPIO_CHANNEL_H -#define _SOC_RTC_GPIO_CHANNEL_H +#ifndef _SOC_RTC_IO_CHANNEL_H +#define _SOC_RTC_IO_CHANNEL_H #define RTC_GPIO_NUMBER 18 diff --git a/components/soc/esp32/rtc_io_periph.c b/components/soc/esp32/rtc_io_periph.c new file mode 100644 index 000000000..6ec58f666 --- /dev/null +++ b/components/soc/esp32/rtc_io_periph.c @@ -0,0 +1,128 @@ +// Copyright 2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/rtc_io_periph.h" + +const int rtc_io_num_map[GPIO_PIN_COUNT] = { + RTCIO_GPIO0_CHANNEL, //GPIO0 + -1,//GPIO1 + RTCIO_GPIO2_CHANNEL, //GPIO2 + -1,//GPIO3 + RTCIO_GPIO4_CHANNEL, //GPIO4 + -1,//GPIO5 + -1,//GPIO6 + -1,//GPIO7 + -1,//GPIO8 + -1,//GPIO9 + -1,//GPIO10 + -1,//GPIO11 + RTCIO_GPIO12_CHANNEL, //GPIO12 + RTCIO_GPIO13_CHANNEL, //GPIO13 + RTCIO_GPIO14_CHANNEL, //GPIO14 + RTCIO_GPIO15_CHANNEL, //GPIO15 + -1,//GPIO16 + -1,//GPIO17 + -1,//GPIO18 + -1,//GPIO19 + -1,//GPIO20 + -1,//GPIO21 + -1,//GPIO22 + -1,//GPIO23 + -1,//GPIO24 + RTCIO_GPIO25_CHANNEL, //GPIO25 + RTCIO_GPIO26_CHANNEL, //GPIO26 + RTCIO_GPIO27_CHANNEL, //GPIO27 + -1,//GPIO28 + -1,//GPIO29 + -1,//GPIO30 + -1,//GPIO31 + RTCIO_GPIO32_CHANNEL, //GPIO32 + RTCIO_GPIO33_CHANNEL, //GPIO33 + RTCIO_GPIO34_CHANNEL, //GPIO34 + RTCIO_GPIO35_CHANNEL, //GPIO35 + RTCIO_GPIO36_CHANNEL, //GPIO36 + RTCIO_GPIO37_CHANNEL, //GPIO37 + RTCIO_GPIO38_CHANNEL, //GPIO38 + RTCIO_GPIO39_CHANNEL, //GPIO39 +}; + +//Reg,Mux,Fun,IE,Up,Down,Rtc_number +const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT] = { + /*REG MUX select function select Input enable Pullup Pulldown Sleep select Sleep input enable PAD hold Pad force hold Mask of drive capability Offset gpio number */ + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M, RTC_IO_SENSE1_FUN_SEL_S, RTC_IO_SENSE1_FUN_IE_M, 0, 0, RTC_IO_SENSE1_SLP_SEL_M, RTC_IO_SENSE1_SLP_IE_M, 0, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE1_HOLD_FORCE_M, 0, 0, RTCIO_CHANNEL_0_GPIO_NUM}, //36 + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, RTC_IO_SENSE2_SLP_SEL_M, RTC_IO_SENSE2_SLP_IE_M, 0, RTC_IO_SENSE2_HOLD_M, RTC_CNTL_SENSE2_HOLD_FORCE_M, 0, 0, RTCIO_CHANNEL_1_GPIO_NUM}, //37 + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE3_MUX_SEL_M, RTC_IO_SENSE3_FUN_SEL_S, RTC_IO_SENSE3_FUN_IE_M, 0, 0, RTC_IO_SENSE3_SLP_SEL_M, RTC_IO_SENSE3_SLP_IE_M, 0, RTC_IO_SENSE3_HOLD_M, RTC_CNTL_SENSE3_HOLD_FORCE_M, 0, 0, RTCIO_CHANNEL_2_GPIO_NUM}, //38 + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE4_MUX_SEL_M, RTC_IO_SENSE4_FUN_SEL_S, RTC_IO_SENSE4_FUN_IE_M, 0, 0, RTC_IO_SENSE4_SLP_SEL_M, RTC_IO_SENSE4_SLP_IE_M, 0, RTC_IO_SENSE4_HOLD_M, RTC_CNTL_SENSE4_HOLD_FORCE_M, 0, 0, RTCIO_CHANNEL_3_GPIO_NUM}, //39 + {RTC_IO_ADC_PAD_REG, RTC_IO_ADC1_MUX_SEL_M, RTC_IO_ADC1_FUN_SEL_S, RTC_IO_ADC1_FUN_IE_M, 0, 0, RTC_IO_ADC1_SLP_SEL_M, RTC_IO_ADC1_SLP_IE_M, 0, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC1_HOLD_FORCE_M, 0, 0, RTCIO_CHANNEL_4_GPIO_NUM}, //34 + {RTC_IO_ADC_PAD_REG, RTC_IO_ADC2_MUX_SEL_M, RTC_IO_ADC2_FUN_SEL_S, RTC_IO_ADC2_FUN_IE_M, 0, 0, RTC_IO_ADC2_SLP_SEL_M, RTC_IO_ADC2_SLP_IE_M, 0, RTC_IO_ADC2_HOLD_M, RTC_CNTL_ADC2_HOLD_FORCE_M, 0, 0, RTCIO_CHANNEL_5_GPIO_NUM}, //35 + {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, RTC_IO_PDAC1_SLP_SEL_M, RTC_IO_PDAC1_SLP_IE_M, 0, RTC_IO_PDAC1_HOLD_M, RTC_CNTL_PDAC1_HOLD_FORCE_M, RTC_IO_PDAC1_DRV_V, RTC_IO_PDAC1_DRV_S, RTCIO_CHANNEL_6_GPIO_NUM}, //25 + {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, RTC_IO_PDAC2_SLP_SEL_M, RTC_IO_PDAC2_SLP_IE_M, 0, RTC_IO_PDAC2_HOLD_M, RTC_CNTL_PDAC2_HOLD_FORCE_M, RTC_IO_PDAC2_DRV_V, RTC_IO_PDAC2_DRV_S, RTCIO_CHANNEL_7_GPIO_NUM}, //26 + {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, 0, RTC_IO_X32N_HOLD_M, RTC_CNTL_X32N_HOLD_FORCE_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, RTCIO_CHANNEL_8_GPIO_NUM}, //33 + {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, 0, RTC_IO_X32P_HOLD_M, RTC_CNTL_X32P_HOLD_FORCE_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, RTCIO_CHANNEL_9_GPIO_NUM}, //32 + {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, 0, RTC_IO_TOUCH_PAD0_HOLD_M, RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_CHANNEL_10_GPIO_NUM},// 4 + {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, 0, RTC_IO_TOUCH_PAD1_HOLD_M, RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_CHANNEL_11_GPIO_NUM},// 0 + {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, RTC_IO_TOUCH_PAD2_SLP_SEL_M, RTC_IO_TOUCH_PAD2_SLP_IE_M, 0, RTC_IO_TOUCH_PAD2_HOLD_M, RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M, RTC_IO_TOUCH_PAD2_DRV_V, RTC_IO_TOUCH_PAD2_DRV_S, RTCIO_CHANNEL_12_GPIO_NUM},// 2 + {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, RTC_IO_TOUCH_PAD3_SLP_SEL_M, RTC_IO_TOUCH_PAD3_SLP_IE_M, 0, RTC_IO_TOUCH_PAD3_HOLD_M, RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M, RTC_IO_TOUCH_PAD3_DRV_V, RTC_IO_TOUCH_PAD3_DRV_S, RTCIO_CHANNEL_13_GPIO_NUM},//15 + {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, RTC_IO_TOUCH_PAD4_SLP_SEL_M, RTC_IO_TOUCH_PAD4_SLP_IE_M, 0, RTC_IO_TOUCH_PAD4_HOLD_M, RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M, RTC_IO_TOUCH_PAD4_DRV_V, RTC_IO_TOUCH_PAD4_DRV_S, RTCIO_CHANNEL_14_GPIO_NUM},//13 + {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, RTC_IO_TOUCH_PAD5_SLP_SEL_M, RTC_IO_TOUCH_PAD5_SLP_IE_M, 0, RTC_IO_TOUCH_PAD5_HOLD_M, RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M, RTC_IO_TOUCH_PAD5_DRV_V, RTC_IO_TOUCH_PAD5_DRV_S, RTCIO_CHANNEL_15_GPIO_NUM},//12 + {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, 0, RTC_IO_TOUCH_PAD6_HOLD_M, RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_CHANNEL_16_GPIO_NUM},//14 + {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, 0, RTC_IO_TOUCH_PAD7_HOLD_M, RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_CHANNEL_17_GPIO_NUM},//27 +}; + +#ifdef CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC +//Reg,Mux,Fun,IE,Up,Down,Rtc_number +const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT] = { + {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_HOLD_M, RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_GPIO0_CHANNEL}, //0 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //1 + {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, RTC_IO_TOUCH_PAD2_SLP_SEL_M, RTC_IO_TOUCH_PAD2_SLP_IE_M, RTC_IO_TOUCH_PAD2_HOLD_M, RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M, RTC_IO_TOUCH_PAD2_DRV_V, RTC_IO_TOUCH_PAD2_DRV_S, RTCIO_GPIO2_CHANNEL}, //2 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //3 + {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_HOLD_M, RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_GPIO4_CHANNEL}, //4 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //5 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //6 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //7 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //8 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //9 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //10 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //11 + {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, RTC_IO_TOUCH_PAD5_SLP_SEL_M, RTC_IO_TOUCH_PAD5_SLP_IE_M, RTC_IO_TOUCH_PAD5_HOLD_M, RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M, RTC_IO_TOUCH_PAD5_DRV_V, RTC_IO_TOUCH_PAD5_DRV_S, RTCIO_GPIO12_CHANNEL}, //12 + {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, RTC_IO_TOUCH_PAD4_SLP_SEL_M, RTC_IO_TOUCH_PAD4_SLP_IE_M, RTC_IO_TOUCH_PAD4_HOLD_M, RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M, RTC_IO_TOUCH_PAD4_DRV_V, RTC_IO_TOUCH_PAD4_DRV_S, RTCIO_GPIO13_CHANNEL}, //13 + {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, RTC_IO_TOUCH_PAD6_HOLD_M, RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_GPIO14_CHANNEL}, //14 + {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, RTC_IO_TOUCH_PAD3_SLP_SEL_M, RTC_IO_TOUCH_PAD3_SLP_IE_M, RTC_IO_TOUCH_PAD3_HOLD_M, RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M, RTC_IO_TOUCH_PAD3_DRV_V, RTC_IO_TOUCH_PAD3_DRV_S, RTCIO_GPIO15_CHANNEL}, //15 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //16 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //17 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //18 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //19 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //20 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //21 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //22 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //23 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //24 + {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, RTC_IO_PDAC1_SLP_SEL_M, RTC_IO_PDAC1_SLP_IE_M, RTC_IO_PDAC1_HOLD_M, RTC_CNTL_PDAC1_HOLD_FORCE_M, RTC_IO_PDAC1_DRV_V, RTC_IO_PDAC1_DRV_S, RTCIO_GPIO25_CHANNEL}, //25 + {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, RTC_IO_PDAC2_SLP_SEL_M, RTC_IO_PDAC2_SLP_IE_M, RTC_IO_PDAC2_HOLD_M, RTC_CNTL_PDAC2_HOLD_FORCE_M, RTC_IO_PDAC2_DRV_V, RTC_IO_PDAC2_DRV_S, RTCIO_GPIO26_CHANNEL}, //26 + {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, RTC_IO_TOUCH_PAD7_HOLD_M, RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_GPIO27_CHANNEL}, //27 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //28 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //29 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //30 + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //31 + {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, RTC_IO_X32P_HOLD_M, RTC_CNTL_X32P_HOLD_FORCE_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, RTCIO_GPIO32_CHANNEL}, //32 + {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, RTC_IO_X32N_HOLD_M, RTC_CNTL_X32N_HOLD_FORCE_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, RTCIO_GPIO33_CHANNEL}, //33 + {RTC_IO_ADC_PAD_REG, RTC_IO_ADC1_MUX_SEL_M, RTC_IO_ADC1_FUN_SEL_S, RTC_IO_ADC1_FUN_IE_M, 0, 0, RTC_IO_ADC1_SLP_SEL_M, RTC_IO_ADC1_SLP_IE_M, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO34_CHANNEL}, //34 + {RTC_IO_ADC_PAD_REG, RTC_IO_ADC2_MUX_SEL_M, RTC_IO_ADC2_FUN_SEL_S, RTC_IO_ADC2_FUN_IE_M, 0, 0, RTC_IO_ADC2_SLP_SEL_M, RTC_IO_ADC2_SLP_IE_M, RTC_IO_ADC2_HOLD_M, RTC_CNTL_ADC2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO35_CHANNEL}, //35 + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M, RTC_IO_SENSE1_FUN_SEL_S, RTC_IO_SENSE1_FUN_IE_M, 0, 0, RTC_IO_SENSE1_SLP_SEL_M, RTC_IO_SENSE1_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO36_CHANNEL}, //36 + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, RTC_IO_SENSE2_SLP_SEL_M, RTC_IO_SENSE2_SLP_IE_M, RTC_IO_SENSE2_HOLD_M, RTC_CNTL_SENSE2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO37_CHANNEL}, //37 + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE3_MUX_SEL_M, RTC_IO_SENSE3_FUN_SEL_S, RTC_IO_SENSE3_FUN_IE_M, 0, 0, RTC_IO_SENSE3_SLP_SEL_M, RTC_IO_SENSE3_SLP_IE_M, RTC_IO_SENSE3_HOLD_M, RTC_CNTL_SENSE3_HOLD_FORCE_M, 0, 0, RTCIO_GPIO38_CHANNEL}, //38 + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE4_MUX_SEL_M, RTC_IO_SENSE4_FUN_SEL_S, RTC_IO_SENSE4_FUN_IE_M, 0, 0, RTC_IO_SENSE4_SLP_SEL_M, RTC_IO_SENSE4_SLP_IE_M, RTC_IO_SENSE4_HOLD_M, RTC_CNTL_SENSE4_HOLD_FORCE_M, 0, 0, RTCIO_GPIO39_CHANNEL}, //39 +}; + +#endif //CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC diff --git a/components/soc/esp32/rtc_periph.c b/components/soc/esp32/rtc_periph.c index 36439362c..e69de29bb 100644 --- a/components/soc/esp32/rtc_periph.c +++ b/components/soc/esp32/rtc_periph.c @@ -1,59 +0,0 @@ -// Copyright 2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include "soc/rtc_periph.h" - -//Reg,Mux,Fun,IE,Up,Down,Rtc_number -const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT] = { - {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_HOLD_M, RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_GPIO0_CHANNEL}, //0 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //1 - {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, RTC_IO_TOUCH_PAD2_SLP_SEL_M, RTC_IO_TOUCH_PAD2_SLP_IE_M, RTC_IO_TOUCH_PAD2_HOLD_M, RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M, RTC_IO_TOUCH_PAD2_DRV_V, RTC_IO_TOUCH_PAD2_DRV_S, RTCIO_GPIO2_CHANNEL}, //2 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //3 - {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_HOLD_M, RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_GPIO4_CHANNEL}, //4 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //5 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //6 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //7 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //8 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //9 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //10 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //11 - {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, RTC_IO_TOUCH_PAD5_SLP_SEL_M, RTC_IO_TOUCH_PAD5_SLP_IE_M, RTC_IO_TOUCH_PAD5_HOLD_M, RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M, RTC_IO_TOUCH_PAD5_DRV_V, RTC_IO_TOUCH_PAD5_DRV_S, RTCIO_GPIO12_CHANNEL}, //12 - {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, RTC_IO_TOUCH_PAD4_SLP_SEL_M, RTC_IO_TOUCH_PAD4_SLP_IE_M, RTC_IO_TOUCH_PAD4_HOLD_M, RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M, RTC_IO_TOUCH_PAD4_DRV_V, RTC_IO_TOUCH_PAD4_DRV_S, RTCIO_GPIO13_CHANNEL}, //13 - {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, RTC_IO_TOUCH_PAD6_HOLD_M, RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_GPIO14_CHANNEL}, //14 - {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, RTC_IO_TOUCH_PAD3_SLP_SEL_M, RTC_IO_TOUCH_PAD3_SLP_IE_M, RTC_IO_TOUCH_PAD3_HOLD_M, RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M, RTC_IO_TOUCH_PAD3_DRV_V, RTC_IO_TOUCH_PAD3_DRV_S, RTCIO_GPIO15_CHANNEL}, //15 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //16 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //17 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //18 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //19 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //20 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //21 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //22 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //23 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //24 - {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, RTC_IO_PDAC1_SLP_SEL_M, RTC_IO_PDAC1_SLP_IE_M, RTC_IO_PDAC1_HOLD_M, RTC_CNTL_PDAC1_HOLD_FORCE_M, RTC_IO_PDAC1_DRV_V, RTC_IO_PDAC1_DRV_S, RTCIO_GPIO25_CHANNEL}, //25 - {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, RTC_IO_PDAC2_SLP_SEL_M, RTC_IO_PDAC2_SLP_IE_M, RTC_IO_PDAC2_HOLD_M, RTC_CNTL_PDAC2_HOLD_FORCE_M, RTC_IO_PDAC2_DRV_V, RTC_IO_PDAC2_DRV_S, RTCIO_GPIO26_CHANNEL}, //26 - {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, RTC_IO_TOUCH_PAD7_HOLD_M, RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_GPIO27_CHANNEL}, //27 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //28 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //29 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //30 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //31 - {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, RTC_IO_X32P_HOLD_M, RTC_CNTL_X32P_HOLD_FORCE_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, RTCIO_GPIO32_CHANNEL}, //32 - {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, RTC_IO_X32N_HOLD_M, RTC_CNTL_X32N_HOLD_FORCE_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, RTCIO_GPIO33_CHANNEL}, //33 - {RTC_IO_ADC_PAD_REG, RTC_IO_ADC1_MUX_SEL_M, RTC_IO_ADC1_FUN_SEL_S, RTC_IO_ADC1_FUN_IE_M, 0, 0, RTC_IO_ADC1_SLP_SEL_M, RTC_IO_ADC1_SLP_IE_M, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO34_CHANNEL}, //34 - {RTC_IO_ADC_PAD_REG, RTC_IO_ADC2_MUX_SEL_M, RTC_IO_ADC2_FUN_SEL_S, RTC_IO_ADC2_FUN_IE_M, 0, 0, RTC_IO_ADC2_SLP_SEL_M, RTC_IO_ADC2_SLP_IE_M, RTC_IO_ADC2_HOLD_M, RTC_CNTL_ADC2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO35_CHANNEL}, //35 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M, RTC_IO_SENSE1_FUN_SEL_S, RTC_IO_SENSE1_FUN_IE_M, 0, 0, RTC_IO_SENSE1_SLP_SEL_M, RTC_IO_SENSE1_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO36_CHANNEL}, //36 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, RTC_IO_SENSE2_SLP_SEL_M, RTC_IO_SENSE2_SLP_IE_M, RTC_IO_SENSE2_HOLD_M, RTC_CNTL_SENSE2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO37_CHANNEL}, //37 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE3_MUX_SEL_M, RTC_IO_SENSE3_FUN_SEL_S, RTC_IO_SENSE3_FUN_IE_M, 0, 0, RTC_IO_SENSE3_SLP_SEL_M, RTC_IO_SENSE3_SLP_IE_M, RTC_IO_SENSE3_HOLD_M, RTC_CNTL_SENSE3_HOLD_FORCE_M, 0, 0, RTCIO_GPIO38_CHANNEL}, //38 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE4_MUX_SEL_M, RTC_IO_SENSE4_FUN_SEL_S, RTC_IO_SENSE4_FUN_IE_M, 0, 0, RTC_IO_SENSE4_SLP_SEL_M, RTC_IO_SENSE4_SLP_IE_M, RTC_IO_SENSE4_HOLD_M, RTC_CNTL_SENSE4_HOLD_FORCE_M, 0, 0, RTCIO_GPIO39_CHANNEL}, //39 -}; diff --git a/components/soc/esp32/sources.cmake b/components/soc/esp32/sources.cmake index 125d3bda0..726389fb7 100644 --- a/components/soc/esp32/sources.cmake +++ b/components/soc/esp32/sources.cmake @@ -3,6 +3,7 @@ set(SOC_SRCS "cpu_util.c" "rtc_clk.c" "rtc_clk_init.c" "rtc_init.c" + "rtc_io_periph.c" "rtc_periph.c" "rtc_pm.c" "rtc_sleep.c" diff --git a/components/soc/esp32s2beta/include/hal/rtc_io_ll.h b/components/soc/esp32s2beta/include/hal/rtc_io_ll.h new file mode 100644 index 000000000..14767873e --- /dev/null +++ b/components/soc/esp32s2beta/include/hal/rtc_io_ll.h @@ -0,0 +1,348 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include +#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_types.h" + +typedef enum { + RTCIO_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */ + RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ +} rtcio_ll_func_t; + +typedef enum { + RTCIO_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */ + RTCIO_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */ + RTCIO_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */ +} rtcio_ll_wake_type_t; + +typedef enum { + RTCIO_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */ + RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */ +} rtcio_ll_out_mode_t; + +/** + * @brief Select the rtcio function. + * + * @note The RTC function must be selected before the pad analog function is enabled. + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param func Select pin function. + */ +static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) +{ + if (func == RTCIO_FUNC_RTC) { + // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. + SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux)); + //0:RTC FUNCTION 1,2,3:Reserved + SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[rtcio_num].func); + } else if (func == RTCIO_FUNC_DIGITAL) { + CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux)); + } +} + +/** + * Enable rtcio output. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_output_enable(int rtcio_num) +{ + RTCIO.enable_w1ts.w1ts = (1U << rtcio_num); +} + +/** + * Disable rtcio output. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_output_disable(int rtcio_num) +{ + RTCIO.enable_w1tc.w1tc = (1U << rtcio_num); +} + +/** + * Set RTCIO output level. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param level 0: output low; ~0: output high. + */ +static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) +{ + if (level) { + RTCIO.out_w1ts.w1ts = (1U << rtcio_num); + } else { + RTCIO.out_w1tc.w1tc = (1U << rtcio_num); + } +} + +/** + * Enable rtcio input. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_input_enable(int rtcio_num) +{ + SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].ie); +} + +/** + * Disable rtcio input. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_input_disable(int rtcio_num) +{ + CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].ie); +} + +/** + * Get RTCIO input level. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return 0: input low; ~0: input high. + */ +static inline uint32_t rtcio_ll_get_level(int rtcio_num) +{ + return (uint32_t)(RTCIO.in_val.in >> rtcio_num) & 0x1; +} + +/** + * @brief Set RTC GPIO pad drive capability + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param strength Drive capability of the pad. Range: 0 ~ 3. + */ +static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strength) +{ + if (rtc_io_desc[rtcio_num].drv_v) { + SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].drv_v, strength, rtc_io_desc[rtcio_num].drv_s); + } +} + +/** + * @brief Get RTC GPIO pad drive capability. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Drive capability of the pad. Range: 0 ~ 3. + */ +static inline uint32_t rtcio_ll_get_drive_capability(int rtcio_num) +{ + return GET_PERI_REG_BITS2(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].drv_v, rtc_io_desc[rtcio_num].drv_s); +} + +/** + * @brief Set RTC GPIO pad output mode. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return mode Output mode. + */ +static inline void rtcio_ll_output_mode_set(int rtcio_num, rtcio_ll_out_mode_t mode) +{ + RTCIO.pin[rtcio_num].pad_driver = mode; +} + +/** + * RTC GPIO pullup enable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pullup_enable(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pullup) { + SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup); + } +} + +/** + * RTC GPIO pullup disable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pullup_disable(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pullup) { + CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup); + } +} + +/** + * RTC GPIO pulldown enable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pulldown_enable(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pulldown) { + SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pulldown); + } +} + +/** + * RTC GPIO pulldown disable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pulldown_disable(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pulldown) { + CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pulldown); + } +} + +/** + * Enable force hold function for RTC IO pad. + * + * Enabling HOLD function will cause the pad to lock current status, such as, + * input/output enable, input/output value, function, drive strength values. + * This function is useful when going into light or deep sleep mode to prevent + * the pin configuration from changing. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_force_hold_enable(int rtcio_num) +{ + SET_PERI_REG_MASK(RTC_CNTL_PAD_HOLD_REG, rtc_io_desc[rtcio_num].hold_force); +} + +/** + * Disable hold function on an RTC IO pad + * + * @note If disable the pad hold, the status of pad maybe changed in sleep mode. + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_force_hold_disable(int rtcio_num) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_PAD_HOLD_REG, rtc_io_desc[rtcio_num].hold_force); +} + +/** + * Enable force hold function for RTC IO pad. + * + * Enabling HOLD function will cause the pad to lock current status, such as, + * input/output enable, input/output value, function, drive strength values. + * This function is useful when going into light or deep sleep mode to prevent + * the pin configuration from changing. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_force_hold_all(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); +} + +/** + * Disable hold function on an RTC IO pad + * + * @note If disable the pad hold, the status of pad maybe changed in sleep mode. + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_force_unhold_all(void) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); +} + +/** + * Enable wakeup function and set wakeup type from light sleep status for rtcio. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param type Wakeup on high level or low level. + */ +static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type) +{ + RTCIO.pin[rtcio_num].wakeup_enable = 0x1; + RTCIO.pin[rtcio_num].int_type = type; +} + +/** + * Disable wakeup function from light sleep status for rtcio. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_wakeup_disable(int rtcio_num) +{ + RTCIO.pin[rtcio_num].wakeup_enable = 0; + RTCIO.pin[rtcio_num].int_type = RTCIO_WAKEUP_DISABLE; +} + +/** + * Enable rtc io output in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num) +{ + if (rtc_io_desc[gpio_num].slpoe) { + SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe); + } +} + +/** + * Disable rtc io output in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_in_sleep_disable_output(gpio_num_t gpio_num) +{ + if (rtc_io_desc[gpio_num].slpoe) { + CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe); + } +} + +/** + * Enable rtc io input in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_in_sleep_enable_input(gpio_num_t gpio_num) +{ + SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie); +} + +/** + * Disable rtc io input in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_in_sleep_disable_input(gpio_num_t gpio_num) +{ + CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie); +} + +/** + * Enable rtc io keep another setting in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num) +{ + SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel); +} + +/** + * Disable rtc io keep another setting in deep sleep. (Default) + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num) +{ + CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel); +} \ No newline at end of file diff --git a/components/soc/esp32s2beta/include/soc/rtc_io_caps.h b/components/soc/esp32s2beta/include/soc/rtc_io_caps.h new file mode 100644 index 000000000..d57a239e2 --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/rtc_io_caps.h @@ -0,0 +1,18 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_RTC_IO_PIN_COUNT 22 +#define SOC_PIN_FUNC_RTC_IO 0 \ No newline at end of file diff --git a/components/soc/esp32s2beta/include/soc/rtc_gpio_channel.h b/components/soc/esp32s2beta/include/soc/rtc_io_channel.h similarity index 98% rename from components/soc/esp32s2beta/include/soc/rtc_gpio_channel.h rename to components/soc/esp32s2beta/include/soc/rtc_io_channel.h index 2c0286611..80ae491e0 100644 --- a/components/soc/esp32s2beta/include/soc/rtc_gpio_channel.h +++ b/components/soc/esp32s2beta/include/soc/rtc_io_channel.h @@ -13,7 +13,7 @@ // limitations under the License. #ifndef _SOC_RTC_GPIO_CHANNEL_H -#define _SOC_RTC_GPIO_CHANNEL_H +#define _SOC_RTC_GPIO_CHANNEL_H #define RTC_GPIO_NUMBER 22 diff --git a/components/soc/esp32s2beta/rtc_io_periph.c b/components/soc/esp32s2beta/rtc_io_periph.c new file mode 100644 index 000000000..92326be96 --- /dev/null +++ b/components/soc/esp32s2beta/rtc_io_periph.c @@ -0,0 +1,93 @@ +// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/rtc_io_periph.h" + +const int rtc_io_num_map[GPIO_PIN_COUNT] = { + RTCIO_GPIO0_CHANNEL, //GPIO0 + RTCIO_GPIO1_CHANNEL, //GPIO1 + RTCIO_GPIO2_CHANNEL, //GPIO2 + RTCIO_GPIO3_CHANNEL, //GPIO3 + RTCIO_GPIO4_CHANNEL, //GPIO4 + RTCIO_GPIO5_CHANNEL, //GPIO5 + RTCIO_GPIO6_CHANNEL, //GPIO6 + RTCIO_GPIO7_CHANNEL, //GPIO7 + RTCIO_GPIO8_CHANNEL, //GPIO8 + RTCIO_GPIO9_CHANNEL, //GPIO9 + RTCIO_GPIO10_CHANNEL, //GPIO10 + RTCIO_GPIO11_CHANNEL, //GPIO11 + RTCIO_GPIO12_CHANNEL, //GPIO12 + RTCIO_GPIO13_CHANNEL, //GPIO13 + RTCIO_GPIO14_CHANNEL, //GPIO14 + RTCIO_GPIO15_CHANNEL, //GPIO15 + RTCIO_GPIO16_CHANNEL, //GPIO16 + RTCIO_GPIO17_CHANNEL, //GPIO17 + RTCIO_GPIO18_CHANNEL, //GPIO18 + RTCIO_GPIO19_CHANNEL, //GPIO19 + RTCIO_GPIO20_CHANNEL, //GPIO20 + RTCIO_GPIO21_CHANNEL, //GPIO21 + -1,//GPIO22 + -1,//GPIO23 + -1,//GPIO24 + -1,//GPIO25 + -1,//GPIO26 + -1,//GPIO27 + -1,//GPIO28 + -1,//GPIO29 + -1,//GPIO30 + -1,//GPIO31 + -1,//GPIO32 + -1,//GPIO33 + -1,//GPIO34 + -1,//GPIO35 + -1,//GPIO36 + -1,//GPIO37 + -1,//GPIO38 + -1,//GPIO39 + -1,//GPIO40 + -1,//GPIO41 + -1,//GPIO42 + -1,//GPIO43 + -1,//GPIO44 + -1,//GPIO45 + -1,//GPIO46 + -1,//GPIO47 +}; + +//Reg,Mux,Fun,IE,Up,Down,Rtc_number +const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT] = { + /*REG MUX select function select Input enable Pullup Pulldown Sleep select Sleep input enable Sleep output enable PAD hold Pad force hold Mask of drive capability Offset gpio number */ + {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD0_HOLD_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_CHANNEL_0_GPIO_NUM}, //0 + {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD1_HOLD_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_CHANNEL_1_GPIO_NUM}, //1 + {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, RTC_IO_TOUCH_PAD2_SLP_SEL_M, RTC_IO_TOUCH_PAD2_SLP_IE_M, RTC_IO_TOUCH_PAD2_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD2_HOLD_M, RTC_IO_TOUCH_PAD2_DRV_V, RTC_IO_TOUCH_PAD2_DRV_S, RTCIO_CHANNEL_2_GPIO_NUM}, //2 + {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, RTC_IO_TOUCH_PAD3_SLP_SEL_M, RTC_IO_TOUCH_PAD3_SLP_IE_M, RTC_IO_TOUCH_PAD3_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD3_HOLD_M, RTC_IO_TOUCH_PAD3_DRV_V, RTC_IO_TOUCH_PAD3_DRV_S, RTCIO_CHANNEL_3_GPIO_NUM}, //3 + {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, RTC_IO_TOUCH_PAD4_SLP_SEL_M, RTC_IO_TOUCH_PAD4_SLP_IE_M, RTC_IO_TOUCH_PAD4_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD4_HOLD_M, RTC_IO_TOUCH_PAD4_DRV_V, RTC_IO_TOUCH_PAD4_DRV_S, RTCIO_CHANNEL_4_GPIO_NUM}, //4 + {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, RTC_IO_TOUCH_PAD5_SLP_SEL_M, RTC_IO_TOUCH_PAD5_SLP_IE_M, RTC_IO_TOUCH_PAD5_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD5_HOLD_M, RTC_IO_TOUCH_PAD5_DRV_V, RTC_IO_TOUCH_PAD5_DRV_S, RTCIO_CHANNEL_5_GPIO_NUM}, //5 + {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, RTC_IO_TOUCH_PAD6_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD6_HOLD_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_CHANNEL_6_GPIO_NUM}, //6 + {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, RTC_IO_TOUCH_PAD7_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD7_HOLD_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_CHANNEL_7_GPIO_NUM}, //7 + {RTC_IO_TOUCH_PAD8_REG, RTC_IO_TOUCH_PAD8_MUX_SEL_M, RTC_IO_TOUCH_PAD8_FUN_SEL_S, RTC_IO_TOUCH_PAD8_FUN_IE_M, RTC_IO_TOUCH_PAD8_RUE_M, RTC_IO_TOUCH_PAD8_RDE_M, RTC_IO_TOUCH_PAD8_SLP_SEL_M, RTC_IO_TOUCH_PAD8_SLP_IE_M, RTC_IO_TOUCH_PAD8_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD8_HOLD_M, RTC_IO_TOUCH_PAD8_DRV_V, RTC_IO_TOUCH_PAD8_DRV_S, RTCIO_CHANNEL_8_GPIO_NUM}, //8 + {RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_MUX_SEL_M, RTC_IO_TOUCH_PAD9_FUN_SEL_S, RTC_IO_TOUCH_PAD9_FUN_IE_M, RTC_IO_TOUCH_PAD9_RUE_M, RTC_IO_TOUCH_PAD9_RDE_M, RTC_IO_TOUCH_PAD9_SLP_SEL_M, RTC_IO_TOUCH_PAD9_SLP_IE_M, RTC_IO_TOUCH_PAD9_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD9_HOLD_M, RTC_IO_TOUCH_PAD9_DRV_V, RTC_IO_TOUCH_PAD9_DRV_S, RTCIO_CHANNEL_9_GPIO_NUM}, //9 + {RTC_IO_TOUCH_PAD10_REG, RTC_IO_TOUCH_PAD10_MUX_SEL_M, RTC_IO_TOUCH_PAD10_FUN_SEL_S, RTC_IO_TOUCH_PAD10_FUN_IE_M, RTC_IO_TOUCH_PAD10_RUE_M, RTC_IO_TOUCH_PAD10_RDE_M, RTC_IO_TOUCH_PAD10_SLP_SEL_M, RTC_IO_TOUCH_PAD10_SLP_IE_M, RTC_IO_TOUCH_PAD10_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD10_HOLD_M, RTC_IO_TOUCH_PAD10_DRV_V, RTC_IO_TOUCH_PAD10_DRV_S, RTCIO_CHANNEL_10_GPIO_NUM}, //10 + {RTC_IO_TOUCH_PAD11_REG, RTC_IO_TOUCH_PAD11_MUX_SEL_M, RTC_IO_TOUCH_PAD11_FUN_SEL_S, RTC_IO_TOUCH_PAD11_FUN_IE_M, RTC_IO_TOUCH_PAD11_RUE_M, RTC_IO_TOUCH_PAD11_RDE_M, RTC_IO_TOUCH_PAD11_SLP_SEL_M, RTC_IO_TOUCH_PAD11_SLP_IE_M, RTC_IO_TOUCH_PAD11_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD11_HOLD_M, RTC_IO_TOUCH_PAD11_DRV_V, RTC_IO_TOUCH_PAD11_DRV_S, RTCIO_CHANNEL_11_GPIO_NUM}, //11 + {RTC_IO_TOUCH_PAD12_REG, RTC_IO_TOUCH_PAD12_MUX_SEL_M, RTC_IO_TOUCH_PAD12_FUN_SEL_S, RTC_IO_TOUCH_PAD12_FUN_IE_M, RTC_IO_TOUCH_PAD12_RUE_M, RTC_IO_TOUCH_PAD12_RDE_M, RTC_IO_TOUCH_PAD12_SLP_SEL_M, RTC_IO_TOUCH_PAD12_SLP_IE_M, RTC_IO_TOUCH_PAD12_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD12_HOLD_M, RTC_IO_TOUCH_PAD12_DRV_V, RTC_IO_TOUCH_PAD12_DRV_S, RTCIO_CHANNEL_12_GPIO_NUM}, //12 + {RTC_IO_TOUCH_PAD13_REG, RTC_IO_TOUCH_PAD13_MUX_SEL_M, RTC_IO_TOUCH_PAD13_FUN_SEL_S, RTC_IO_TOUCH_PAD13_FUN_IE_M, RTC_IO_TOUCH_PAD13_RUE_M, RTC_IO_TOUCH_PAD13_RDE_M, RTC_IO_TOUCH_PAD13_SLP_SEL_M, RTC_IO_TOUCH_PAD13_SLP_IE_M, RTC_IO_TOUCH_PAD13_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD13_HOLD_M, RTC_IO_TOUCH_PAD13_DRV_V, RTC_IO_TOUCH_PAD13_DRV_S, RTCIO_CHANNEL_13_GPIO_NUM}, //13 + {RTC_IO_TOUCH_PAD14_REG, RTC_IO_TOUCH_PAD14_MUX_SEL_M, RTC_IO_TOUCH_PAD14_FUN_SEL_S, RTC_IO_TOUCH_PAD14_FUN_IE_M, RTC_IO_TOUCH_PAD14_RUE_M, RTC_IO_TOUCH_PAD14_RDE_M, RTC_IO_TOUCH_PAD14_SLP_SEL_M, RTC_IO_TOUCH_PAD14_SLP_IE_M, RTC_IO_TOUCH_PAD14_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD14_HOLD_M, RTC_IO_TOUCH_PAD14_DRV_V, RTC_IO_TOUCH_PAD14_DRV_S, RTCIO_CHANNEL_14_GPIO_NUM}, //14 + {RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, RTC_IO_X32P_SLP_OE_M, 0, RTC_CNTL_X32P_HOLD_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, RTCIO_CHANNEL_15_GPIO_NUM}, //15 + {RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, RTC_IO_X32N_SLP_OE_M, 0, RTC_CNTL_X32N_HOLD_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, RTCIO_CHANNEL_16_GPIO_NUM}, //16 + {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, RTC_IO_PDAC1_SLP_SEL_M, RTC_IO_PDAC1_SLP_IE_M, RTC_IO_PDAC1_SLP_OE_M, 0, RTC_CNTL_PDAC1_HOLD_M, RTC_IO_PDAC1_DRV_V, RTC_IO_PDAC1_DRV_S, RTCIO_CHANNEL_17_GPIO_NUM}, //17 + {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, RTC_IO_PDAC2_SLP_SEL_M, RTC_IO_PDAC2_SLP_IE_M, RTC_IO_PDAC2_SLP_OE_M, 0, RTC_CNTL_PDAC2_HOLD_M, RTC_IO_PDAC2_DRV_V, RTC_IO_PDAC2_DRV_S, RTCIO_CHANNEL_18_GPIO_NUM}, //18 + {RTC_IO_RTC_PAD19_REG, RTC_IO_PAD19_MUX_SEL_M, RTC_IO_PAD19_FUN_SEL_S, RTC_IO_PAD19_FUN_IE_M, RTC_IO_PAD19_RUE_M, RTC_IO_PAD19_RDE_M, RTC_IO_PAD19_SLP_SEL_M, RTC_IO_PAD19_SLP_IE_M, RTC_IO_PAD19_SLP_OE_M, 0, RTC_CNTL_PAD19_HOLD_M, RTC_IO_PAD19_DRV_V, RTC_IO_PAD19_DRV_S, RTCIO_CHANNEL_19_GPIO_NUM}, //19 + {RTC_IO_RTC_PAD20_REG, RTC_IO_PAD20_MUX_SEL_M, RTC_IO_PAD20_FUN_SEL_S, RTC_IO_PAD20_FUN_IE_M, RTC_IO_PAD20_RUE_M, RTC_IO_PAD20_RDE_M, RTC_IO_PAD20_SLP_SEL_M, RTC_IO_PAD20_SLP_IE_M, RTC_IO_PAD20_SLP_OE_M, 0, RTC_CNTL_PAD20_HOLD_M, RTC_IO_PAD20_DRV_V, RTC_IO_PAD20_DRV_S, RTCIO_CHANNEL_20_GPIO_NUM}, //20 + {RTC_IO_RTC_PAD21_REG, RTC_IO_PAD21_MUX_SEL_M, RTC_IO_PAD21_FUN_SEL_S, RTC_IO_PAD21_FUN_IE_M, RTC_IO_PAD21_RUE_M, RTC_IO_PAD21_RDE_M, RTC_IO_PAD21_SLP_SEL_M, RTC_IO_PAD21_SLP_IE_M, RTC_IO_PAD21_SLP_OE_M, 0, RTC_CNTL_PAD21_HOLD_M, RTC_IO_PAD21_DRV_V, RTC_IO_PAD21_DRV_S, RTCIO_CHANNEL_21_GPIO_NUM}, //21 +}; diff --git a/components/soc/esp32s2beta/rtc_periph.c b/components/soc/esp32s2beta/rtc_periph.c index 87d5ddc1b..72b0de6ec 100644 --- a/components/soc/esp32s2beta/rtc_periph.c +++ b/components/soc/esp32s2beta/rtc_periph.c @@ -13,29 +13,3 @@ // limitations under the License. #include "soc/rtc_periph.h" - -/* Reg,Mux,Fun,IE,Up,Down,Rtc_number */ -rtc_gpio_info_t* rtc_gpio_reg[RTC_GPIO_NUMBER] = { - (rtc_gpio_info_t*)&RTCIO.touch_pad[0].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[1].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[2].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[3].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[4].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[5].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[6].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[7].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[8].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[9].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[10].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[11].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[12].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[13].val, - (rtc_gpio_info_t*)&RTCIO.touch_pad[14].val, - (rtc_gpio_info_t*)&RTCIO.xtal_32p_pad.val, - (rtc_gpio_info_t*)&RTCIO.xtal_32n_pad.val, - (rtc_gpio_info_t*)&RTCIO.pad_dac[0].val, - (rtc_gpio_info_t*)&RTCIO.pad_dac[1].val, - (rtc_gpio_info_t*)&RTCIO.rtc_pad19.val, - (rtc_gpio_info_t*)&RTCIO.rtc_pad20.val, - (rtc_gpio_info_t*)&RTCIO.rtc_pad21.val -}; \ No newline at end of file diff --git a/components/soc/esp32s2beta/sources.cmake b/components/soc/esp32s2beta/sources.cmake index 8fcfefd6a..5c07bfccb 100644 --- a/components/soc/esp32s2beta/sources.cmake +++ b/components/soc/esp32s2beta/sources.cmake @@ -2,6 +2,7 @@ set(SOC_SRCS "cpu_util.c" "gpio_periph.c" "rtc_clk.c" "rtc_init.c" + "rtc_io_periph.c" "rtc_periph.c" "rtc_pm.c" "rtc_sleep.c" diff --git a/components/soc/include/hal/gpio_types.h b/components/soc/include/hal/gpio_types.h new file mode 100644 index 000000000..1b0c46c14 --- /dev/null +++ b/components/soc/include/hal/gpio_types.h @@ -0,0 +1,51 @@ +#pragma once + +#include "soc/gpio_pins.h" + +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output + @note There are more enumerations like that + up to GPIO39, excluding GPIO20, GPIO24 and GPIO28..31. + They are not shown here to reduce redundant information. + @note GPIO34..39 are input mode only. */ +/** @cond */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ + + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + + GPIO_NUM_32 = 32, /*!< GPIO32, input and output */ + GPIO_NUM_33 = 33, /*!< GPIO33, input and output */ + GPIO_NUM_34 = 34, /*!< GPIO34, input mode only */ + GPIO_NUM_35 = 35, /*!< GPIO35, input mode only */ + GPIO_NUM_36 = 36, /*!< GPIO36, input mode only */ + GPIO_NUM_37 = 37, /*!< GPIO37, input mode only */ + GPIO_NUM_38 = 38, /*!< GPIO38, input mode only */ + GPIO_NUM_39 = 39, /*!< GPIO39, input mode only */ + GPIO_NUM_MAX = 40, +/** @endcond */ +} gpio_num_t; \ No newline at end of file diff --git a/components/soc/include/hal/rtc_io_hal.h b/components/soc/include/hal/rtc_io_hal.h new file mode 100644 index 000000000..d1a8b1178 --- /dev/null +++ b/components/soc/include/hal/rtc_io_hal.h @@ -0,0 +1,239 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The HAL layer for RTC IO master (common part) + +#pragma once + +#include "hal/rtc_io_ll.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Select the rtcio function. + * + * @note The RTC function must be selected before the pad analog function is enabled. + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + * @param func Select pin function. + */ +#define rtcio_hal_function_select(rtcio_num, func) rtcio_ll_function_select(rtcio_num, func) + +/** + * Enable rtcio output. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_output_enable(rtcio_num) rtcio_ll_output_enable(rtcio_num) + +/** + * Disable rtcio output. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_output_disable(rtcio_num) rtcio_ll_output_disable(rtcio_num) + +/** + * Set RTCIO output level. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + * @param level 0: output low; ~0: output high. + */ +#define rtcio_hal_set_level(rtcio_num, level) rtcio_ll_set_level(rtcio_num, level) + +/** + * Enable rtcio input. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_input_enable(rtcio_num) rtcio_ll_input_enable(rtcio_num) + +/** + * Disable rtcio input. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_input_disable(rtcio_num) rtcio_ll_input_disable(rtcio_num) + +/** + * Get RTCIO input level. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + * @return 0: input low; ~0: input high. + */ +#define rtcio_hal_get_level(rtcio_num) rtcio_ll_get_level(rtcio_num) + +/** + * @brief Set RTC GPIO pad drive capability. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + * @param strength Drive capability of the pad. Range: 0 ~ 3. + */ +#define rtcio_hal_set_drive_capability(rtcio_num, strength) rtcio_ll_set_drive_capability(rtcio_num, strength) + +/** + * @brief Get RTC GPIO pad drive capability. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + * @return Drive capability of the pad. Range: 0 ~ 3. + */ +#define rtcio_hal_get_drive_capability(rtcio_num) rtcio_ll_get_drive_capability(rtcio_num) + +/** + * Set RTCIO output level. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + * @param level 0: output low; ~0: output high. + */ +#define rtcio_hal_set_level(rtcio_num, level) rtcio_ll_set_level(rtcio_num, level) + +/** + * Get RTCIO input level. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + * @return 0: input low; ~0: input high. + */ +#define rtcio_hal_get_level(rtcio_num) rtcio_ll_get_level(rtcio_num) + +/** + * Set RTC IO direction. + * + * Configure RTC IO direction, such as output only, input only, + * output and input. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + * @param mode IO direction. + */ +void rtcio_hal_set_direction(int rtcio_num, rtc_gpio_mode_t mode); + +/** + * Set RTC IO direction in deep sleep or disable sleep status. + * + * NOTE: ESP32 support INPUT_ONLY mode. + * ESP32S2 support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + * @param mode IO direction. + */ +void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode); + +/** + * RTC GPIO pullup enable. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_pullup_enable(rtcio_num) rtcio_ll_pullup_enable(rtcio_num) + +/** + * RTC GPIO pullup disable. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_pullup_disable(rtcio_num) rtcio_ll_pullup_disable(rtcio_num) + +/** + * RTC GPIO pulldown enable. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_pulldown_enable(rtcio_num) rtcio_ll_pulldown_enable(rtcio_num) + +/** + * RTC GPIO pulldown disable. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_pulldown_disable(rtcio_num) rtcio_ll_pulldown_disable(rtcio_num) + +/** + * Enable force hold function for RTC IO pad. + * + * Enabling HOLD function will cause the pad to lock current status, such as, + * input/output enable, input/output value, function, drive strength values. + * This function is useful when going into light or deep sleep mode to prevent + * the pin configuration from changing. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_hold_enable(rtcio_num) rtcio_ll_force_hold_enable(rtcio_num) + +/** + * Disable hold function on an RTC IO pad + * + * @note If disable the pad hold, the status of pad maybe changed in sleep mode. + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_hold_disable(rtcio_num) rtcio_ll_force_hold_disable(rtcio_num) + +/** + * Enable force hold function for RTC IO pads. + * + * Enabling HOLD function will cause the pad to lock current status, such as, + * input/output enable, input/output value, function, drive strength values. + * This function is useful when going into light or deep sleep mode to prevent + * the pin configuration from changing. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_hold_all() rtcio_ll_force_hold_all() + +/** + * Disable hold function on an RTC IO pads. + * + * @note If disable the pad hold, the status of pad maybe changed in sleep mode. + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_unhold_all() rtcio_ll_force_unhold_all() + +/** + * Enable wakeup function and set wakeup type from light sleep status for rtcio. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + * @param type Wakeup on high level or low level. + */ +#define rtcio_hal_wakeup_enable(rtcio_num, type) rtcio_ll_wakeup_enable(rtcio_num, type) + +/** + * Disable wakeup function from light sleep status for rtcio. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +#define rtcio_hal_wakeup_disable(rtcio_num) rtcio_ll_wakeup_disable(rtcio_num) + +/** + * Helper function to disconnect internal circuits from an RTC IO + * This function disables input, output, pullup, pulldown, and enables + * hold feature for an RTC IO. + * Use this function if an RTC IO needs to be disconnected from internal + * circuits in deep sleep, to minimize leakage current. + * + * In particular, for ESP32-WROVER module, call + * rtc_gpio_isolate(GPIO_NUM_12) before entering deep sleep, to reduce + * deep sleep current. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT. + */ +void rtcio_hal_isolate(int rtc_num); + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/components/soc/include/hal/rtc_io_types.h b/components/soc/include/hal/rtc_io_types.h new file mode 100644 index 000000000..82b358d86 --- /dev/null +++ b/components/soc/include/hal/rtc_io_types.h @@ -0,0 +1,25 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** RTCIO output/input mode type. */ +typedef enum { + RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad input */ + RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad output */ + RTC_GPIO_MODE_INPUT_OUTPUT, /*!< Pad input + output */ + RTC_GPIO_MODE_DISABLED, /*!< Pad (output + input) disable */ + RTC_GPIO_MODE_OUTPUT_OD, /*!< Pad open-drain output */ + RTC_GPIO_MODE_INPUT_OUTPUT_OD, /*!< Pad input + open-drain output */ +} rtc_gpio_mode_t; \ No newline at end of file diff --git a/components/soc/include/soc/rtc_io_periph.h b/components/soc/include/soc/rtc_io_periph.h new file mode 100644 index 000000000..de24b9b9d --- /dev/null +++ b/components/soc/include/soc/rtc_io_periph.h @@ -0,0 +1,109 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" +//include soc related (generated) definitions +#include "soc/rtc_io_caps.h" +#include "soc/rtc_io_channel.h" +#include "soc/rtc_io_reg.h" +#include "soc/rtc_io_struct.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/rtc_cntl_struct.h" +#include "hal/gpio_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief Pin function information for a single RTCIO pad's. + * + * This is an internal function of the driver, and is not usually useful + * for external use. + */ +typedef struct { + uint32_t reg; /*!< Register of RTC pad, or 0 if not an RTC GPIO */ + uint32_t mux; /*!< Bit mask for selecting digital pad or RTC pad */ + uint32_t func; /*!< Shift of pad function (FUN_SEL) field */ + uint32_t ie; /*!< Mask of input enable */ + uint32_t pullup; /*!< Mask of pullup enable */ + uint32_t pulldown; /*!< Mask of pulldown enable */ + uint32_t slpsel; /*!< If slpsel bit is set, slpie will be used as pad input enabled signal in sleep mode */ + uint32_t slpie; /*!< Mask of input enable in sleep mode */ + uint32_t slpoe; /*!< Mask of output enable in sleep mode */ + uint32_t hold; /*!< Mask of hold enable */ + uint32_t hold_force;/*!< Mask of hold_force bit for RTC IO in RTC_CNTL_HOLD_REG */ + uint32_t drv_v; /*!< Mask of drive capability */ + uint32_t drv_s; /*!< Offset of drive capability */ + int rtc_num; /*!< GPIO number (corresponds to RTC pad) */ +} rtc_io_desc_t; + +/** + * @brief Provides access to a constant table of RTC I/O pin + * function information. + * The index of table is the index of rtcio. + * + * This is an internal function of the driver, and is not usually useful + * for external use. + */ +extern const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT]; + +/** + * @brief Provides a constant table to get rtc io number with gpio number + * + * This is an internal function of the driver, and is not usually useful + * for external use. + */ +extern const int rtc_io_num_map[GPIO_PIN_COUNT]; + +#ifdef CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC +/** + * @brief Pin function information for a single GPIO pad's RTC functions. + * + * This is an internal function of the driver, and is not usually useful + * for external use. + */ +typedef struct { + uint32_t reg; /*!< Register of RTC pad, or 0 if not an RTC GPIO */ + uint32_t mux; /*!< Bit mask for selecting digital pad or RTC pad */ + uint32_t func; /*!< Shift of pad function (FUN_SEL) field */ + uint32_t ie; /*!< Mask of input enable */ + uint32_t pullup; /*!< Mask of pullup enable */ + uint32_t pulldown; /*!< Mask of pulldown enable */ + uint32_t slpsel; /*!< If slpsel bit is set, slpie will be used as pad input enabled signal in sleep mode */ + uint32_t slpie; /*!< Mask of input enable in sleep mode */ + uint32_t hold; /*!< Mask of hold enable */ + uint32_t hold_force;/*!< Mask of hold_force bit for RTC IO in RTC_CNTL_HOLD_FORCE_REG */ + uint32_t drv_v; /*!< Mask of drive capability */ + uint32_t drv_s; /*!< Offset of drive capability */ + int rtc_num; /*!< RTC IO number, or -1 if not an RTC GPIO */ +} rtc_gpio_desc_t; + +/** + * @brief Provides access to a constant table of RTC I/O pin + * function information. + * + * This is an internal function of the driver, and is not usually useful + * for external use. + */ +extern const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT]; + +#endif // CONFIG_IDF_TARGET_ESP32 + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/components/soc/include/soc/rtc_periph.h b/components/soc/include/soc/rtc_periph.h index fedd5e54b..ace548990 100644 --- a/components/soc/include/soc/rtc_periph.h +++ b/components/soc/include/soc/rtc_periph.h @@ -14,11 +14,7 @@ #pragma once #include -#include "soc/rtc_io_reg.h" -#include "soc/rtc_io_struct.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/rtc_cntl_struct.h" -#include "soc/rtc_gpio_channel.h" +#include "rtc_io_periph.h" #include "soc/gpio_pins.h" #ifdef __cplusplus @@ -26,54 +22,6 @@ extern "C" { #endif -/** - * @brief Pin function information for a single GPIO pad's RTC functions. - * - * This is an internal function of the driver, and is not usually useful - * for external use. - */ -typedef struct { - uint32_t reg; /*!< Register of RTC pad, or 0 if not an RTC GPIO */ - uint32_t mux; /*!< Bit mask for selecting digital pad or RTC pad */ - uint32_t func; /*!< Shift of pad function (FUN_SEL) field */ - uint32_t ie; /*!< Mask of input enable */ - uint32_t pullup; /*!< Mask of pullup enable */ - uint32_t pulldown; /*!< Mask of pulldown enable */ - uint32_t slpsel; /*!< If slpsel bit is set, slpie will be used as pad input enabled signal in sleep mode */ - uint32_t slpie; /*!< Mask of input enable in sleep mode */ - uint32_t hold; /*!< Mask of hold enable */ - uint32_t hold_force;/*!< Mask of hold_force bit for RTC IO in RTC_CNTL_HOLD_FORCE_REG */ - uint32_t drv_v; /*!< Mask of drive capability */ - uint32_t drv_s; /*!< Offset of drive capability */ - int rtc_num; /*!< RTC IO number, or -1 if not an RTC GPIO */ -} rtc_gpio_desc_t; - -/** - * @brief Provides access to a constant table of RTC I/O pin - * function information. - * - * This is an internal function of the driver, and is not usually useful - * for external use. - */ -extern const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT]; - -typedef volatile struct { - uint32_t reserved0: 13; - uint32_t fun_ie: 1; /*input enable in work mode*/ - uint32_t slp_oe: 1; /*output enable in sleep mode*/ - uint32_t slp_ie: 1; /*input enable in sleep mode*/ - uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ - uint32_t fun_sel: 2; /*function sel*/ - uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ - uint32_t reserved20: 7; - uint32_t rue: 1; /*RUE*/ - uint32_t rde: 1; /*RDE*/ - uint32_t drv: 2; /*DRV*/ - uint32_t reserved31: 1; -} rtc_gpio_info_t; - -extern rtc_gpio_info_t* rtc_gpio_reg[RTC_GPIO_NUMBER]; - #ifdef __cplusplus } #endif diff --git a/components/soc/src/hal/rtc_io_hal.c b/components/soc/src/hal/rtc_io_hal.c new file mode 100644 index 000000000..c37ed6a5e --- /dev/null +++ b/components/soc/src/hal/rtc_io_hal.c @@ -0,0 +1,92 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The HAL layer for RTC IO (common part) + +#include "hal/rtc_io_hal.h" + +void rtcio_hal_set_direction(int rtcio_num, rtc_gpio_mode_t mode) +{ + switch (mode) { + case RTC_GPIO_MODE_INPUT_ONLY: + rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_NORMAL); + rtcio_ll_output_disable(rtcio_num); + rtcio_ll_input_enable(rtcio_num); + break; + case RTC_GPIO_MODE_OUTPUT_ONLY: + rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_NORMAL); + rtcio_ll_output_enable(rtcio_num); + rtcio_ll_input_disable(rtcio_num); + break; + case RTC_GPIO_MODE_INPUT_OUTPUT: + rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_NORMAL); + rtcio_ll_output_enable(rtcio_num); + rtcio_ll_input_enable(rtcio_num); + break; + case RTC_GPIO_MODE_DISABLED: + rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_NORMAL); + rtcio_ll_output_disable(rtcio_num); + rtcio_ll_input_disable(rtcio_num); + break; + case RTC_GPIO_MODE_OUTPUT_OD: + rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_OD); + rtcio_ll_output_enable(rtcio_num); + rtcio_ll_input_disable(rtcio_num); + break; + case RTC_GPIO_MODE_INPUT_OUTPUT_OD: + rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_OD); + rtcio_ll_output_enable(rtcio_num); + rtcio_ll_input_enable(rtcio_num); + break; + default: + break; + } +} + +void rtcio_hal_isolate(int rtcio_num) +{ + rtcio_ll_pullup_disable(rtcio_num); + rtcio_ll_pulldown_disable(rtcio_num); + rtcio_ll_output_disable(rtcio_num); + rtcio_ll_input_disable(rtcio_num); + rtcio_ll_force_hold_enable(rtcio_num); +} + +void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode) +{ + switch (mode) { + case RTC_GPIO_MODE_INPUT_ONLY: + rtcio_ll_in_sleep_enable_input(rtcio_num); + rtcio_ll_in_sleep_disable_output(rtcio_num); + rtcio_ll_enable_sleep_setting(rtcio_num); + break; + case RTC_GPIO_MODE_OUTPUT_ONLY: + rtcio_ll_enable_output_in_sleep(rtcio_num); + rtcio_ll_in_sleep_disable_input(rtcio_num); + rtcio_ll_enable_sleep_setting(rtcio_num); + break; + case RTC_GPIO_MODE_INPUT_OUTPUT: + rtcio_ll_in_sleep_enable_input(rtcio_num); + rtcio_ll_enable_output_in_sleep(rtcio_num); + rtcio_ll_enable_sleep_setting(rtcio_num); + break; + case RTC_GPIO_MODE_DISABLED: + rtcio_ll_in_sleep_disable_input(rtcio_num); + rtcio_ll_in_sleep_disable_output(rtcio_num); + rtcio_ll_disable_sleep_setting(rtcio_num); + break; + default: + break; + } +} \ No newline at end of file diff --git a/docs/Doxyfile b/docs/Doxyfile index 8d98ccadc..3009d4b44 100644 --- a/docs/Doxyfile +++ b/docs/Doxyfile @@ -107,11 +107,12 @@ INPUT = \ ../../components/soc/include/hal/spi_types.h \ ../../components/soc/include/hal/pcnt_types.h \ ../../components/soc/include/hal/i2s_types.h \ + ../../components/soc/include/hal/rtc_io_types.h \ ../../components/soc/esp32/include/soc/adc_channel.h \ ../../components/soc/esp32/include/soc/dac_channel.h \ ../../components/soc/esp32/include/soc/touch_channel.h \ ../../components/soc/esp32/include/soc/uart_channel.h \ - ../../components/soc/esp32/include/soc/rtc_gpio_channel.h \ + ../../components/soc/esp32/include/soc/rtc_io_channel.h \ ## esp_netif - API Reference ../../components/esp_netif/include/esp_netif.h \ ## diff --git a/examples/system/ulp/main/ulp_example_main.c b/examples/system/ulp/main/ulp_example_main.c index fa6e1eead..296c123b2 100644 --- a/examples/system/ulp/main/ulp_example_main.c +++ b/examples/system/ulp/main/ulp_example_main.c @@ -49,7 +49,8 @@ static void init_ulp_program(void) /* GPIO used for pulse counting. */ gpio_num_t gpio_num = GPIO_NUM_0; - assert(rtc_gpio_desc[gpio_num].reg && "GPIO used for pulse counting must be an RTC IO"); + int rtcio_num = rtc_io_number_get(gpio_num); + assert(rtc_gpio_is_valid_gpio(gpio_num) && "GPIO used for pulse counting must be an RTC IO"); /* Initialize some variables used by ULP program. * Each 'ulp_xyz' variable corresponds to 'xyz' variable in the ULP program. @@ -63,7 +64,7 @@ static void init_ulp_program(void) ulp_debounce_counter = 3; ulp_debounce_max_count = 3; ulp_next_edge = 0; - ulp_io_number = rtc_gpio_desc[gpio_num].rtc_num; /* map from GPIO# to RTC_IO# */ + ulp_io_number = rtcio_num; /* map from GPIO# to RTC_IO# */ ulp_edge_count_to_wake_up = 10; /* Initialize selected GPIO as RTC IO, enable input, disable pullup and pulldown */