Merge branch 'feature/add_psram_workaround_option_3.2' into 'release/v3.2'
make psram workaround depend on chip revison (v3.2) See merge request espressif/esp-idf!6304
This commit is contained in:
commit
093214c86f
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@ -93,6 +93,13 @@ bool bootloader_common_label_search(const char *list, char *label);
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*/
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*/
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esp_err_t bootloader_common_get_sha256_of_partition(uint32_t address, uint32_t size, int type, uint8_t *out_sha_256);
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esp_err_t bootloader_common_get_sha256_of_partition(uint32_t address, uint32_t size, int type, uint8_t *out_sha_256);
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/**
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* @brief Get chip revision
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*
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* @return Chip revision number
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*/
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uint8_t bootloader_common_get_chip_revision(void);
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/**
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/**
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* @brief Check if the image (bootloader and application) has valid chip ID and revision
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* @brief Check if the image (bootloader and application) has valid chip ID and revision
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*
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*
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@ -30,9 +30,10 @@
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#include "soc/efuse_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/rtc.h"
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#include "soc/rtc.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/apb_ctrl_reg.h"
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#include "esp_image_format.h"
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#include "esp_image_format.h"
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#include "bootloader_sha.h"
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#include "bootloader_sha.h"
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#include "esp_efuse.h"
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#define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
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#define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
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@ -222,22 +223,48 @@ void bootloader_common_set_flash_cs_timing()
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SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
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}
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}
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uint8_t bootloader_common_get_chip_revision(void)
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{
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uint8_t eco_bit0, eco_bit1, eco_bit2;
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eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15;
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eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20;
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eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31;
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uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
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uint8_t chip_ver = 0;
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switch (combine_value) {
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case 0:
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chip_ver = 0;
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break;
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case 1:
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chip_ver = 1;
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break;
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case 3:
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chip_ver = 2;
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break;
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case 7:
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chip_ver = 3;
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break;
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default:
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chip_ver = 0;
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break;
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}
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return chip_ver;
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}
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esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr)
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esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr)
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{
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{
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esp_err_t err = ESP_OK;
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esp_err_t err = ESP_OK;
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esp_chip_id_t chip_id = CONFIG_IDF_FIRMWARE_CHIP_ID;
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esp_chip_id_t chip_id = CONFIG_IDF_FIRMWARE_CHIP_ID;
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if (chip_id != img_hdr->chip_id) {
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if (chip_id != img_hdr->chip_id) {
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ESP_LOGE(TAG, "image has invalid chip ID, expected at least %d, found %d", chip_id, img_hdr->chip_id);
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ESP_LOGE(TAG, "mismatch chip ID, expect %d, found %d", chip_id, img_hdr->chip_id);
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err = ESP_FAIL;
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err = ESP_FAIL;
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}
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}
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uint8_t revision = esp_efuse_get_chip_ver();
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uint8_t revision = bootloader_common_get_chip_revision();
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if (revision < img_hdr->min_chip_rev) {
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if (revision < img_hdr->min_chip_rev) {
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ESP_LOGE(TAG, "image has invalid chip revision, expected at least %d, found %d", revision, img_hdr->min_chip_rev);
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ESP_LOGE(TAG, "can't run on lower chip revision, expect %d, found %d", revision, img_hdr->min_chip_rev);
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err = ESP_FAIL;
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err = ESP_FAIL;
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} else if (revision != img_hdr->min_chip_rev) {
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} else if (revision != img_hdr->min_chip_rev) {
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ESP_LOGI(TAG, "This chip is revision %d but project was configured for minimum revision %d. "\
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ESP_LOGI(TAG, "mismatch chip revision, expect %d, found %d", revision, img_hdr->min_chip_rev);
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"Suggest setting project minimum revision to %d if safe to do so.",
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revision, img_hdr->min_chip_rev, revision);
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}
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}
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return err;
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return err;
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}
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}
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@ -127,7 +127,7 @@ static esp_err_t bootloader_main()
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return ESP_FAIL;
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return ESP_FAIL;
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}
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}
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/* Check chip ID and minimum chip revision that supported by this image */
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/* Check chip ID and minimum chip revision that supported by this image */
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uint8_t revision = esp_efuse_get_chip_ver();
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uint8_t revision = bootloader_common_get_chip_revision();
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ESP_LOGI(TAG, "Chip Revision: %d", revision);
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ESP_LOGI(TAG, "Chip Revision: %d", revision);
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if (bootloader_common_check_chip_validity(&fhdr) != ESP_OK) {
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if (bootloader_common_check_chip_validity(&fhdr) != ESP_OK) {
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return ESP_FAIL;
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return ESP_FAIL;
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@ -147,7 +147,7 @@ config SPIRAM_MEMTEST
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config SPIRAM_CACHE_WORKAROUND
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config SPIRAM_CACHE_WORKAROUND
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bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
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bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
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depends on SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
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depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN < 3)
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default "y"
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default "y"
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help
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help
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Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations
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Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations
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@ -158,6 +158,8 @@ config SPIRAM_CACHE_WORKAROUND
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This will also not use any bits of newlib that are located in ROM, opting for a version that is compiled
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This will also not use any bits of newlib that are located in ROM, opting for a version that is compiled
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with the workaround and located in flash instead.
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with the workaround and located in flash instead.
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The workaround is not required for ESP32 revision 3 and above.
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config SPIRAM_BANKSWITCH_ENABLE
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config SPIRAM_BANKSWITCH_ENABLE
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bool "Enable bank switching for >4MiB external RAM"
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bool "Enable bank switching for >4MiB external RAM"
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default y
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default y
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