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Merge branch 'feature/add_psram_workaround_option_3.2' into 'release/v3.2'

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make psram workaround depend on chip revison (v3.2)

See merge request espressif/esp-idf!6304
This commit is contained in:
Jiang Jiang Jian 2019-10-14 21:45:34 +08:00
parent f55cb56380 ef796860d7
commit 093214c86f
4 changed files with 45 additions and 9 deletions
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7
components/bootloader_support/include/bootloader_common.h
View file

@ -93,6 +93,13 @@ bool bootloader_common_label_search(const char *list, char *label);
*/
esp_err_t bootloader_common_get_sha256_of_partition(uint32_t address, uint32_t size, int type, uint8_t *out_sha_256);
/**
* @brief Get chip revision
*
* @return Chip revision number
*/
uint8_t bootloader_common_get_chip_revision(void);
/**
* @brief Check if the image (bootloader and application) has valid chip ID and revision
*

41
components/bootloader_support/src/bootloader_common.c
View file

@ -30,9 +30,10 @@
#include "soc/efuse_reg.h"
#include "soc/rtc.h"
#include "soc/spi_reg.h"
#include "soc/efuse_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "esp_image_format.h"
#include "bootloader_sha.h"
#include "esp_efuse.h"
#define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
@ -222,22 +223,48 @@ void bootloader_common_set_flash_cs_timing()
SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
}
uint8_t bootloader_common_get_chip_revision(void)
{
uint8_t eco_bit0, eco_bit1, eco_bit2;
eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15;
eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20;
eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31;
uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
uint8_t chip_ver = 0;
switch (combine_value) {
case 0:
chip_ver = 0;
break;
case 1:
chip_ver = 1;
break;
case 3:
chip_ver = 2;
break;
case 7:
chip_ver = 3;
break;
default:
chip_ver = 0;
break;
}
return chip_ver;
}
esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr)
{
esp_err_t err = ESP_OK;
esp_chip_id_t chip_id = CONFIG_IDF_FIRMWARE_CHIP_ID;
if (chip_id != img_hdr->chip_id) {
ESP_LOGE(TAG, "image has invalid chip ID, expected at least %d, found %d", chip_id, img_hdr->chip_id);
ESP_LOGE(TAG, "mismatch chip ID, expect %d, found %d", chip_id, img_hdr->chip_id);
err = ESP_FAIL;
}
uint8_t revision = esp_efuse_get_chip_ver();
uint8_t revision = bootloader_common_get_chip_revision();
if (revision < img_hdr->min_chip_rev) {
ESP_LOGE(TAG, "image has invalid chip revision, expected at least %d, found %d", revision, img_hdr->min_chip_rev);
ESP_LOGE(TAG, "can't run on lower chip revision, expect %d, found %d", revision, img_hdr->min_chip_rev);
err = ESP_FAIL;
} else if (revision != img_hdr->min_chip_rev) {
ESP_LOGI(TAG, "This chip is revision %d but project was configured for minimum revision %d. "\
"Suggest setting project minimum revision to %d if safe to do so.",
revision, img_hdr->min_chip_rev, revision);
ESP_LOGI(TAG, "mismatch chip revision, expect %d, found %d", revision, img_hdr->min_chip_rev);
}
return err;
}

2
components/bootloader_support/src/bootloader_init.c
View file

@ -127,7 +127,7 @@ static esp_err_t bootloader_main()
return ESP_FAIL;
}
/* Check chip ID and minimum chip revision that supported by this image */
uint8_t revision = esp_efuse_get_chip_ver();
uint8_t revision = bootloader_common_get_chip_revision();
ESP_LOGI(TAG, "Chip Revision: %d", revision);
if (bootloader_common_check_chip_validity(&fhdr) != ESP_OK) {
return ESP_FAIL;

4
components/esp32/Kconfig
View file

@ -147,7 +147,7 @@ config SPIRAM_MEMTEST
config SPIRAM_CACHE_WORKAROUND
bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
depends on SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN < 3)
default "y"
help
Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations
@ -158,6 +158,8 @@ config SPIRAM_CACHE_WORKAROUND
This will also not use any bits of newlib that are located in ROM, opting for a version that is compiled
with the workaround and located in flash instead.
The workaround is not required for ESP32 revision 3 and above.
config SPIRAM_BANKSWITCH_ENABLE
bool "Enable bank switching for >4MiB external RAM"
default y