esp_system: fix various review issues

components/esp32s2/clk.c

@@ -21,7 +21,7 @@
 
 #define MHZ (1000000)
 
-// g_ticks_us defined in ROMs for PRO and APP CPU
+// g_ticks_us defined in ROMs
 extern uint32_t g_ticks_per_us_pro;
 
 int IRAM_ATTR esp_clk_cpu_freq(void)

components/esp_system/port/cpu_start.c

@@ -140,8 +140,8 @@ void IRAM_ATTR call_start_cpu1(void)
 
     s_cpu_inited[1] = true;
 
-    while(!s_resume_cores) {
-        cpu_hal_delay_us(100);
+    while (!s_resume_cores) {
+        ets_delay_us(100);
     }
 
     SYS_STARTUP_FN();
@@ -172,12 +172,12 @@ static void start_other_core(void)
 
         volatile bool cpus_up = false;
 
-        while(!cpus_up){
+        while (!cpus_up){
             cpus_up = true;
             for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
                 cpus_up &= s_cpu_up[i];
             }
-            cpu_hal_delay_us(100);
+            ets_delay_us(100);
         }
     }
     else {
@@ -190,12 +190,7 @@ static void start_other_core(void)
 
 static void intr_matrix_clear(void)
 {
-#if CONFIG_IDF_TARGET_ESP32
-    //Clear all the interrupt matrix register
-    for (int i = ETS_WIFI_MAC_INTR_SOURCE; i <= ETS_CACHE_IA_INTR_SOURCE; i++) {
-#elif CONFIG_IDF_TARGET_ESP32S2
     for (int i = ETS_WIFI_MAC_INTR_SOURCE; i < ETS_MAX_INTR_SOURCE; i++) {
-#endif
         intr_matrix_set(0, i, ETS_INVALID_INUM);
 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
         intr_matrix_set(1, i, ETS_INVALID_INUM);
@@ -232,12 +227,10 @@ void IRAM_ATTR call_start_cpu0(void)
         || rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
 #endif
     ) {
-#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
         wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
         wdt_hal_write_protect_disable(&rtc_wdt_ctx);
         wdt_hal_disable(&rtc_wdt_ctx);
         wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-#endif
     }
 #endif
 
@@ -413,12 +406,12 @@ void IRAM_ATTR call_start_cpu0(void)
 
     volatile bool cpus_inited = false;
 
-    while(!cpus_inited) {
+    while (!cpus_inited) {
         cpus_inited = true;
         for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
             cpus_inited &= s_cpu_inited[i];
         }
-        cpu_hal_delay_us(100);
+        ets_delay_us(100);
     }
 #endif
 

components/esp_system/startup.c

@@ -54,10 +54,12 @@
 // [refactor-todo] make this file completely target-independent
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/uart.h"
+#include "esp32/rom/ets_sys.h"
 #include "esp32/spiram.h"
 #include "esp32/brownout.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/uart.h"
+#include "esp32s2/rom/ets_sys.h"
 #include "esp32s2/spiram.h"
 #include "esp32s2/brownout.h"
 #endif
@@ -143,8 +145,8 @@ static void IRAM_ATTR do_system_init_fn(void)
 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 static void IRAM_ATTR app_mainX_default(void)
 {
-    while(1) {
-        cpu_hal_delay_us(UINT32_MAX);
+    while (1) {
+        ets_delay_us(UINT32_MAX);
     }
 }
 
@@ -152,8 +154,8 @@ static void IRAM_ATTR start_cpuX_default(void)
 {
     do_system_init_fn();
 
-    while(!s_system_full_inited) {
-        cpu_hal_delay_us(100);
+    while (!s_system_full_inited) {
+        ets_delay_us(100);
     }
 
     app_mainX();
@@ -192,12 +194,6 @@ static void IRAM_ATTR do_core_init(void)
     esp_brownout_init();
 #endif
 
-#if CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE || CONFIG_ESP32S2_DISABLE_BASIC_ROM_CONSOLE
-    // [refactor-todo] leads to call chain `esp_efuse_read_field_blob` (efuse) -> `esp_efuse_utility_process` ->  `ESP_LOGX`
-    // syscall table must at least be init
-    esp_efuse_disable_basic_rom_console();
-#endif
-
 #ifdef CONFIG_VFS_SUPPORT_IO
     esp_vfs_dev_uart_register();
 #endif // CONFIG_VFS_SUPPORT_IO
@@ -277,12 +273,12 @@ static void IRAM_ATTR do_secondary_init(void)
     // Wait for all cores to finish secondary init.
     volatile bool system_inited = false;
 
-    while(!system_inited) {
+    while (!system_inited) {
         system_inited = true;
         for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
             system_inited &= s_system_inited[i];
         }
-        cpu_hal_delay_us(100);
+        ets_delay_us(100);
     }
 #endif
 }
@@ -336,13 +332,11 @@ void IRAM_ATTR start_cpu0_default(void)
 #endif
 
     app_main();
-    while(1);
+    while (1);
 }
 
 IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
 {
-    esp_err_t err;
-
 #ifdef CONFIG_PM_ENABLE
     const int uart_clk_freq = REF_CLK_FREQ;
     /* When DFS is enabled, use REFTICK as UART clock source */
@@ -350,9 +344,6 @@ IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
     uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif // CONFIG_ESP_CONSOLE_UART_NONE
 
-    err = esp_pthread_init();
-    assert(err == ESP_OK && "Failed to init pthread module!");
-
 #ifdef CONFIG_PM_ENABLE
     esp_pm_impl_init();
 #ifdef CONFIG_PM_DFS_INIT_AUTO

components/freertos/xtensa/port.c

@@ -529,7 +529,6 @@ static void main_task(void* args)
 #endif
 
 
-
 #if !CONFIG_FREERTOS_UNICORE
 void app_mainX(void)
 {

components/soc/include/hal/cpu_hal.h

@@ -107,13 +107,6 @@ void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_tr
  */
 void cpu_hal_clear_watchpoint(int id);
 
-/*
- * Insert a delay.
- * 
- * @param delay_us length of delay in microseconds
- */
-void cpu_hal_delay_us(uint32_t delay_us);
-
 #endif // SOC_CPU_WATCHPOINTS_NUM > 0
 
 /**

components/soc/src/hal/cpu_hal.c

@@ -68,8 +68,3 @@ void cpu_hal_set_vecbase(const void* base)
 {
     cpu_ll_set_vecbase(base);
 }
-
-void cpu_hal_delay_us(uint32_t delay_us)
-{
-    ets_delay_us(delay_us);
-}