esp_system: fix various review issues
This commit is contained in:
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5e59b4a812
commit
08cbfa6187
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@ -21,7 +21,7 @@
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#define MHZ (1000000)
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#define MHZ (1000000)
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// g_ticks_us defined in ROMs for PRO and APP CPU
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// g_ticks_us defined in ROMs
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extern uint32_t g_ticks_per_us_pro;
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extern uint32_t g_ticks_per_us_pro;
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int IRAM_ATTR esp_clk_cpu_freq(void)
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int IRAM_ATTR esp_clk_cpu_freq(void)
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@ -2,8 +2,8 @@ idf_component_register(SRCS "panic.c" "system_api.c" "startup.c"
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INCLUDE_DIRS include
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INCLUDE_DIRS include
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PRIV_INCLUDE_DIRS private_include
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PRIV_INCLUDE_DIRS private_include
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PRIV_REQUIRES spi_flash app_update
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PRIV_REQUIRES spi_flash app_update
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# requirements due to startup code
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# requirements due to startup code
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nvs_flash pthread app_trace
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nvs_flash pthread app_trace
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LDFRAGMENTS "linker.lf")
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LDFRAGMENTS "linker.lf")
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add_subdirectory(port)
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add_subdirectory(port)
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@ -140,8 +140,8 @@ void IRAM_ATTR call_start_cpu1(void)
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s_cpu_inited[1] = true;
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s_cpu_inited[1] = true;
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while(!s_resume_cores) {
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while (!s_resume_cores) {
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cpu_hal_delay_us(100);
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ets_delay_us(100);
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}
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}
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SYS_STARTUP_FN();
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SYS_STARTUP_FN();
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@ -172,12 +172,12 @@ static void start_other_core(void)
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volatile bool cpus_up = false;
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volatile bool cpus_up = false;
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while(!cpus_up){
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while (!cpus_up){
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cpus_up = true;
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cpus_up = true;
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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cpus_up &= s_cpu_up[i];
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cpus_up &= s_cpu_up[i];
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}
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}
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cpu_hal_delay_us(100);
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ets_delay_us(100);
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}
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}
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}
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}
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else {
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else {
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@ -190,12 +190,7 @@ static void start_other_core(void)
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static void intr_matrix_clear(void)
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static void intr_matrix_clear(void)
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{
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{
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#if CONFIG_IDF_TARGET_ESP32
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//Clear all the interrupt matrix register
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for (int i = ETS_WIFI_MAC_INTR_SOURCE; i <= ETS_CACHE_IA_INTR_SOURCE; i++) {
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#elif CONFIG_IDF_TARGET_ESP32S2
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for (int i = ETS_WIFI_MAC_INTR_SOURCE; i < ETS_MAX_INTR_SOURCE; i++) {
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for (int i = ETS_WIFI_MAC_INTR_SOURCE; i < ETS_MAX_INTR_SOURCE; i++) {
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#endif
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intr_matrix_set(0, i, ETS_INVALID_INUM);
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intr_matrix_set(0, i, ETS_INVALID_INUM);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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intr_matrix_set(1, i, ETS_INVALID_INUM);
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intr_matrix_set(1, i, ETS_INVALID_INUM);
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@ -232,12 +227,10 @@ void IRAM_ATTR call_start_cpu0(void)
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|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
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|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
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#endif
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#endif
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) {
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) {
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#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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}
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}
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#endif
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#endif
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@ -413,12 +406,12 @@ void IRAM_ATTR call_start_cpu0(void)
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volatile bool cpus_inited = false;
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volatile bool cpus_inited = false;
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while(!cpus_inited) {
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while (!cpus_inited) {
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cpus_inited = true;
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cpus_inited = true;
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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cpus_inited &= s_cpu_inited[i];
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cpus_inited &= s_cpu_inited[i];
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}
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}
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cpu_hal_delay_us(100);
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ets_delay_us(100);
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}
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}
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#endif
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#endif
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@ -54,10 +54,12 @@
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// [refactor-todo] make this file completely target-independent
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// [refactor-todo] make this file completely target-independent
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/uart.h"
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#include "esp32/rom/uart.h"
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#include "esp32/rom/ets_sys.h"
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#include "esp32/spiram.h"
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#include "esp32/spiram.h"
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#include "esp32/brownout.h"
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#include "esp32/brownout.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/uart.h"
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#include "esp32s2/rom/uart.h"
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#include "esp32s2/rom/ets_sys.h"
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#include "esp32s2/spiram.h"
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#include "esp32s2/spiram.h"
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#include "esp32s2/brownout.h"
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#include "esp32s2/brownout.h"
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#endif
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#endif
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@ -143,8 +145,8 @@ static void IRAM_ATTR do_system_init_fn(void)
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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static void IRAM_ATTR app_mainX_default(void)
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static void IRAM_ATTR app_mainX_default(void)
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{
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{
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while(1) {
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while (1) {
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cpu_hal_delay_us(UINT32_MAX);
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ets_delay_us(UINT32_MAX);
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}
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}
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}
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}
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@ -152,8 +154,8 @@ static void IRAM_ATTR start_cpuX_default(void)
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{
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{
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do_system_init_fn();
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do_system_init_fn();
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while(!s_system_full_inited) {
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while (!s_system_full_inited) {
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cpu_hal_delay_us(100);
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ets_delay_us(100);
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}
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}
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app_mainX();
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app_mainX();
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@ -192,12 +194,6 @@ static void IRAM_ATTR do_core_init(void)
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esp_brownout_init();
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esp_brownout_init();
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#endif
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#endif
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#if CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE || CONFIG_ESP32S2_DISABLE_BASIC_ROM_CONSOLE
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// [refactor-todo] leads to call chain `esp_efuse_read_field_blob` (efuse) -> `esp_efuse_utility_process` -> `ESP_LOGX`
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// syscall table must at least be init
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esp_efuse_disable_basic_rom_console();
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#endif
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#ifdef CONFIG_VFS_SUPPORT_IO
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#ifdef CONFIG_VFS_SUPPORT_IO
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esp_vfs_dev_uart_register();
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esp_vfs_dev_uart_register();
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#endif // CONFIG_VFS_SUPPORT_IO
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#endif // CONFIG_VFS_SUPPORT_IO
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@ -277,12 +273,12 @@ static void IRAM_ATTR do_secondary_init(void)
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// Wait for all cores to finish secondary init.
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// Wait for all cores to finish secondary init.
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volatile bool system_inited = false;
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volatile bool system_inited = false;
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while(!system_inited) {
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while (!system_inited) {
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system_inited = true;
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system_inited = true;
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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system_inited &= s_system_inited[i];
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system_inited &= s_system_inited[i];
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}
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}
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cpu_hal_delay_us(100);
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ets_delay_us(100);
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}
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}
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#endif
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#endif
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}
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}
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@ -336,13 +332,11 @@ void IRAM_ATTR start_cpu0_default(void)
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#endif
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#endif
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app_main();
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app_main();
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while(1);
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while (1);
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}
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}
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IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
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IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
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{
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{
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esp_err_t err;
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#ifdef CONFIG_PM_ENABLE
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#ifdef CONFIG_PM_ENABLE
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const int uart_clk_freq = REF_CLK_FREQ;
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const int uart_clk_freq = REF_CLK_FREQ;
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/* When DFS is enabled, use REFTICK as UART clock source */
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/* When DFS is enabled, use REFTICK as UART clock source */
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@ -350,9 +344,6 @@ IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
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uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
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uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
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#endif // CONFIG_ESP_CONSOLE_UART_NONE
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#endif // CONFIG_ESP_CONSOLE_UART_NONE
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err = esp_pthread_init();
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assert(err == ESP_OK && "Failed to init pthread module!");
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#ifdef CONFIG_PM_ENABLE
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#ifdef CONFIG_PM_ENABLE
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esp_pm_impl_init();
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esp_pm_impl_init();
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#ifdef CONFIG_PM_DFS_INIT_AUTO
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#ifdef CONFIG_PM_DFS_INIT_AUTO
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@ -473,50 +473,50 @@ extern void __real_app_main(void);
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static void main_task(void* args)
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static void main_task(void* args)
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{
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{
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#if !CONFIG_FREERTOS_UNICORE
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#if !CONFIG_FREERTOS_UNICORE
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// Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
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// Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
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while (port_xSchedulerRunning[1] == 0) {
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while (port_xSchedulerRunning[1] == 0) {
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;
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;
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}
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}
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#endif
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#endif
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// [refactor-todo] check if there is a way to move the following block to esp_system startup
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// [refactor-todo] check if there is a way to move the following block to esp_system startup
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heap_caps_enable_nonos_stack_heaps();
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heap_caps_enable_nonos_stack_heaps();
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// Now we have startup stack RAM available for heap, enable any DMA pool memory
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// Now we have startup stack RAM available for heap, enable any DMA pool memory
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#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
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#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
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if (g_spiram_ok) {
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if (g_spiram_ok) {
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esp_err_t r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
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esp_err_t r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
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if (r != ESP_OK) {
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if (r != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r);
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ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r);
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abort();
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abort();
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}
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}
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}
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}
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#endif
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#endif
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//Initialize task wdt if configured to do so
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//Initialize task wdt if configured to do so
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#ifdef CONFIG_ESP_TASK_WDT_PANIC
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#ifdef CONFIG_ESP_TASK_WDT_PANIC
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ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
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ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
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#elif CONFIG_ESP_TASK_WDT
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#elif CONFIG_ESP_TASK_WDT
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ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
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ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
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#endif
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#endif
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//Add IDLE 0 to task wdt
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//Add IDLE 0 to task wdt
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#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
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#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
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TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
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TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
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if(idle_0 != NULL){
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if(idle_0 != NULL){
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ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
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ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
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}
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}
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#endif
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#endif
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//Add IDLE 1 to task wdt
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//Add IDLE 1 to task wdt
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#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
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#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
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TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
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TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
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if(idle_1 != NULL){
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if(idle_1 != NULL){
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ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));
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ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));
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}
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}
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#endif
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#endif
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__real_app_main();
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__real_app_main();
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vTaskDelete(NULL);
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vTaskDelete(NULL);
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}
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}
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// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
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// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
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@ -529,7 +529,6 @@ static void main_task(void* args)
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#endif
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#endif
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#if !CONFIG_FREERTOS_UNICORE
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#if !CONFIG_FREERTOS_UNICORE
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void app_mainX(void)
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void app_mainX(void)
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{
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{
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abort();
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abort();
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}
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}
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// Wait for FreeRTOS initialization to finish on PRO CPU
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// Wait for FreeRTOS initialization to finish on PRO CPU
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while (port_xSchedulerRunning[0] == 0) {
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while (port_xSchedulerRunning[0] == 0) {
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;
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;
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}
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}
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#if CONFIG_APPTRACE_ENABLE
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#if CONFIG_APPTRACE_ENABLE
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// [refactor-todo] move to esp_system initialization
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// [refactor-todo] move to esp_system initialization
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esp_err_t err = esp_apptrace_init();
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esp_err_t err = esp_apptrace_init();
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assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
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assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
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#endif
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#endif
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#if CONFIG_ESP_INT_WDT
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#if CONFIG_ESP_INT_WDT
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//Initialize the interrupt watch dog for CPU1.
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//Initialize the interrupt watch dog for CPU1.
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esp_int_wdt_cpu_init();
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esp_int_wdt_cpu_init();
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#endif
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#endif
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esp_crosscore_int_init();
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esp_crosscore_int_init();
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esp_dport_access_int_init();
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esp_dport_access_int_init();
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ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
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ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
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xPortStartScheduler();
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xPortStartScheduler();
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abort(); /* Only get to here if FreeRTOS somehow very broken */
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abort(); /* Only get to here if FreeRTOS somehow very broken */
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}
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}
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#endif
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#endif
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void __wrap_app_main(void)
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void __wrap_app_main(void)
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{
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{
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#if CONFIG_ESP_INT_WDT
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#if CONFIG_ESP_INT_WDT
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esp_int_wdt_init();
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esp_int_wdt_init();
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//Initialize the interrupt watch dog for CPU0.
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//Initialize the interrupt watch dog for CPU0.
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esp_int_wdt_cpu_init();
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esp_int_wdt_cpu_init();
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#else
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#else
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!");
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assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!");
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#endif
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#endif
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#endif
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#endif
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esp_crosscore_int_init();
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esp_crosscore_int_init();
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#ifndef CONFIG_FREERTOS_UNICORE
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#ifndef CONFIG_FREERTOS_UNICORE
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esp_dport_access_int_init();
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esp_dport_access_int_init();
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||||||
#endif
|
#endif
|
||||||
|
|
||||||
portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
|
portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
|
||||||
ESP_TASK_MAIN_STACK, NULL,
|
ESP_TASK_MAIN_STACK, NULL,
|
||||||
ESP_TASK_MAIN_PRIO, NULL, 0);
|
ESP_TASK_MAIN_PRIO, NULL, 0);
|
||||||
assert(res == pdTRUE);
|
assert(res == pdTRUE);
|
||||||
|
|
||||||
// ESP32 has single core variants. Check that FreeRTOS has been configured properly.
|
// ESP32 has single core variants. Check that FreeRTOS has been configured properly.
|
||||||
#if CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
|
#if CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
|
||||||
if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU)) {
|
if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU)) {
|
||||||
ESP_EARLY_LOGE(TAG, "Running on single core chip, but FreeRTOS is built with dual core support.");
|
ESP_EARLY_LOGE(TAG, "Running on single core chip, but FreeRTOS is built with dual core support.");
|
||||||
ESP_EARLY_LOGE(TAG, "Please enable CONFIG_FREERTOS_UNICORE option in menuconfig.");
|
ESP_EARLY_LOGE(TAG, "Please enable CONFIG_FREERTOS_UNICORE option in menuconfig.");
|
||||||
abort();
|
abort();
|
||||||
}
|
}
|
||||||
#endif // CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
|
#endif // CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
|
||||||
|
|
||||||
ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
|
ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
|
||||||
vTaskStartScheduler();
|
vTaskStartScheduler();
|
||||||
}
|
}
|
|
@ -107,13 +107,6 @@ void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_tr
|
||||||
*/
|
*/
|
||||||
void cpu_hal_clear_watchpoint(int id);
|
void cpu_hal_clear_watchpoint(int id);
|
||||||
|
|
||||||
/*
|
|
||||||
* Insert a delay.
|
|
||||||
*
|
|
||||||
* @param delay_us length of delay in microseconds
|
|
||||||
*/
|
|
||||||
void cpu_hal_delay_us(uint32_t delay_us);
|
|
||||||
|
|
||||||
#endif // SOC_CPU_WATCHPOINTS_NUM > 0
|
#endif // SOC_CPU_WATCHPOINTS_NUM > 0
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -12,4 +12,4 @@
|
||||||
#define SOC_CAN_SUPPORTED 1
|
#define SOC_CAN_SUPPORTED 1
|
||||||
#define SOC_EMAC_SUPPORTED 1
|
#define SOC_EMAC_SUPPORTED 1
|
||||||
|
|
||||||
#define SOC_CPU_CORES_NUM 2
|
#define SOC_CPU_CORES_NUM 2
|
|
@ -67,9 +67,4 @@ void cpu_hal_clear_watchpoint(int id)
|
||||||
void cpu_hal_set_vecbase(const void* base)
|
void cpu_hal_set_vecbase(const void* base)
|
||||||
{
|
{
|
||||||
cpu_ll_set_vecbase(base);
|
cpu_ll_set_vecbase(base);
|
||||||
}
|
|
||||||
|
|
||||||
void cpu_hal_delay_us(uint32_t delay_us)
|
|
||||||
{
|
|
||||||
ets_delay_us(delay_us);
|
|
||||||
}
|
}
|
Loading…
Reference in a new issue