esp_system: fix various review issues
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5e59b4a812
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08cbfa6187
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@ -21,7 +21,7 @@
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#define MHZ (1000000)
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#define MHZ (1000000)
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// g_ticks_us defined in ROMs for PRO and APP CPU
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// g_ticks_us defined in ROMs
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extern uint32_t g_ticks_per_us_pro;
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extern uint32_t g_ticks_per_us_pro;
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int IRAM_ATTR esp_clk_cpu_freq(void)
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int IRAM_ATTR esp_clk_cpu_freq(void)
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@ -141,7 +141,7 @@ void IRAM_ATTR call_start_cpu1(void)
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s_cpu_inited[1] = true;
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s_cpu_inited[1] = true;
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while (!s_resume_cores) {
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while (!s_resume_cores) {
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cpu_hal_delay_us(100);
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ets_delay_us(100);
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}
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}
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SYS_STARTUP_FN();
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SYS_STARTUP_FN();
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@ -177,7 +177,7 @@ static void start_other_core(void)
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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cpus_up &= s_cpu_up[i];
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cpus_up &= s_cpu_up[i];
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}
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}
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cpu_hal_delay_us(100);
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ets_delay_us(100);
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}
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}
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}
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}
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else {
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else {
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@ -190,12 +190,7 @@ static void start_other_core(void)
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static void intr_matrix_clear(void)
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static void intr_matrix_clear(void)
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{
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{
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#if CONFIG_IDF_TARGET_ESP32
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//Clear all the interrupt matrix register
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for (int i = ETS_WIFI_MAC_INTR_SOURCE; i <= ETS_CACHE_IA_INTR_SOURCE; i++) {
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#elif CONFIG_IDF_TARGET_ESP32S2
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for (int i = ETS_WIFI_MAC_INTR_SOURCE; i < ETS_MAX_INTR_SOURCE; i++) {
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for (int i = ETS_WIFI_MAC_INTR_SOURCE; i < ETS_MAX_INTR_SOURCE; i++) {
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#endif
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intr_matrix_set(0, i, ETS_INVALID_INUM);
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intr_matrix_set(0, i, ETS_INVALID_INUM);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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intr_matrix_set(1, i, ETS_INVALID_INUM);
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intr_matrix_set(1, i, ETS_INVALID_INUM);
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@ -232,12 +227,10 @@ void IRAM_ATTR call_start_cpu0(void)
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|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
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|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
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#endif
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#endif
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) {
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) {
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#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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}
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}
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#endif
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#endif
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@ -418,7 +411,7 @@ void IRAM_ATTR call_start_cpu0(void)
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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cpus_inited &= s_cpu_inited[i];
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cpus_inited &= s_cpu_inited[i];
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}
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}
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cpu_hal_delay_us(100);
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ets_delay_us(100);
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}
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}
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#endif
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#endif
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@ -54,10 +54,12 @@
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// [refactor-todo] make this file completely target-independent
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// [refactor-todo] make this file completely target-independent
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/uart.h"
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#include "esp32/rom/uart.h"
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#include "esp32/rom/ets_sys.h"
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#include "esp32/spiram.h"
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#include "esp32/spiram.h"
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#include "esp32/brownout.h"
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#include "esp32/brownout.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/uart.h"
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#include "esp32s2/rom/uart.h"
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#include "esp32s2/rom/ets_sys.h"
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#include "esp32s2/spiram.h"
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#include "esp32s2/spiram.h"
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#include "esp32s2/brownout.h"
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#include "esp32s2/brownout.h"
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#endif
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#endif
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@ -144,7 +146,7 @@ static void IRAM_ATTR do_system_init_fn(void)
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static void IRAM_ATTR app_mainX_default(void)
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static void IRAM_ATTR app_mainX_default(void)
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{
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{
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while (1) {
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while (1) {
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cpu_hal_delay_us(UINT32_MAX);
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ets_delay_us(UINT32_MAX);
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}
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}
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}
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}
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@ -153,7 +155,7 @@ static void IRAM_ATTR start_cpuX_default(void)
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do_system_init_fn();
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do_system_init_fn();
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while (!s_system_full_inited) {
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while (!s_system_full_inited) {
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cpu_hal_delay_us(100);
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ets_delay_us(100);
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}
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}
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app_mainX();
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app_mainX();
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@ -192,12 +194,6 @@ static void IRAM_ATTR do_core_init(void)
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esp_brownout_init();
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esp_brownout_init();
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#endif
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#endif
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#if CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE || CONFIG_ESP32S2_DISABLE_BASIC_ROM_CONSOLE
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// [refactor-todo] leads to call chain `esp_efuse_read_field_blob` (efuse) -> `esp_efuse_utility_process` -> `ESP_LOGX`
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// syscall table must at least be init
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esp_efuse_disable_basic_rom_console();
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#endif
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#ifdef CONFIG_VFS_SUPPORT_IO
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#ifdef CONFIG_VFS_SUPPORT_IO
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esp_vfs_dev_uart_register();
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esp_vfs_dev_uart_register();
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#endif // CONFIG_VFS_SUPPORT_IO
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#endif // CONFIG_VFS_SUPPORT_IO
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@ -282,7 +278,7 @@ static void IRAM_ATTR do_secondary_init(void)
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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system_inited &= s_system_inited[i];
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system_inited &= s_system_inited[i];
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}
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}
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cpu_hal_delay_us(100);
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ets_delay_us(100);
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}
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}
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#endif
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#endif
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}
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}
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@ -341,8 +337,6 @@ void IRAM_ATTR start_cpu0_default(void)
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IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
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IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
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{
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{
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esp_err_t err;
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#ifdef CONFIG_PM_ENABLE
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#ifdef CONFIG_PM_ENABLE
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const int uart_clk_freq = REF_CLK_FREQ;
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const int uart_clk_freq = REF_CLK_FREQ;
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/* When DFS is enabled, use REFTICK as UART clock source */
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/* When DFS is enabled, use REFTICK as UART clock source */
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@ -350,9 +344,6 @@ IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
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uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
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uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
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#endif // CONFIG_ESP_CONSOLE_UART_NONE
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#endif // CONFIG_ESP_CONSOLE_UART_NONE
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err = esp_pthread_init();
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assert(err == ESP_OK && "Failed to init pthread module!");
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#ifdef CONFIG_PM_ENABLE
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#ifdef CONFIG_PM_ENABLE
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esp_pm_impl_init();
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esp_pm_impl_init();
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#ifdef CONFIG_PM_DFS_INIT_AUTO
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#ifdef CONFIG_PM_DFS_INIT_AUTO
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@ -529,7 +529,6 @@ static void main_task(void* args)
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#endif
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#endif
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#if !CONFIG_FREERTOS_UNICORE
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#if !CONFIG_FREERTOS_UNICORE
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void app_mainX(void)
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void app_mainX(void)
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{
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{
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@ -107,13 +107,6 @@ void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_tr
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*/
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*/
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void cpu_hal_clear_watchpoint(int id);
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void cpu_hal_clear_watchpoint(int id);
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/*
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* Insert a delay.
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*
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* @param delay_us length of delay in microseconds
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*/
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void cpu_hal_delay_us(uint32_t delay_us);
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#endif // SOC_CPU_WATCHPOINTS_NUM > 0
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#endif // SOC_CPU_WATCHPOINTS_NUM > 0
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/**
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/**
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@ -68,8 +68,3 @@ void cpu_hal_set_vecbase(const void* base)
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{
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{
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cpu_ll_set_vecbase(base);
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cpu_ll_set_vecbase(base);
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}
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}
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void cpu_hal_delay_us(uint32_t delay_us)
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{
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ets_delay_us(delay_us);
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}
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