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esp_system: fix various review issues

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This commit is contained in:
Renz Bagaporo 2020-06-09 08:17:48 +08:00 committed by Angus Gratton
parent 5e59b4a812
commit 08cbfa6187
8 changed files with 78 additions and 107 deletions
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2
components/esp32s2/clk.c
View file

@ -21,7 +21,7 @@
#define MHZ (1000000)
// g_ticks_us defined in ROMs for PRO and APP CPU
// g_ticks_us defined in ROMs
extern uint32_t g_ticks_per_us_pro;
int IRAM_ATTR esp_clk_cpu_freq(void)

4
components/esp_system/CMakeLists.txt
View file

@ -2,8 +2,8 @@ idf_component_register(SRCS "panic.c" "system_api.c" "startup.c"
INCLUDE_DIRS include
PRIV_INCLUDE_DIRS private_include
PRIV_REQUIRES spi_flash app_update
# requirements due to startup code
nvs_flash pthread app_trace
# requirements due to startup code
nvs_flash pthread app_trace
LDFRAGMENTS "linker.lf")
add_subdirectory(port)

19
components/esp_system/port/cpu_start.c
View file

@ -140,8 +140,8 @@ void IRAM_ATTR call_start_cpu1(void)
s_cpu_inited[1] = true;
while(!s_resume_cores) {
cpu_hal_delay_us(100);
while (!s_resume_cores) {
ets_delay_us(100);
}
SYS_STARTUP_FN();
@ -172,12 +172,12 @@ static void start_other_core(void)
volatile bool cpus_up = false;
while(!cpus_up){
while (!cpus_up){
cpus_up = true;
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
cpus_up &= s_cpu_up[i];
}
cpu_hal_delay_us(100);
ets_delay_us(100);
}
}
else {
@ -190,12 +190,7 @@ static void start_other_core(void)
static void intr_matrix_clear(void)
{
#if CONFIG_IDF_TARGET_ESP32
//Clear all the interrupt matrix register
for (int i = ETS_WIFI_MAC_INTR_SOURCE; i <= ETS_CACHE_IA_INTR_SOURCE; i++) {
#elif CONFIG_IDF_TARGET_ESP32S2
for (int i = ETS_WIFI_MAC_INTR_SOURCE; i < ETS_MAX_INTR_SOURCE; i++) {
#endif
intr_matrix_set(0, i, ETS_INVALID_INUM);
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
intr_matrix_set(1, i, ETS_INVALID_INUM);
@ -232,12 +227,10 @@ void IRAM_ATTR call_start_cpu0(void)
|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
#endif
) {
#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_disable(&rtc_wdt_ctx);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
#endif
}
#endif
@ -413,12 +406,12 @@ void IRAM_ATTR call_start_cpu0(void)
volatile bool cpus_inited = false;
while(!cpus_inited) {
while (!cpus_inited) {
cpus_inited = true;
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
cpus_inited &= s_cpu_inited[i];
}
cpu_hal_delay_us(100);
ets_delay_us(100);
}
#endif

27
components/esp_system/startup.c
View file

@ -54,10 +54,12 @@
// [refactor-todo] make this file completely target-independent
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/spiram.h"
#include "esp32/brownout.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/spiram.h"
#include "esp32s2/brownout.h"
#endif
@ -143,8 +145,8 @@ static void IRAM_ATTR do_system_init_fn(void)
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
static void IRAM_ATTR app_mainX_default(void)
{
while(1) {
cpu_hal_delay_us(UINT32_MAX);
while (1) {
ets_delay_us(UINT32_MAX);
}
}
@ -152,8 +154,8 @@ static void IRAM_ATTR start_cpuX_default(void)
{
do_system_init_fn();
while(!s_system_full_inited) {
cpu_hal_delay_us(100);
while (!s_system_full_inited) {
ets_delay_us(100);
}
app_mainX();
@ -192,12 +194,6 @@ static void IRAM_ATTR do_core_init(void)
esp_brownout_init();
#endif
#if CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE || CONFIG_ESP32S2_DISABLE_BASIC_ROM_CONSOLE
// [refactor-todo] leads to call chain `esp_efuse_read_field_blob` (efuse) -> `esp_efuse_utility_process` -> `ESP_LOGX`
// syscall table must at least be init
esp_efuse_disable_basic_rom_console();
#endif
#ifdef CONFIG_VFS_SUPPORT_IO
esp_vfs_dev_uart_register();
#endif // CONFIG_VFS_SUPPORT_IO
@ -277,12 +273,12 @@ static void IRAM_ATTR do_secondary_init(void)
// Wait for all cores to finish secondary init.
volatile bool system_inited = false;
while(!system_inited) {
while (!system_inited) {
system_inited = true;
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
system_inited &= s_system_inited[i];
}
cpu_hal_delay_us(100);
ets_delay_us(100);
}
#endif
}
@ -336,13 +332,11 @@ void IRAM_ATTR start_cpu0_default(void)
#endif
app_main();
while(1);
while (1);
}
IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
{
esp_err_t err;
#ifdef CONFIG_PM_ENABLE
const int uart_clk_freq = REF_CLK_FREQ;
/* When DFS is enabled, use REFTICK as UART clock source */
@ -350,9 +344,6 @@ IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
#endif // CONFIG_ESP_CONSOLE_UART_NONE
err = esp_pthread_init();
assert(err == ESP_OK && "Failed to init pthread module!");
#ifdef CONFIG_PM_ENABLE
esp_pm_impl_init();
#ifdef CONFIG_PM_DFS_INIT_AUTO

119
components/freertos/xtensa/port.c
View file

@ -473,50 +473,50 @@ extern void __real_app_main(void);
static void main_task(void* args)
{
#if !CONFIG_FREERTOS_UNICORE
// Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
while (port_xSchedulerRunning[1] == 0) {
;
}
// Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
while (port_xSchedulerRunning[1] == 0) {
;
}
#endif
// [refactor-todo] check if there is a way to move the following block to esp_system startup
heap_caps_enable_nonos_stack_heaps();
heap_caps_enable_nonos_stack_heaps();
// Now we have startup stack RAM available for heap, enable any DMA pool memory
// Now we have startup stack RAM available for heap, enable any DMA pool memory
#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
if (g_spiram_ok) {
esp_err_t r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
if (r != ESP_OK) {
ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r);
abort();
}
}
if (g_spiram_ok) {
esp_err_t r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
if (r != ESP_OK) {
ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r);
abort();
}
}
#endif
//Initialize task wdt if configured to do so
//Initialize task wdt if configured to do so
#ifdef CONFIG_ESP_TASK_WDT_PANIC
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
#elif CONFIG_ESP_TASK_WDT
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
#endif
//Add IDLE 0 to task wdt
//Add IDLE 0 to task wdt
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
if(idle_0 != NULL){
ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
}
TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
if(idle_0 != NULL){
ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
}
#endif
//Add IDLE 1 to task wdt
//Add IDLE 1 to task wdt
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
if(idle_1 != NULL){
ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));
}
TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
if(idle_1 != NULL){
ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));
}
#endif
__real_app_main();
vTaskDelete(NULL);
__real_app_main();
vTaskDelete(NULL);
}
// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
@ -529,7 +529,6 @@ static void main_task(void* args)
#endif
#if !CONFIG_FREERTOS_UNICORE
void app_mainX(void)
{
@ -538,63 +537,63 @@ void app_mainX(void)
abort();
}
// Wait for FreeRTOS initialization to finish on PRO CPU
while (port_xSchedulerRunning[0] == 0) {
;
}
// Wait for FreeRTOS initialization to finish on PRO CPU
while (port_xSchedulerRunning[0] == 0) {
;
}
#if CONFIG_APPTRACE_ENABLE
// [refactor-todo] move to esp_system initialization
esp_err_t err = esp_apptrace_init();
assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
// [refactor-todo] move to esp_system initialization
esp_err_t err = esp_apptrace_init();
assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
#endif
#if CONFIG_ESP_INT_WDT
//Initialize the interrupt watch dog for CPU1.
esp_int_wdt_cpu_init();
//Initialize the interrupt watch dog for CPU1.
esp_int_wdt_cpu_init();
#endif
esp_crosscore_int_init();
esp_dport_access_int_init();
esp_crosscore_int_init();
esp_dport_access_int_init();
ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
xPortStartScheduler();
abort(); /* Only get to here if FreeRTOS somehow very broken */
ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
xPortStartScheduler();
abort(); /* Only get to here if FreeRTOS somehow very broken */
}
#endif
void __wrap_app_main(void)
{
#if CONFIG_ESP_INT_WDT
esp_int_wdt_init();
//Initialize the interrupt watch dog for CPU0.
esp_int_wdt_cpu_init();
esp_int_wdt_init();
//Initialize the interrupt watch dog for CPU0.
esp_int_wdt_cpu_init();
#else
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!");
assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!");
#endif
#endif
esp_crosscore_int_init();
esp_crosscore_int_init();
#ifndef CONFIG_FREERTOS_UNICORE
esp_dport_access_int_init();
esp_dport_access_int_init();
#endif
portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
ESP_TASK_MAIN_STACK, NULL,
ESP_TASK_MAIN_PRIO, NULL, 0);
assert(res == pdTRUE);
portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
ESP_TASK_MAIN_STACK, NULL,
ESP_TASK_MAIN_PRIO, NULL, 0);
assert(res == pdTRUE);
// ESP32 has single core variants. Check that FreeRTOS has been configured properly.
#if CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU)) {
ESP_EARLY_LOGE(TAG, "Running on single core chip, but FreeRTOS is built with dual core support.");
ESP_EARLY_LOGE(TAG, "Please enable CONFIG_FREERTOS_UNICORE option in menuconfig.");
abort();
}
if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU)) {
ESP_EARLY_LOGE(TAG, "Running on single core chip, but FreeRTOS is built with dual core support.");
ESP_EARLY_LOGE(TAG, "Please enable CONFIG_FREERTOS_UNICORE option in menuconfig.");
abort();
}
#endif // CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
vTaskStartScheduler();
ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
vTaskStartScheduler();
}

7
components/soc/include/hal/cpu_hal.h
View file

@ -107,13 +107,6 @@ void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_tr
*/
void cpu_hal_clear_watchpoint(int id);
/*
* Insert a delay.
*
* @param delay_us length of delay in microseconds
*/
void cpu_hal_delay_us(uint32_t delay_us);
#endif // SOC_CPU_WATCHPOINTS_NUM > 0
/**

2
components/soc/soc/esp32/include/soc/soc_caps.h
View file

@ -12,4 +12,4 @@
#define SOC_CAN_SUPPORTED 1
#define SOC_EMAC_SUPPORTED 1
#define SOC_CPU_CORES_NUM 2
#define SOC_CPU_CORES_NUM 2

5
components/soc/src/hal/cpu_hal.c
View file

@ -67,9 +67,4 @@ void cpu_hal_clear_watchpoint(int id)
void cpu_hal_set_vecbase(const void* base)
{
cpu_ll_set_vecbase(base);
}
void cpu_hal_delay_us(uint32_t delay_us)
{
ets_delay_us(delay_us);
}