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soc: Fix esp_ptr_executable() for single core ESP32 config & cache memory

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In single core mode, APP CPU cache region is added to the available range.
This commit is contained in:
Angus Gratton 2020-01-03 14:31:16 +11:00 committed by Angus Gratton
parent 3386cb5400
commit 07387fbd29
1 changed files with 4 additions and 0 deletions
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4
components/soc/include/soc/soc_memory_layout.h
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@ -154,6 +154,10 @@ inline static bool IRAM_ATTR esp_ptr_executable(const void *p)
intptr_t ip = (intptr_t) p; intptr_t ip = (intptr_t) p;
return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH) return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH)
|| (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH) || (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH)
|| (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH)
#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_FREERTOS_UNICORE)
|| (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
#endif
|| (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH); || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH);
} }