Crash_Override/OVMS3-idf
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bootloader, rtc: don't disable PLL if it is already enabled

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This commit is contained in:
Ivan Grokhotkov 2020-04-30 16:50:41 +02:00
parent 19c73192ba
commit 0620890028
2 changed files with 22 additions and 18 deletions
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5
components/bootloader_support/src/bootloader_clock.c
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@ -21,9 +21,11 @@
#ifdef CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h" #include "esp32/rom/uart.h"
#include "esp32/rom/rtc.h" #include "esp32/rom/rtc.h"
#define CPU_RESET_REASON SW_CPU_RESET
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/uart.h" #include "esp32s2/rom/uart.h"
#include "esp32s2/rom/rtc.h" #include "esp32s2/rom/rtc.h"
#define CPU_RESET_REASON RTC_SW_CPU_RESET
#endif #endif
void bootloader_clock_configure(void) void bootloader_clock_configure(void)
@ -50,7 +52,7 @@ void bootloader_clock_configure(void)
cpu_freq_mhz = 240; cpu_freq_mhz = 240;
} }
#endif #endif
if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {
rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT(); rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ; clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
@ -65,6 +67,7 @@ void bootloader_clock_configure(void)
* part of the start up time by enabling 32k XTAL early. * part of the start up time by enabling 32k XTAL early.
* App startup code will wait until the oscillator has started up. * App startup code will wait until the oscillator has started up.
*/ */
}
/* TODO: move the clock option into esp_system, so that this doesn't have /* TODO: move the clock option into esp_system, so that this doesn't have
* to continue: * to continue:

7
components/soc/src/esp32s2/rtc_clk.c
View file

@ -41,7 +41,8 @@ static const char *TAG = "rtc_clk";
#define RTC_PLL_FREQ_480M 480 #define RTC_PLL_FREQ_480M 480
// Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled. // Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
static int s_cur_pll_freq; // On the ESP32-S2, 480MHz PLL is enabled at reset.
static int s_cur_pll_freq = RTC_PLL_FREQ_480M;
static void rtc_clk_cpu_freq_to_8m(void); static void rtc_clk_cpu_freq_to_8m(void);
@ -374,7 +375,7 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config)
if (soc_clk_sel != DPORT_SOC_CLK_SEL_XTAL) { if (soc_clk_sel != DPORT_SOC_CLK_SEL_XTAL) {
rtc_clk_cpu_freq_to_xtal(xtal_freq, 1); rtc_clk_cpu_freq_to_xtal(xtal_freq, 1);
} }
if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) { if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL && config->source_freq_mhz != s_cur_pll_freq) {
rtc_clk_bbpll_disable(); rtc_clk_bbpll_disable();
} }
if (config->source == RTC_CPU_FREQ_SRC_XTAL) { if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
@ -463,7 +464,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
int freq_mhz = (int) rtc_clk_xtal_freq_get(); int freq_mhz = (int) rtc_clk_xtal_freq_get();
rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
rtc_clk_bbpll_disable(); /* BBPLL is kept enabled */
} }
/** /**