header files: clean up

1. format;
2. Slow RTC memory reverse 2KB;
This commit is contained in:
Wu Jian Gang 2016-09-05 16:20:26 +08:00
parent 24011ddd05
commit 04b53643ef
12 changed files with 223 additions and 225 deletions

View file

@ -11,6 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_AES_H_
#define _ROM_AES_H_

View file

@ -11,6 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_BIGINT_H_
#define _ROM_BIGINT_H_

View file

@ -11,6 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_CACHE_H_
#define _ROM_CACHE_H_
@ -92,7 +93,6 @@ unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsign
* 4 : mmu table to be written is out of range
* 5 : vaddr is out of range
*/
unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
/**

View file

@ -11,9 +11,12 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef ROM_CRC_H
#define ROM_CRC_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif

View file

@ -11,9 +11,12 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_EFUSE_H_
#define _ROM_EFUSE_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
@ -35,7 +38,7 @@ extern "C" {
*
* @return null
*/
void ets_efuse_read_op(viid);
void ets_efuse_read_op(void);
/**
* @brief Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again.
@ -54,7 +57,7 @@ void ets_efuse_program_op(void);
*
* @return u32: 1 for 100KHZ.
*/
u32 ets_efuse_get_8M_clock(void);
uint32_t ets_efuse_get_8M_clock(void);
/**
* @brief Read spi pad configuration, show gpio number of flash pad, includes 5 pads.
@ -64,7 +67,6 @@ u32 ets_efuse_get_8M_clock(void);
* @return uint32_t: 0, invalid, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*/
uint32_t ets_efuse_get_spiconfig(void);
/**
@ -82,7 +84,6 @@ unsigned char esp_crc8(unsigned char const * p, unsigned int len);
* @}
*/
#ifdef __cplusplus
}
#endif

View file

@ -51,7 +51,6 @@ extern "C" {
* @{
*/
typedef enum {
ETS_OK = 0, /**< return successful in ets*/
ETS_FAILED = 1 /**< return failed in ets*/
@ -118,6 +117,7 @@ void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen);
* @return ETS_FAILED : post failed
*/
ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
/**
* @}
*/
@ -130,7 +130,6 @@ ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
* @{
*/
extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/
/**
@ -196,11 +195,11 @@ ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool
* @return ETS_FAILED : unpack failed
*/
ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config);
/**
* @}
*/
/** \defgroup ets_printf_apis, ets_printf related apis used in ets
* @brief ets printf apis
*/
@ -275,7 +274,6 @@ void ets_install_uart_printf(void);
* @}
*/
/** \defgroup ets_timer_apis, ets_timer related apis used in ets
* @brief ets timer apis
*/
@ -393,7 +391,7 @@ void ets_update_cpu_frequency(uint32_t ticks_per_us);
*
* @return uint32_t : CPU ticks per us record in ets.
*/
uint32_t ets_get_cpu_frequency();
uint32_t ets_get_cpu_frequency(void);
/**
* @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module.
@ -402,7 +400,7 @@ uint32_t ets_get_cpu_frequency();
*
* @return uint32_t : xtal_freq/analog_8M*256.
*/
uint32_t ets_get_xtal_scale();
uint32_t ets_get_xtal_scale(void);
/**
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
@ -415,14 +413,12 @@ uint32_t ets_get_xtal_scale();
* clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40;
* else clock = 26M.
*/
uint32_t ets_get_detected_xtal_freq();
uint32_t ets_get_detected_xtal_freq(void);
/**
* @}
*/
/** \defgroup ets_intr_apis, ets interrupt configure related apis
* @brief ets intr apis
*/
@ -596,19 +592,19 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
#define ETS_SLC_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_SLC_INUM)
#endif
/**
* @}
*/
#ifndef MAC2STR
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
#endif
#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
/**
* @}
*/

View file

@ -33,7 +33,6 @@ extern "C" {
* @{
*/
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
#define GPIO_PIN_COUNT 40
@ -200,7 +199,7 @@ void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
*
* @return None
*/
void gpio_pin_wakeup_disable();
void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.

View file

@ -44,8 +44,8 @@ extern "C" {
*************************************************************************************
* rtc memory addr type size usage
* 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
* 0x3ff61000+SIZE_CP Slow 7936-SIZE_CP
* 0x3ff62f00 Slow 256 Reserved
* 0x3ff61000+SIZE_CP Slow 6144-SIZE_CP
* 0x3ff62800 Slow 2048 Reserved
*
* 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code
*

View file

@ -11,6 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SECURE_BOOT_H_
#define _ROM_SECURE_BOOT_H_

View file

@ -11,6 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
@ -216,9 +217,6 @@ void SelectSpiFunction(uint32_t ishspi);
*/
void spi_flash_attach(uint32_t ishspi, bool legacy);
//void spi_cache_sram_init();
/**
* @brief SPI Read Flash status register. We use CMD 0x05.
* Please do not call this function in SDK.
@ -337,7 +335,7 @@ uint16_t SPI_Common_Command(SpiCommonCmd * cmd);
* SPI_FLASH_RESULT_ERR : Unlock error.
* SPI_FLASH_RESULT_TIMEOUT : Unlock timeout.
*/
SpiFlashOpResult SPIUnlock();
SpiFlashOpResult SPIUnlock(void);
/**
* @brief SPI write protect.
@ -349,7 +347,7 @@ SpiFlashOpResult SPIUnlock();
* SPI_FLASH_RESULT_ERR : Lock error.
* SPI_FLASH_RESULT_TIMEOUT : Lock timeout.
*/
SpiFlashOpResult SPILock();
SpiFlashOpResult SPILock(void);
/**
* @brief Update SPI Flash parameter.
@ -445,7 +443,7 @@ SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t* src, int32_t len);
*
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
*
* @param uint32_t* data : The buf to read the data.
* @param uint32_t *dest : The buf to read the data.
*
* @param uint32_t len : Length to read, should be 4 bytes aligned.
*
@ -463,7 +461,7 @@ SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t* dest, int32_t len);
*
* @return None
*/
void SPI_Write_Encrypt_Enable();
void SPI_Write_Encrypt_Enable(void);
/**
* @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
@ -487,7 +485,7 @@ SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t* data);
*
* @return None
*/
void SPI_Write_Encrypt_Disable();
void SPI_Write_Encrypt_Disable(void);
/**
* @brief Encrpto writing data to flash, you should Erase it yourself if need.

16
components/esp32/include/rom/uart.h Executable file → Normal file
View file

@ -129,7 +129,7 @@ typedef struct {
uint8_t *pRcvMsgBuff;
uint8_t *pWritePos;
uint8_t *pReadPos;
uint8_t TrigLvl; //JLU: may need to pad
uint8_t TrigLvl;
RcvMsgBuffState BuffState;
} RcvMsgBuff;
@ -169,7 +169,7 @@ typedef struct{
*
* @return None
*/
void uartAttach();
void uartAttach(void);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
@ -340,10 +340,10 @@ STATUS UartGetCmdLn(uint8_t * pCmdLn);
*
* @return UartDevice * : uart configuration struct pointer.
*/
UartDevice * GetUartDevice();
UartDevice *GetUartDevice(void);
/**
* @brief Send an packet to download tool, with ESC char.
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to output string.
@ -355,7 +355,7 @@ UartDevice * GetUartDevice();
void send_packet(uint8_t *p, int len);
/**
* @brief Receive an packet from download tool, with ESC char.
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to input string.
@ -369,9 +369,8 @@ void send_packet(uint8_t *p, int len);
*/
int recv_packet(uint8_t *p, int len, uint8_t is_sync);
/**
* @brief Send an packet to download tool, with ESC char.
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *pData : the pointer to input string.
@ -383,9 +382,8 @@ int recv_packet(uint8_t *p, int len, uint8_t is_sync);
*/
STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
/**
* @brief Receive an packet from download tool, with ESC char.
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *pData : the pointer to input string.