423 lines
14 KiB
C
423 lines
14 KiB
C
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_EFUSE_REG_H_
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#define _SOC_EFUSE_REG_H_
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#include "soc.h"
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#define EFUSE_BLK0_RDATA0 (DR_REG_EFUSE_BASE + 0x000)
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#define EFUSE_RD_FLASH_CRYPT_CNT 0x000000FF
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#define EFUSE_RD_FLASH_CRYPT_CNT_S 20
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#define EFUSE_RD_EFUSE_RD_DIS 0x0000000F
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#define EFUSE_RD_EFUSE_RD_DIS_S 16
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#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF
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#define EFUSE_RD_EFUSE_WR_DIS_S 0
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#define EFUSE_BLK0_RDATA1 (DR_REG_EFUSE_BASE + 0x004)
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#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF
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#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0
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#define EFUSE_BLK0_RDATA2 (DR_REG_EFUSE_BASE + 0x008)
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#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF
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#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0
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#define EFUSE_BLK0_RDATA3 (DR_REG_EFUSE_BASE + 0x00c)
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#define EFUSE_RD_CHIP_VER_RESERVE 0x00001FFF
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#define EFUSE_RD_CHIP_VER_RESERVE_S 4
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#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3))
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#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3
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#define EFUSE_RD_CHIP_VER_32PAD (BIT(2))
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#define EFUSE_RD_CHIP_VER_32PAD_S 2
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#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1))
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#define EFUSE_RD_CHIP_VER_DIS_BT_S 1
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#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0))
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#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0
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#define EFUSE_BLK0_RDATA4 (DR_REG_EFUSE_BASE + 0x010)
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#define EFUSE_RD_SDIO_FORCE (BIT(16))
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#define EFUSE_RD_SDIO_FORCE_S 16
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#define EFUSE_RD_SDIO_TIEH (BIT(15))
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#define EFUSE_RD_SDIO_TIEH_S 15
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#define EFUSE_RD_XPD_SDIO_REG (BIT(14))
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#define EFUSE_RD_XPD_SDIO_REG_S 14
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#define EFUSE_RD_SDIO_DREFL 0x00000003
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#define EFUSE_RD_SDIO_DREFL_S 12
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#define EFUSE_RD_SDIO_DREFM 0x00000003
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#define EFUSE_RD_SDIO_DREFM_S 10
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#define EFUSE_RD_SDIO_DREFH 0x00000003
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#define EFUSE_RD_SDIO_DREFH_S 8
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#define EFUSE_RD_CK8M_FREQ 0x000000FF
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#define EFUSE_RD_CK8M_FREQ_S 0
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#define EFUSE_BLK0_RDATA5 (DR_REG_EFUSE_BASE + 0x014)
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#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F
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#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28
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#define EFUSE_RD_INST_CONFIG 0x000000FF
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#define EFUSE_RD_INST_CONFIG_S 20
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#define EFUSE_RD_SPI_PAD_CONFIG 0x000FFFFF
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#define EFUSE_RD_SPI_PAD_CONFIG_S 0
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#define EFUSE_BLK0_RDATA6 (DR_REG_EFUSE_BASE + 0x018)
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#define EFUSE_RD_KEY_STATUS (BIT(10))
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#define EFUSE_RD_KEY_STATUS_S 10
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#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9))
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#define EFUSE_RD_DISABLE_DL_CACHE_S 9
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#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8))
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#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8
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#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7))
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#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7
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#define EFUSE_RD_DISABLE_JTAG (BIT(6))
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#define EFUSE_RD_DISABLE_JTAG_S 6
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#define EFUSE_RD_ABS_DONE_1 (BIT(5))
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#define EFUSE_RD_ABS_DONE_1_S 5
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#define EFUSE_RD_ABS_DONE_0 (BIT(4))
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#define EFUSE_RD_ABS_DONE_0_S 4
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#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3))
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#define EFUSE_RD_DISABLE_SDIO_HOST_S 3
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#define EFUSE_RD_DIG_RESERVE (BIT(2))
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#define EFUSE_RD_DIG_RESERVE_S 2
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#define EFUSE_RD_CODING_SCHEME 0x00000003
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#define EFUSE_RD_CODING_SCHEME_S 0
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#define EFUSE_BLK0_WDATA0 (DR_REG_EFUSE_BASE + 0x01c)
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#define EFUSE_FLASH_CRYPT_CNT 0x000000FF
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#define EFUSE_FLASH_CRYPT_CNT_S 20
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#define EFUSE_EFUSE_RD_DIS 0x0000000F
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#define EFUSE_EFUSE_RD_DIS_S 16
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#define EFUSE_EFUSE_WR_DIS 0x0000FFFF
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#define EFUSE_EFUSE_WR_DIS_S 0
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#define EFUSE_BLK0_WDATA1 (DR_REG_EFUSE_BASE + 0x020)
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#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF
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#define EFUSE_WIFI_MAC_CRC_LOW_S 0
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#define EFUSE_BLK0_WDATA2 (DR_REG_EFUSE_BASE + 0x024)
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#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF
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#define EFUSE_WIFI_MAC_CRC_HIGH_S 0
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#define EFUSE_BLK0_WDATA3 (DR_REG_EFUSE_BASE + 0x028)
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#define EFUSE_CHIP_VER_RESERVE 0x00001FFF
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#define EFUSE_CHIP_VER_RESERVE_S 4
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#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3))
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#define EFUSE_CHIP_VER_DIS_CACHE_S 3
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#define EFUSE_CHIP_VER_32PAD (BIT(2))
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#define EFUSE_CHIP_VER_32PAD_S 2
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#define EFUSE_CHIP_VER_DIS_BT (BIT(1))
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#define EFUSE_CHIP_VER_DIS_BT_S 1
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#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0))
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#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0
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#define EFUSE_BLK0_WDATA4 (DR_REG_EFUSE_BASE + 0x02c)
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#define EFUSE_SDIO_FORCE (BIT(16))
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#define EFUSE_SDIO_FORCE_S 16
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#define EFUSE_SDIO_TIEH (BIT(15))
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#define EFUSE_SDIO_TIEH_S 15
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#define EFUSE_XPD_SDIO_REG (BIT(14))
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#define EFUSE_XPD_SDIO_REG_S 14
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#define EFUSE_SDIO_DREFL 0x00000003
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#define EFUSE_SDIO_DREFL_S 12
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#define EFUSE_SDIO_DREFM 0x00000003
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#define EFUSE_SDIO_DREFM_S 10
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#define EFUSE_SDIO_DREFH 0x00000003
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#define EFUSE_SDIO_DREFH_S 8
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#define EFUSE_CK8M_FREQ 0x000000FF
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#define EFUSE_CK8M_FREQ_S 0
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#define EFUSE_BLK0_WDATA5 (DR_REG_EFUSE_BASE + 0x030)
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#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F
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#define EFUSE_FLASH_CRYPT_CONFIG_S 28
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#define EFUSE_INST_CONFIG 0x000000FF
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#define EFUSE_INST_CONFIG_S 20
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#define EFUSE_SPI_PAD_CONFIG 0x000FFFFF
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#define EFUSE_SPI_PAD_CONFIG_S 0
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#define EFUSE_BLK0_WDATA6 (DR_REG_EFUSE_BASE + 0x034)
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#define EFUSE_KEY_STATUS (BIT(10))
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#define EFUSE_KEY_STATUS_S 10
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#define EFUSE_DISABLE_DL_CACHE (BIT(9))
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#define EFUSE_DISABLE_DL_CACHE_S 9
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#define EFUSE_DISABLE_DL_DECRYPT (BIT(8))
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#define EFUSE_DISABLE_DL_DECRYPT_S 8
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#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7))
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#define EFUSE_DISABLE_DL_ENCRYPT_S 7
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#define EFUSE_DISABLE_JTAG (BIT(6))
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#define EFUSE_DISABLE_JTAG_S 6
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#define EFUSE_ABS_DONE_1 (BIT(5))
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#define EFUSE_ABS_DONE_1_S 5
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#define EFUSE_ABS_DONE_0 (BIT(4))
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#define EFUSE_ABS_DONE_0_S 4
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#define EFUSE_DISABLE_SDIO_HOST (BIT(3))
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#define EFUSE_DISABLE_SDIO_HOST_S 3
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#define EFUSE_DIG_RESERVE (BIT(2))
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#define EFUSE_DIG_RESERVE_S 2
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#define EFUSE_CODING_SCHEME 0x00000003
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#define EFUSE_CODING_SCHEME_S 0
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#define EFUSE_BLK1_RDATA0 (DR_REG_EFUSE_BASE + 0x038)
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#define EFUSE_EFUSE_BLK1_DOUT0 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DOUT0_S 0
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#define EFUSE_BLK1_RDATA1 (DR_REG_EFUSE_BASE + 0x03c)
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#define EFUSE_EFUSE_BLK1_DOUT1 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DOUT1_S 0
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#define EFUSE_BLK1_RDATA2 (DR_REG_EFUSE_BASE + 0x040)
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#define EFUSE_EFUSE_BLK1_DOUT2 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DOUT2_S 0
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#define EFUSE_BLK1_RDATA3 (DR_REG_EFUSE_BASE + 0x044)
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#define EFUSE_EFUSE_BLK1_DOUT3 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DOUT3_S 0
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#define EFUSE_BLK1_RDATA4 (DR_REG_EFUSE_BASE + 0x048)
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#define EFUSE_EFUSE_BLK1_DOUT4 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DOUT4_S 0
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#define EFUSE_BLK1_RDATA5 (DR_REG_EFUSE_BASE + 0x04c)
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#define EFUSE_EFUSE_BLK1_DOUT5 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DOUT5_S 0
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#define EFUSE_BLK1_RDATA6 (DR_REG_EFUSE_BASE + 0x050)
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#define EFUSE_EFUSE_BLK1_DOUT6 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DOUT6_S 0
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#define EFUSE_BLK1_RDATA7 (DR_REG_EFUSE_BASE + 0x054)
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#define EFUSE_EFUSE_BLK1_DOUT7 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DOUT7_S 0
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#define EFUSE_BLK2_RDATA0 (DR_REG_EFUSE_BASE + 0x058)
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#define EFUSE_EFUSE_BLK2_DOUT0 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DOUT0_S 0
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#define EFUSE_BLK2_RDATA1 (DR_REG_EFUSE_BASE + 0x05c)
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#define EFUSE_EFUSE_BLK2_DOUT1 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DOUT1_S 0
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#define EFUSE_BLK2_RDATA2 (DR_REG_EFUSE_BASE + 0x060)
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#define EFUSE_EFUSE_BLK2_DOUT2 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DOUT2_S 0
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#define EFUSE_BLK2_RDATA3 (DR_REG_EFUSE_BASE + 0x064)
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#define EFUSE_EFUSE_BLK2_DOUT3 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DOUT3_S 0
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#define EFUSE_BLK2_RDATA4 (DR_REG_EFUSE_BASE + 0x068)
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#define EFUSE_EFUSE_BLK2_DOUT4 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DOUT4_S 0
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#define EFUSE_BLK2_RDATA5 (DR_REG_EFUSE_BASE + 0x06c)
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#define EFUSE_EFUSE_BLK2_DOUT5 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DOUT5_S 0
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#define EFUSE_BLK2_RDATA6 (DR_REG_EFUSE_BASE + 0x070)
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#define EFUSE_EFUSE_BLK2_DOUT6 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DOUT6_S 0
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#define EFUSE_BLK2_RDATA7 (DR_REG_EFUSE_BASE + 0x074)
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#define EFUSE_EFUSE_BLK2_DOUT7 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DOUT7_S 0
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#define EFUSE_BLK3_RDATA0 (DR_REG_EFUSE_BASE + 0x078)
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#define EFUSE_EFUSE_BLK3_DOUT0 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DOUT0_S 0
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#define EFUSE_BLK3_RDATA1 (DR_REG_EFUSE_BASE + 0x07c)
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#define EFUSE_EFUSE_BLK3_DOUT1 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DOUT1_S 0
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#define EFUSE_BLK3_RDATA2 (DR_REG_EFUSE_BASE + 0x080)
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#define EFUSE_EFUSE_BLK3_DOUT2 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DOUT2_S 0
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#define EFUSE_BLK3_RDATA3 (DR_REG_EFUSE_BASE + 0x084)
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#define EFUSE_EFUSE_BLK3_DOUT3 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DOUT3_S 0
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#define EFUSE_BLK3_RDATA4 (DR_REG_EFUSE_BASE + 0x088)
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#define EFUSE_EFUSE_BLK3_DOUT4 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DOUT4_S 0
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#define EFUSE_BLK3_RDATA5 (DR_REG_EFUSE_BASE + 0x08c)
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#define EFUSE_EFUSE_BLK3_DOUT5 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DOUT5_S 0
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#define EFUSE_BLK3_RDATA6 (DR_REG_EFUSE_BASE + 0x090)
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#define EFUSE_EFUSE_BLK3_DOUT6 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DOUT6_S 0
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#define EFUSE_BLK3_RDATA7 (DR_REG_EFUSE_BASE + 0x094)
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#define EFUSE_EFUSE_BLK3_DOUT7 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DOUT7_S 0
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#define EFUSE_BLK1_WDATA0 (DR_REG_EFUSE_BASE + 0x098)
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#define EFUSE_EFUSE_BLK1_DIN0 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DIN0_S 0
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#define EFUSE_BLK1_WDATA1 (DR_REG_EFUSE_BASE + 0x09c)
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#define EFUSE_EFUSE_BLK1_DIN1 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DIN1_S 0
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#define EFUSE_BLK1_WDATA2 (DR_REG_EFUSE_BASE + 0x0a0)
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#define EFUSE_EFUSE_BLK1_DIN2 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DIN2_S 0
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#define EFUSE_BLK1_WDATA3 (DR_REG_EFUSE_BASE + 0x0a4)
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#define EFUSE_EFUSE_BLK1_DIN3 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DIN3_S 0
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#define EFUSE_BLK1_WDATA4 (DR_REG_EFUSE_BASE + 0x0a8)
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#define EFUSE_EFUSE_BLK1_DIN4 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DIN4_S 0
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#define EFUSE_BLK1_WDATA5 (DR_REG_EFUSE_BASE + 0x0ac)
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#define EFUSE_EFUSE_BLK1_DIN5 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DIN5_S 0
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#define EFUSE_BLK1_WDATA6 (DR_REG_EFUSE_BASE + 0x0b0)
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#define EFUSE_EFUSE_BLK1_DIN6 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DIN6_S 0
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#define EFUSE_BLK1_WDATA7 (DR_REG_EFUSE_BASE + 0x0b4)
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#define EFUSE_EFUSE_BLK1_DIN7 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK1_DIN7_S 0
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#define EFUSE_BLK2_WDATA0 (DR_REG_EFUSE_BASE + 0x0b8)
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#define EFUSE_EFUSE_BLK2_DIN0 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DIN0_S 0
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#define EFUSE_BLK2_WDATA1 (DR_REG_EFUSE_BASE + 0x0bc)
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#define EFUSE_EFUSE_BLK2_DIN1 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DIN1_S 0
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#define EFUSE_BLK2_WDATA2 (DR_REG_EFUSE_BASE + 0x0c0)
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#define EFUSE_EFUSE_BLK2_DIN2 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DIN2_S 0
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#define EFUSE_BLK2_WDATA3 (DR_REG_EFUSE_BASE + 0x0c4)
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#define EFUSE_EFUSE_BLK2_DIN3 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DIN3_S 0
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#define EFUSE_BLK2_WDATA4 (DR_REG_EFUSE_BASE + 0x0c8)
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#define EFUSE_EFUSE_BLK2_DIN4 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DIN4_S 0
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#define EFUSE_BLK2_WDATA5 (DR_REG_EFUSE_BASE + 0x0cc)
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#define EFUSE_EFUSE_BLK2_DIN5 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DIN5_S 0
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#define EFUSE_BLK2_WDATA6 (DR_REG_EFUSE_BASE + 0x0d0)
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#define EFUSE_EFUSE_BLK2_DIN6 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DIN6_S 0
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#define EFUSE_BLK2_WDATA7 (DR_REG_EFUSE_BASE + 0x0d4)
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#define EFUSE_EFUSE_BLK2_DIN7 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK2_DIN7_S 0
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#define EFUSE_BLK3_WDATA0 (DR_REG_EFUSE_BASE + 0x0d8)
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#define EFUSE_EFUSE_BLK3_DIN0 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DIN0_S 0
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#define EFUSE_BLK3_WDATA1 (DR_REG_EFUSE_BASE + 0x0dc)
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#define EFUSE_EFUSE_BLK3_DIN1 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DIN1_S 0
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#define EFUSE_BLK3_WDATA2 (DR_REG_EFUSE_BASE + 0x0e0)
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#define EFUSE_EFUSE_BLK3_DIN2 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DIN2_S 0
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#define EFUSE_BLK3_WDATA3 (DR_REG_EFUSE_BASE + 0x0e4)
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#define EFUSE_EFUSE_BLK3_DIN3 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DIN3_S 0
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#define EFUSE_BLK3_WDATA4 (DR_REG_EFUSE_BASE + 0x0e8)
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#define EFUSE_EFUSE_BLK3_DIN4 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DIN4_S 0
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#define EFUSE_BLK3_WDATA5 (DR_REG_EFUSE_BASE + 0x0ec)
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#define EFUSE_EFUSE_BLK3_DIN5 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DIN5_S 0
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#define EFUSE_BLK3_WDATA6 (DR_REG_EFUSE_BASE + 0x0f0)
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#define EFUSE_EFUSE_BLK3_DIN6 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DIN6_S 0
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#define EFUSE_BLK3_WDATA7 (DR_REG_EFUSE_BASE + 0x0f4)
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#define EFUSE_EFUSE_BLK3_DIN7 0xFFFFFFFF
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#define EFUSE_EFUSE_BLK3_DIN7_S 0
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#define EFUSE_CLK (DR_REG_EFUSE_BASE + 0x0f8)
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#define EFUSE_CLK_EN (BIT(16))
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#define EFUSE_CLK_EN_S 16
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#define EFUSE_EFUSE_CLK_SEL1 0x000000FF
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#define EFUSE_EFUSE_CLK_SEL1_S 8
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#define EFUSE_EFUSE_CLK_SEL0 0x000000FF
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#define EFUSE_EFUSE_CLK_SEL0_S 0
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#define EFUSE_CONF (DR_REG_EFUSE_BASE + 0x0fc)
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#define EFUSE_EFUSE_FORCE_NO_WR_RD_DIS (BIT(16))
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#define EFUSE_EFUSE_FORCE_NO_WR_RD_DIS_S 16
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#define EFUSE_EFUSE_OP_CODE 0x0000FFFF
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#define EFUSE_EFUSE_OP_CODE_S 0
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#define EFUSE_STATUS (DR_REG_EFUSE_BASE + 0x100)
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#define EFUSE_EFUSE_DEBUG 0xFFFFFFFF
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#define EFUSE_EFUSE_DEBUG_S 0
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#define EFUSE_CMD (DR_REG_EFUSE_BASE + 0x104)
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#define EFUSE_EFUSE_PGM_CMD (BIT(1))
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#define EFUSE_EFUSE_PGM_CMD_S 1
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#define EFUSE_EFUSE_READ_CMD (BIT(0))
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#define EFUSE_EFUSE_READ_CMD_S 0
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#define EFUSE_INT_RAW (DR_REG_EFUSE_BASE + 0x108)
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#define EFUSE_EFUSE_PGM_DONE_INT_RAW (BIT(1))
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#define EFUSE_EFUSE_PGM_DONE_INT_RAW_S 1
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#define EFUSE_EFUSE_READ_DONE_INT_RAW (BIT(0))
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#define EFUSE_EFUSE_READ_DONE_INT_RAW_S 0
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#define EFUSE_INT_ST (DR_REG_EFUSE_BASE + 0x10c)
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#define EFUSE_EFUSE_PGM_DONE_INT_ST (BIT(1))
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#define EFUSE_EFUSE_PGM_DONE_INT_ST_S 1
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#define EFUSE_EFUSE_READ_DONE_INT_ST (BIT(0))
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#define EFUSE_EFUSE_READ_DONE_INT_ST_S 0
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#define EFUSE_INT_ENA (DR_REG_EFUSE_BASE + 0x110)
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#define EFUSE_EFUSE_PGM_DONE_INT_ENA (BIT(1))
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#define EFUSE_EFUSE_PGM_DONE_INT_ENA_S 1
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#define EFUSE_EFUSE_READ_DONE_INT_ENA (BIT(0))
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#define EFUSE_EFUSE_READ_DONE_INT_ENA_S 0
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#define EFUSE_INT_CLR (DR_REG_EFUSE_BASE + 0x114)
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#define EFUSE_EFUSE_PGM_DONE_INT_CLR (BIT(1))
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#define EFUSE_EFUSE_PGM_DONE_INT_CLR_S 1
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#define EFUSE_EFUSE_READ_DONE_INT_CLR (BIT(0))
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#define EFUSE_EFUSE_READ_DONE_INT_CLR_S 0
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#define EFUSE_DAC_CONF (DR_REG_EFUSE_BASE + 0x118)
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#define EFUSE_EFUSE_DAC_CLK_PAD_SEL (BIT(8))
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#define EFUSE_EFUSE_DAC_CLK_PAD_SEL_S 8
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#define EFUSE_EFUSE_DAC_CLK_DIV 0x000000FF
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#define EFUSE_EFUSE_DAC_CLK_DIV_S 0
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#define EFUSE_DEC_STATUS (DR_REG_EFUSE_BASE + 0x11c)
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#define EFUSE_EFUSE_DEC_WARNINGS 0x00000FFF
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#define EFUSE_EFUSE_DEC_WARNINGS_S 0
|
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#define EFUSE_DATE (DR_REG_EFUSE_BASE + 0x1FC)
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#define EFUSE_EFUSE_DATE 0xFFFFFFFF
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#define EFUSE_EFUSE_DATE_S 0
|
||
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#define EFUSE_EFUSE_DATE_VERSION 0x16042600
|
||
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#endif /* _SOC_EFUSE_REG_H_ */
|