2019-04-04 08:06:22 +00:00
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Descriptions have been adapted from the comments in xt_perf_const.h,
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// licensed under MIT license and copyright by Tensilica Inc.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "xtensa_perfmon_masks.h"
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const xtensa_perfmon_select_t xtensa_perfmon_select_table[] = {
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// select, description
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{XTPERF_CNT_CYCLES, "Counts cycles"},
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{XTPERF_CNT_OVERFLOW, "Overflow of counter"},
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{XTPERF_CNT_INSN, "Successfully Retired Instructions"},
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{XTPERF_CNT_D_STALL, "Data-related GlobalStall cycles"},
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{XTPERF_CNT_I_STALL, "Instruction-related and Other GlobalStall cycles"},
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{XTPERF_CNT_EXR, "Exceptions and Pipeline Replays"},
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{XTPERF_CNT_BUBBLES, "Hold and Other Bubble cycles"},
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{XTPERF_CNT_I_TLB, "Instruction TLB Accesses (per instruction retiring)"},
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{XTPERF_CNT_I_MEM, "Instruction Memory Accesses (per instruction retiring)"},
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{XTPERF_CNT_D_TLB, "Data TLB Accesses"},
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{XTPERF_CNT_D_LOAD_U1, "Load Instruction (Data Memory)"},
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{XTPERF_CNT_D_LOAD_U2, "Load Instruction (Data Memory)"},
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{XTPERF_CNT_D_LOAD_U3, "Load Instruction (Data Memory)"},
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{XTPERF_CNT_D_STORE_U1, "Store Instruction (Data Memory)"},
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{XTPERF_CNT_D_STORE_U2, "Store Instruction (Data Memory)"},
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{XTPERF_CNT_D_STORE_U3, "Store Instruction (Data Memory)"},
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{XTPERF_CNT_D_ACCESS_U1, "Accesses to Data Memory (Load, Store, S32C1I, ...)"},
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{XTPERF_CNT_D_ACCESS_U2, "Accesses to Data Memory (Load, Store, S32C1I, ...)"},
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{XTPERF_CNT_D_ACCESS_U3, "Accesses to Data Memory (Load, Store, S32C1I, ...)"},
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{XTPERF_CNT_MULTIPLE_LS, "Multiple Load/Store"},
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{XTPERF_CNT_OUTBOUND_PIF, "Outbound PIF"},
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{XTPERF_CNT_INBOUND_PIF, "Inbound PIF"},
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{XTPERF_CNT_PREFETCH, "Prefetch"},
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2019-11-28 13:07:47 +00:00
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#if XCHAL_HW_VERSION >= 270004
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2019-04-04 08:06:22 +00:00
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{XTPERF_CNT_IDMA, "iDMA"},
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{XTPERF_CNT_INSN_LENGTH, "Length of Instructions"},
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2019-11-28 13:07:47 +00:00
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#endif
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2019-04-04 08:06:22 +00:00
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{-1, ""},
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};
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const xtensa_perfmon_masks_t xtensa_perfmon_masks_table[] = {
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// select, mask, description
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{XTPERF_CNT_CYCLES, 1, "Amount of cycles"},
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{XTPERF_CNT_OVERFLOW, 1, "Overflow counter"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_JX, "JX instructions"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_CALLX, "CALLXn instructions"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_RET, "return instructions (RET, RETW, ...)"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_RF, "supervisor return instructions (RFDE, RFE, RFI, RFWO, RFWU)"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_TAKEN, "Conditional branch instructions where execution"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_TAKEN, "transfers to the target (aka. taken branch),"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_TAKEN, " or loopgtz/loopnez instr where execution skips"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_TAKEN, " the loop (aka. not-taken loop)"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_J, "J instr"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_CALL, "CALLn instr"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_NOT_TAKEN, "Conditional branch instr where execution"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_NOT_TAKEN, " falls through (aka. not-taken branch)"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_TAKEN, "Loop instr where execution falls into loop (aka. taken loop)"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_BEG, "Last inst of loop and execution transfers"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_BEG, " to LBEG (aka. loopback taken)"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_END, "Last inst of loop and execution falls "},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_END, " through to LEND (aka. loopback fallthrough)"},
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{XTPERF_CNT_INSN, XTPERF_MASK_INSN_NON_BRANCH, "Non-branch instr (aka. non-CTI)"},
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{XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_STORE_BUF_FULL, "Store buffer full stall"},
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{XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT, "Store buffer conflict stall"},
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{XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_CACHE_MISS, "Data Cache-miss stall (unused)"},
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{XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_BUSY, "Data RAM/ROM/XLMI busy stall"},
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{XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_IN_PIF, "Data inbound-PIF request stall (includes s32c1i)"},
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{XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_MHT_LOOKUP, "MHT lookup stall"},
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{XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_UNCACHED_LOAD, "Uncached load stall (included in MHT lookup stall below)"},
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{XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_BANK_CONFLICT, "Bank-conflict stall"},
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{XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_CACHE_MISS, "ICache-miss stall"},
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{XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_BUSY, "Instruction RAM/ROM busy stall"},
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{XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_IN_PIF, "Instruction RAM inbound-PIF request stall"},
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{XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_TIE_PORT, "TIE port stall"},
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{XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL, "External RunStall signal status"},
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{XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_UNCACHED_FETCH, "Uncached fetch stall"},
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{XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_FAST_L32R, "FastL32R stall"},
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{XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_ITERATIVE_MUL, "Iterative multiply stall"},
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{XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_ITERATIVE_DIV, "Iterative divide stall"},
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{XTPERF_CNT_EXR, XTPERF_MASK_EXR_REPLAYS, "Other Pipeline Replay (i.e. excludes cache miss etc.)"},
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{XTPERF_CNT_EXR, XTPERF_MASK_EXR_LEVEL1_INT, "Level-1 interrupt"},
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{XTPERF_CNT_EXR, XTPERF_MASK_EXR_LEVELH_INT, "Greater-than-level-1 interrupt"},
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{XTPERF_CNT_EXR, XTPERF_MASK_EXR_DEBUG, "Debug exception"},
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{XTPERF_CNT_EXR, XTPERF_MASK_EXR_NMI, "NMI"},
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{XTPERF_CNT_EXR, XTPERF_MASK_EXR_WINDOW, "Window exception"},
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{XTPERF_CNT_EXR, XTPERF_MASK_EXR_ALLOCA, "Allocate exception"},
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{XTPERF_CNT_EXR, XTPERF_MASK_EXR_OTHER, "Other exceptions"},
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{XTPERF_CNT_EXR, XTPERF_MASK_EXR_MEM_ERR, "HW-corrected memory error"},
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{XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_PSO, "Processor domain PSO bubble"},
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{XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS, "R hold caused by Data Cache miss(unused)"},
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{XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE, "R hold caused by Store release"},
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{XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP, "R hold caused by register dependency"},
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{XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_WAIT, "R hold caused by MEMW, EXTW or EXCW"},
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{XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_HALT, "R hold caused by Halt instruction (TX only)"},
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{XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_CTI, "CTI bubble (e.g. branch delay slot)"},
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{XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_WAITI, "WAITI bubble i.e. a cycle spent in WaitI power down mode."},
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{XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_HITS, "ITLB Hit"},
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{XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_REPLAYS, "Replay of instruction due to ITLB miss"},
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{XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_REFILLS, "HW-assisted TLB Refill completes"},
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{XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_MISSES, "ITLB Miss Exception"},
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{XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_CACHE_HITS, "Instruction Cache Hit"},
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{XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_CACHE_MISSES, "Instruction Cache Miss"},
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{XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_IRAM, "All InstRAM or InstROM accesses"},
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{XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_BYPASS, "Bypass (i.e. uncached) fetch"},
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{XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_HITS, "DTLB Hit"},
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{XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_REPLAYS, "Replay of load/store due to DTLB miss"},
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{XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_REFILLS, "HW-assisted TLB Refill completes"},
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{XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_MISSES, "DTLB Miss Exception"},
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{XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_CACHE_HITS, "Data Cache Hit(unused)"},
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{XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_CACHE_MISSES, "Data Cache Miss(unused)"},
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{XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_LOCAL_MEM, "Load from local memory i.e. DataRAM, DataROM, InstRAM, InstROM"},
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{XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_BYPASS, "Bypass (i.e. uncached) load"},
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{XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_CACHE_HITS, "Data Cache Hit(unused)"},
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{XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_CACHE_MISSES, "Data Cache Miss(unused)"},
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{XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_LOCAL_MEM, "Load from local memory i.e. DataRAM, DataROM, InstRAM, InstROM"},
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{XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_BYPASS, "Bypass (i.e. uncached) load"},
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{XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_CACHE_HITS, "Data Cache Hit (unused)"},
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{XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_CACHE_MISSES, "Data Cache Miss (unused)"},
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{XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_LOCAL_MEM, "Load from local memory i.e. DataRAM, DataROM, InstRAM, InstROM"},
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{XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_BYPASS, "Bypass (i.e. uncached) load"},
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{XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_CACHE_HITS, "Data Cache Hit (unused)"},
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{XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_CACHE_MISSES, "Data Cache Miss (unused)"},
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{XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_LOCAL_MEM, "Store to local memory i.e. DataRAM, InstRAM"},
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{XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_PIF, "PIF Store"},
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{XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_CACHE_HITS, "Data Cache Hit(unused)"},
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{XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_CACHE_MISSES, "Data Cache Miss(unused)"},
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{XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_LOCAL_MEM, "Store to local memory i.e. DataRAM, InstRAM"},
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{XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_PIF, "PIF Store"},
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{XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_CACHE_HITS, "Data Cache Hit (unused)"},
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{XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_CACHE_MISSES, "Data Cache Miss (unused)"},
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{XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_LOCAL_MEM, "Store to local memory i.e. DataRAM, InstRAM"},
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{XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_PIF, "PIF Store"},
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{XTPERF_CNT_D_ACCESS_U1, XTPERF_MASK_D_ACCESS_CACHE_MISSES, "Cache Miss"},
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{XTPERF_CNT_D_ACCESS_U2, XTPERF_MASK_D_ACCESS_CACHE_MISSES, "Cache Miss"},
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{XTPERF_CNT_D_ACCESS_U3, XTPERF_MASK_D_ACCESS_CACHE_MISSES, "Cache Miss"},
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{XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_0L, "0 stores and 0 loads"},
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{XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_1L, "0 stores and 1 loads"},
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{XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_1S_0L, "1 stores and 0 loads"},
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{XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_1S_1L, "1 stores and 1 loads"},
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{XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_2L, "0 stores and 2 loads"},
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{XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_2S_0L, "2 stores and 0 loads"},
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{XTPERF_CNT_OUTBOUND_PIF, XTPERF_MASK_OUTBOUND_PIF_CASTOUT, "Castout"},
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{XTPERF_CNT_OUTBOUND_PIF, XTPERF_MASK_OUTBOUND_PIF_PREFETCH, "Prefetch"},
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{XTPERF_CNT_INBOUND_PIF, XTPERF_MASK_INBOUND_PIF_I_DMA, "Data DMA"},
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{XTPERF_CNT_INBOUND_PIF, XTPERF_MASK_INBOUND_PIF_D_DMA, "Instruction DMA"},
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{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_HIT, "I prefetch-buffer-lookup hit"},
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{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_HIT, "D prefetch-buffer-lookup hit"},
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{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_MISS, "I prefetch-buffer-lookup miss"},
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{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_MISS, "D prefetch-buffer-lookup miss"},
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{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_L1_FILL, "Direct fill to (L1) Data Cache (unused)"},
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2019-11-28 13:07:47 +00:00
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#if XCHAL_HW_VERSION >= 270004
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2019-04-04 08:06:22 +00:00
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{XTPERF_CNT_IDMA, XTPERF_MASK_IDMA_ACTIVE_CYCLES, "active cycles"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_16, "16-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_24, "24-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_32, "32-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_40, "40-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_48, "48-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_56, "56-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_64, "64-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_72, "72-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_80, "80-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_88, "88-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_96, "96-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_104, "104-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_112, "112-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_120, "120-bit"},
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{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_128, "128-bit"},
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2019-11-28 13:07:47 +00:00
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#endif
|
2019-04-04 08:06:22 +00:00
|
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{-1, 0, ""},
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};
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// All availible combinations
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const uint32_t xtensa_perfmon_select_mask_all[MAX_PERFMON_EVENTS * 2] = {
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XTPERF_CNT_CYCLES, XTPERF_MASK_CYCLES,
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XTPERF_CNT_OVERFLOW, XTPERF_MASK_OVERFLOW,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_JX,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_CALLX,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_RET,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_RF,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_TAKEN,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_J,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_CALL,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_NOT_TAKEN,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_TAKEN,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_BEG,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_END,
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_NON_BRANCH,
|
2019-09-03 03:49:58 +00:00
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XTPERF_CNT_INSN, XTPERF_MASK_INSN_ALL,
|
2019-04-04 08:06:22 +00:00
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XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_STORE_BUF_FULL,
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XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT,
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XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_CACHE_MISS,
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XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_BUSY,
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XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_IN_PIF,
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XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_MHT_LOOKUP,
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XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_UNCACHED_LOAD,
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XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_BANK_CONFLICT,
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XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_CACHE_MISS,
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XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_BUSY,
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XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_IN_PIF,
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XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_TIE_PORT,
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XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL,
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XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_UNCACHED_FETCH,
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XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_FAST_L32R,
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XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_ITERATIVE_MUL,
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XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_ITERATIVE_DIV,
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XTPERF_CNT_EXR, XTPERF_MASK_EXR_REPLAYS,
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XTPERF_CNT_EXR, XTPERF_MASK_EXR_LEVEL1_INT,
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XTPERF_CNT_EXR, XTPERF_MASK_EXR_LEVELH_INT,
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XTPERF_CNT_EXR, XTPERF_MASK_EXR_DEBUG,
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XTPERF_CNT_EXR, XTPERF_MASK_EXR_NMI,
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XTPERF_CNT_EXR, XTPERF_MASK_EXR_WINDOW,
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XTPERF_CNT_EXR, XTPERF_MASK_EXR_ALLOCA,
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XTPERF_CNT_EXR, XTPERF_MASK_EXR_OTHER,
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XTPERF_CNT_EXR, XTPERF_MASK_EXR_MEM_ERR,
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XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_PSO,
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XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS,
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XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE,
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XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP,
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XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_WAIT,
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XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_HALT,
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XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_CTI,
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XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_WAITI,
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XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_HITS,
|
|
|
|
|
XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_REPLAYS,
|
|
|
|
|
XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_REFILLS,
|
|
|
|
|
XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_MISSES,
|
|
|
|
|
XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_CACHE_HITS,
|
|
|
|
|
XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_CACHE_MISSES,
|
|
|
|
|
XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_IRAM,
|
|
|
|
|
XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_BYPASS,
|
|
|
|
|
XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_HITS,
|
|
|
|
|
XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_REPLAYS,
|
|
|
|
|
XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_REFILLS,
|
|
|
|
|
XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_MISSES,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_CACHE_HITS,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_CACHE_MISSES,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_LOCAL_MEM,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_BYPASS,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_CACHE_HITS,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_CACHE_MISSES,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_LOCAL_MEM,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_BYPASS,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_CACHE_HITS,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_CACHE_MISSES,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_LOCAL_MEM,
|
|
|
|
|
XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_BYPASS,
|
|
|
|
|
XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_CACHE_HITS,
|
|
|
|
|
XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_CACHE_MISSES,
|
|
|
|
|
XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_LOCAL_MEM,
|
|
|
|
|
XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_PIF,
|
|
|
|
|
XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_CACHE_HITS,
|
|
|
|
|
XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_CACHE_MISSES,
|
|
|
|
|
XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_LOCAL_MEM,
|
|
|
|
|
XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_PIF,
|
|
|
|
|
XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_CACHE_HITS,
|
|
|
|
|
XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_CACHE_MISSES,
|
|
|
|
|
XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_LOCAL_MEM,
|
|
|
|
|
XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_PIF,
|
|
|
|
|
XTPERF_CNT_D_ACCESS_U1, XTPERF_MASK_D_ACCESS_CACHE_MISSES,
|
|
|
|
|
XTPERF_CNT_D_ACCESS_U2, XTPERF_MASK_D_ACCESS_CACHE_MISSES,
|
|
|
|
|
XTPERF_CNT_D_ACCESS_U3, XTPERF_MASK_D_ACCESS_CACHE_MISSES,
|
|
|
|
|
XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_0L,
|
|
|
|
|
XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_1L,
|
|
|
|
|
XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_1S_0L,
|
|
|
|
|
XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_1S_1L,
|
|
|
|
|
XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_2L,
|
|
|
|
|
XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_2S_0L,
|
|
|
|
|
XTPERF_CNT_OUTBOUND_PIF, XTPERF_MASK_OUTBOUND_PIF_CASTOUT,
|
|
|
|
|
XTPERF_CNT_OUTBOUND_PIF, XTPERF_MASK_OUTBOUND_PIF_PREFETCH,
|
|
|
|
|
XTPERF_CNT_INBOUND_PIF, XTPERF_MASK_INBOUND_PIF_I_DMA,
|
|
|
|
|
XTPERF_CNT_INBOUND_PIF, XTPERF_MASK_INBOUND_PIF_D_DMA,
|
|
|
|
|
XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_HIT,
|
|
|
|
|
XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_HIT,
|
|
|
|
|
XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_MISS,
|
|
|
|
|
XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_MISS,
|
|
|
|
|
XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_L1_FILL,
|
2019-11-28 13:07:47 +00:00
|
|
|
#if XCHAL_HW_VERSION >= 270004
|
2019-04-04 08:06:22 +00:00
|
|
|
XTPERF_CNT_IDMA, XTPERF_MASK_IDMA_ALL,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_16,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_24,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_32,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_40,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_48,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_56,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_64,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_72,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_80,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_88,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_96,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_104,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_112,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_120,
|
|
|
|
|
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_128
|
2019-11-28 13:07:47 +00:00
|
|
|
#endif
|
2019-04-04 08:06:22 +00:00
|
|
|
};
|
