411 lines
12 KiB
C
411 lines
12 KiB
C
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use in application code.
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* See readme.md in soc/include/hal/readme.md
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******************************************************************************/
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// The LL layer for ESP32 GPIO register operations
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#pragma once
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#include "soc/soc.h"
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#include "soc/gpio_periph.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/rtc_io_reg.h"
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#include "hal/gpio_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Get GPIO hardware instance with giving gpio num
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#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
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/**
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* @brief Enable pull-up on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
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}
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/**
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* @brief Disable pull-up on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
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}
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/**
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* @brief Enable pull-down on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
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}
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/**
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* @brief Disable pull-down on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
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}
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/**
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* @brief GPIO set interrupt trigger type
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16);
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* @param intr_type Interrupt type, select from gpio_int_type_t
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*/
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static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
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{
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hw->pin[gpio_num].int_type = intr_type;
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}
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/**
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* @brief Get GPIO interrupt status
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param core_id interrupt core id
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* @param status interrupt status
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*/
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static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
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{
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*status = (core_id == 0) ? hw->pcpu_int : hw->acpu_int;
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}
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/**
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* @brief Get GPIO interrupt status high
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param core_id interrupt core id
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* @param status interrupt status high
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*/
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static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
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{
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*status = (core_id == 0) ? hw->pcpu_int1.intr : hw->acpu_int1.intr;
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}
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/**
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* @brief Clear GPIO interrupt status
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param mask interrupt status clear mask
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*/
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static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
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{
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hw->status_w1tc = mask;
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}
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/**
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* @brief Clear GPIO interrupt status high
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param mask interrupt status high clear mask
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*/
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static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
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{
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hw->status1_w1tc.intr_st = mask;
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}
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/**
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* @brief Enable GPIO module interrupt signal
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param core_id Interrupt enabled CPU to corresponding ID
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* @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
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*/
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static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
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{
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if (core_id == 0) {
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hw->pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr
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} else {
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hw->pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr
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}
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}
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/**
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* @brief Disable GPIO module interrupt signal
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
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*/
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static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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hw->pin[gpio_num].int_ena = 0; //disable GPIO intr
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}
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/**
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* @brief Disable input mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
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}
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/**
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* @brief Enable input mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
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}
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/**
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* @brief Disable output mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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if (gpio_num < 32) {
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hw->enable_w1tc = (0x1 << gpio_num);
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} else {
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hw->enable1_w1tc.data = (0x1 << (gpio_num - 32));
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}
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// Ensure no other output signal is routed via GPIO matrix to this pin
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REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4),
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SIG_GPIO_OUT_IDX);
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}
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/**
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* @brief Enable output mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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if (gpio_num < 32) {
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hw->enable_w1ts = (0x1 << gpio_num);
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} else {
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hw->enable1_w1ts.data = (0x1 << (gpio_num - 32));
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}
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}
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/**
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* @brief Disable open-drain mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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hw->pin[gpio_num].pad_driver = 0;
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}
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/**
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* @brief Enable open-drain mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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hw->pin[gpio_num].pad_driver = 1;
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}
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/**
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* @brief GPIO set output level
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
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* @param level Output level. 0: low ; 1: high
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*/
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static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level)
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{
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if (level) {
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if (gpio_num < 32) {
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hw->out_w1ts = (1 << gpio_num);
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} else {
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hw->out1_w1ts.data = (1 << (gpio_num - 32));
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}
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} else {
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if (gpio_num < 32) {
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hw->out_w1tc = (1 << gpio_num);
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} else {
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hw->out1_w1tc.data = (1 << (gpio_num - 32));
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}
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}
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}
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/**
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* @brief GPIO get input level
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*
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* @warning If the pad is not configured for input (or input and output) the returned value is always 0.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
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*
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* @return
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* - 0 the GPIO input level is 0
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* - 1 the GPIO input level is 1
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*/
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static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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if (gpio_num < 32) {
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return (hw->in >> gpio_num) & 0x1;
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} else {
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return (hw->in1.data >> (gpio_num - 32)) & 0x1;
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}
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}
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/**
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* @brief Enable GPIO wake-up function.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number.
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* @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
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*/
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static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
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{
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hw->pin[gpio_num].int_type = intr_type;
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hw->pin[gpio_num].wakeup_enable = 0x1;
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}
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/**
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* @brief Disable GPIO wake-up function.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
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{
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hw->pin[gpio_num].wakeup_enable = 0;
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}
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/**
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* @brief Set GPIO pad drive capability
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number, only support output GPIOs
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* @param strength Drive capability of the pad
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*/
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static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength)
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{
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SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);
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}
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/**
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* @brief Get GPIO pad drive capability
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number, only support output GPIOs
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* @param strength Pointer to accept drive capability of the pad
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*/
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static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
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{
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*strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
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}
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/**
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* @brief Enable all digital gpio pad hold function during Deep-sleep.
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*
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* @param hw Peripheral GPIO hardware instance address.
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*/
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static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
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{
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SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
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}
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/**
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* @brief Disable all digital gpio pad hold function during Deep-sleep.
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*
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* @param hw Peripheral GPIO hardware instance address.
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*/
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static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
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{
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
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}
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/**
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* @brief Enable gpio pad hold function.
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*
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||
|
|
* @param hw Peripheral GPIO hardware instance address.
|
||
|
|
* @param gpio_num GPIO number, only support output GPIOs
|
||
|
|
*/
|
||
|
|
static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num)
|
||
|
|
{
|
||
|
|
SET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable gpio pad hold function.
|
||
|
|
*
|
||
|
|
* @param hw Peripheral GPIO hardware instance address.
|
||
|
|
* @param gpio_num GPIO number, only support output GPIOs
|
||
|
|
*/
|
||
|
|
static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
|
||
|
|
{
|
||
|
|
CLEAR_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set pad input to a peripheral signal through the IOMUX.
|
||
|
|
*
|
||
|
|
* @param hw Peripheral GPIO hardware instance address.
|
||
|
|
* @param gpio_num GPIO number of the pad.
|
||
|
|
* @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``.
|
||
|
|
*/
|
||
|
|
static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
|
||
|
|
{
|
||
|
|
hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
|
||
|
|
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set peripheral output to an GPIO pad through the IOMUX.
|
||
|
|
*
|
||
|
|
* @param hw Peripheral GPIO hardware instance address.
|
||
|
|
* @param gpio_num gpio_num GPIO number of the pad.
|
||
|
|
* @param func The function number of the peripheral pin to output pin.
|
||
|
|
* One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``.
|
||
|
|
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
|
||
|
|
*/
|
||
|
|
static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
|
||
|
|
{
|
||
|
|
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
|
||
|
|
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
|
||
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func);
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|