2016-12-19 14:19:47 +00:00
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SDMMC_REG_H_
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#define _SOC_SDMMC_REG_H_
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#include "soc.h"
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#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00)
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#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04)
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#define SDMMC_CLKDIV_REG (DR_REG_SDMMC_BASE + 0x08)
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#define SDMMC_CLKSRC_REG (DR_REG_SDMMC_BASE + 0x0c)
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#define SDMMC_CLKENA_REG (DR_REG_SDMMC_BASE + 0x10)
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#define SDMMC_TMOUT_REG (DR_REG_SDMMC_BASE + 0x14)
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#define SDMMC_CTYPE_REG (DR_REG_SDMMC_BASE + 0x18)
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#define SDMMC_BLKSIZ_REG (DR_REG_SDMMC_BASE + 0x1c)
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#define SDMMC_BYTCNT_REG (DR_REG_SDMMC_BASE + 0x20)
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#define SDMMC_INTMASK_REG (DR_REG_SDMMC_BASE + 0x24)
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#define SDMMC_CMDARG_REG (DR_REG_SDMMC_BASE + 0x28)
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#define SDMMC_CMD_REG (DR_REG_SDMMC_BASE + 0x2c)
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#define SDMMC_RESP0_REG (DR_REG_SDMMC_BASE + 0x30)
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#define SDMMC_RESP1_REG (DR_REG_SDMMC_BASE + 0x34)
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#define SDMMC_RESP2_REG (DR_REG_SDMMC_BASE + 0x38)
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#define SDMMC_RESP3_REG (DR_REG_SDMMC_BASE + 0x3c)
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#define SDMMC_MINTSTS_REG (DR_REG_SDMMC_BASE + 0x40)
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#define SDMMC_RINTSTS_REG (DR_REG_SDMMC_BASE + 0x44)
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#define SDMMC_STATUS_REG (DR_REG_SDMMC_BASE + 0x48)
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#define SDMMC_FIFOTH_REG (DR_REG_SDMMC_BASE + 0x4c)
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#define SDMMC_CDETECT_REG (DR_REG_SDMMC_BASE + 0x50)
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#define SDMMC_WRTPRT_REG (DR_REG_SDMMC_BASE + 0x54)
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#define SDMMC_GPIO_REG (DR_REG_SDMMC_BASE + 0x58)
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#define SDMMC_TCBCNT_REG (DR_REG_SDMMC_BASE + 0x5c)
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#define SDMMC_TBBCNT_REG (DR_REG_SDMMC_BASE + 0x60)
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#define SDMMC_DEBNCE_REG (DR_REG_SDMMC_BASE + 0x64)
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#define SDMMC_USRID_REG (DR_REG_SDMMC_BASE + 0x68)
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#define SDMMC_VERID_REG (DR_REG_SDMMC_BASE + 0x6c)
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#define SDMMC_HCON_REG (DR_REG_SDMMC_BASE + 0x70)
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#define SDMMC_UHS_REG_REG (DR_REG_SDMMC_BASE + 0x74)
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#define SDMMC_RST_N_REG (DR_REG_SDMMC_BASE + 0x78)
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#define SDMMC_BMOD_REG (DR_REG_SDMMC_BASE + 0x80)
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#define SDMMC_PLDMND_REG (DR_REG_SDMMC_BASE + 0x84)
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#define SDMMC_DBADDR_REG (DR_REG_SDMMC_BASE + 0x88)
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#define SDMMC_DBADDRU_REG (DR_REG_SDMMC_BASE + 0x8c)
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#define SDMMC_IDSTS_REG (DR_REG_SDMMC_BASE + 0x8c)
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#define SDMMC_IDINTEN_REG (DR_REG_SDMMC_BASE + 0x90)
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#define SDMMC_DSCADDR_REG (DR_REG_SDMMC_BASE + 0x94)
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#define SDMMC_DSCADDRL_REG (DR_REG_SDMMC_BASE + 0x98)
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#define SDMMC_DSCADDRU_REG (DR_REG_SDMMC_BASE + 0x9c)
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#define SDMMC_BUFADDRL_REG (DR_REG_SDMMC_BASE + 0xa0)
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#define SDMMC_BUFADDRU_REG (DR_REG_SDMMC_BASE + 0xa4)
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#define SDMMC_CARDTHRCTL_REG (DR_REG_SDMMC_BASE + 0x100)
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#define SDMMC_BACK_END_POWER_REG (DR_REG_SDMMC_BASE + 0x104)
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#define SDMMC_UHS_REG_EXT_REG (DR_REG_SDMMC_BASE + 0x108)
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#define SDMMC_EMMC_DDR_REG_REG (DR_REG_SDMMC_BASE + 0x10c)
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#define SDMMC_ENABLE_SHIFT_REG (DR_REG_SDMMC_BASE + 0x110)
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#define SDMMC_CLOCK_REG (DR_REG_SDMMC_BASE + 0x800)
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2018-03-06 09:57:52 +00:00
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#define SDMMC_INTMASK_IO_SLOT1 BIT(17)
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#define SDMMC_INTMASK_IO_SLOT0 BIT(16)
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2016-12-19 14:19:47 +00:00
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#define SDMMC_INTMASK_EBE BIT(15)
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#define SDMMC_INTMASK_ACD BIT(14)
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#define SDMMC_INTMASK_SBE BIT(13)
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#define SDMMC_INTMASK_HLE BIT(12)
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#define SDMMC_INTMASK_FRUN BIT(11)
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#define SDMMC_INTMASK_HTO BIT(10)
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#define SDMMC_INTMASK_DTO BIT(9)
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#define SDMMC_INTMASK_RTO BIT(8)
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#define SDMMC_INTMASK_DCRC BIT(7)
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#define SDMMC_INTMASK_RCRC BIT(6)
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#define SDMMC_INTMASK_RXDR BIT(5)
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#define SDMMC_INTMASK_TXDR BIT(4)
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#define SDMMC_INTMASK_DATA_OVER BIT(3)
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#define SDMMC_INTMASK_CMD_DONE BIT(2)
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#define SDMMC_INTMASK_RESP_ERR BIT(1)
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#define SDMMC_INTMASK_CD BIT(0)
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#define SDMMC_IDMAC_INTMASK_AI BIT(9)
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#define SDMMC_IDMAC_INTMASK_NI BIT(8)
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#define SDMMC_IDMAC_INTMASK_CES BIT(5)
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#define SDMMC_IDMAC_INTMASK_DU BIT(4)
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#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
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#define SDMMC_IDMAC_INTMASK_RI BIT(1)
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#define SDMMC_IDMAC_INTMASK_TI BIT(0)
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#endif /* _SOC_SDMMC_REG_H_ */
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