2018-07-04 23:01:03 +00:00
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <sys/param.h>
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#include "esp_log.h"
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#include "esp_heap_caps.h"
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#include "driver/gpio.h"
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#include "driver/sdmmc_defs.h"
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#include "driver/sdspi_host.h"
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#include "sdspi_private.h"
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#include "sdspi_crc.h"
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#include "esp_timer.h"
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2019-06-25 05:36:24 +00:00
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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2018-07-04 23:01:03 +00:00
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/// Max number of transactions in flight (used in start_command_write_blocks)
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#define SDSPI_TRANSACTION_COUNT 4
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#define SDSPI_MOSI_IDLE_VAL 0xff //!< Data value which causes MOSI to stay high
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#define GPIO_UNUSED 0xff //!< Flag indicating that CD/WP is unused
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/// Size of the buffer returned by get_block_buf
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#define SDSPI_BLOCK_BUF_SIZE (SDSPI_MAX_DATA_LEN + 4)
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/// Maximum number of dummy bytes between the request and response (minimum is 1)
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#define SDSPI_RESPONSE_MAX_DELAY 8
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/// Structure containing run time configuration for a single SD slot
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typedef struct {
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spi_device_handle_t handle; //!< SPI device handle, used for transactions
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uint8_t gpio_cs; //!< CS GPIO
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uint8_t gpio_cd; //!< Card detect GPIO, or GPIO_UNUSED
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uint8_t gpio_wp; //!< Write protect GPIO, or GPIO_UNUSED
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2018-12-28 18:04:37 +00:00
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uint8_t gpio_int; //!< Write protect GPIO, or GPIO_UNUSED
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2018-07-04 23:01:03 +00:00
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/// Set to 1 if the higher layer has asked the card to enable CRC checks
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uint8_t data_crc_enabled : 1;
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/// Number of transactions in 'transactions' array which are in use
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uint8_t used_transaction_count: 3;
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/// Intermediate buffer used when application buffer is not in DMA memory;
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/// allocated on demand, SDSPI_BLOCK_BUF_SIZE bytes long. May be zero.
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uint8_t* block_buf;
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/// array with SDSPI_TRANSACTION_COUNT transaction structures
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spi_transaction_t* transactions;
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2018-12-28 18:04:37 +00:00
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/// semaphore of gpio interrupt
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SemaphoreHandle_t semphr_int;
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2018-07-04 23:01:03 +00:00
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} slot_info_t;
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static slot_info_t s_slots[3];
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static const char *TAG = "sdspi_host";
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/// Functions to send out different kinds of commands
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static esp_err_t start_command_read_blocks(int slot, sdspi_hw_cmd_t *cmd,
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2018-12-28 18:04:37 +00:00
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uint8_t *data, uint32_t rx_length, bool need_stop_command);
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2018-07-04 23:01:03 +00:00
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static esp_err_t start_command_write_blocks(int slot, sdspi_hw_cmd_t *cmd,
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2018-12-28 18:04:37 +00:00
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const uint8_t *data, uint32_t tx_length, bool multi_block, bool stop_trans);
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2018-07-04 23:01:03 +00:00
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static esp_err_t start_command_default(int slot, int flags, sdspi_hw_cmd_t *cmd);
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2018-12-28 18:04:37 +00:00
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static esp_err_t shift_cmd_response(sdspi_hw_cmd_t *cmd, int sent_bytes);
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2018-07-04 23:01:03 +00:00
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/// A few helper functions
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/// Set CS high for given slot
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static void cs_high(int slot)
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{
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gpio_set_level(s_slots[slot].gpio_cs, 1);
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}
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/// Set CS low for given slot
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static void cs_low(int slot)
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{
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gpio_set_level(s_slots[slot].gpio_cs, 0);
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}
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/// Return true if WP pin is configured and is low
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static bool card_write_protected(int slot)
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{
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if (s_slots[slot].gpio_wp == GPIO_UNUSED) {
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return false;
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}
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return gpio_get_level(s_slots[slot].gpio_wp) == 0;
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}
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/// Return true if CD pin is configured and is high
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static bool card_missing(int slot)
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{
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if (s_slots[slot].gpio_cd == GPIO_UNUSED) {
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return false;
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}
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return gpio_get_level(s_slots[slot].gpio_cd) == 1;
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}
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/// Check if slot number is within bounds
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static bool is_valid_slot(int slot)
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{
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return slot == VSPI_HOST || slot == HSPI_HOST;
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}
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static spi_device_handle_t spi_handle(int slot)
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{
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return s_slots[slot].handle;
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}
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static bool is_slot_initialized(int slot)
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{
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return spi_handle(slot) != NULL;
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}
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static bool data_crc_enabled(int slot)
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{
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return s_slots[slot].data_crc_enabled;
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}
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/// Get pointer to a block of DMA memory, allocate if necessary.
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/// This is used if the application provided buffer is not in DMA capable memory.
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static esp_err_t get_block_buf(int slot, uint8_t** out_buf)
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{
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if (s_slots[slot].block_buf == NULL) {
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s_slots[slot].block_buf = heap_caps_malloc(SDSPI_BLOCK_BUF_SIZE, MALLOC_CAP_DMA);
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if (s_slots[slot].block_buf == NULL) {
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return ESP_ERR_NO_MEM;
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}
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}
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*out_buf = s_slots[slot].block_buf;
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return ESP_OK;
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}
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static spi_transaction_t* get_transaction(int slot)
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{
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size_t used_transaction_count = s_slots[slot].used_transaction_count;
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assert(used_transaction_count < SDSPI_TRANSACTION_COUNT);
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spi_transaction_t* ret = &s_slots[slot].transactions[used_transaction_count];
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++s_slots[slot].used_transaction_count;
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return ret;
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}
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static void release_transaction(int slot)
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{
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--s_slots[slot].used_transaction_count;
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}
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static void wait_for_transactions(int slot)
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{
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size_t used_transaction_count = s_slots[slot].used_transaction_count;
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for (size_t i = 0; i < used_transaction_count; ++i) {
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spi_transaction_t* t_out;
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spi_device_get_trans_result(spi_handle(slot), &t_out, portMAX_DELAY);
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release_transaction(slot);
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}
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}
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/// Clock out one byte (CS has to be high) to make the card release MISO
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/// (clocking one bit would work as well, but that triggers a bug in SPI DMA)
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static void release_bus(int slot)
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{
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spi_transaction_t t = {
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.flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA,
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.length = 8,
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.tx_data = {0xff}
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};
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spi_device_transmit(spi_handle(slot), &t);
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// don't care if this failed
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}
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/// Clock out 80 cycles (10 bytes) before GO_IDLE command
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static void go_idle_clockout(int slot)
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{
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//actually we need 10, declare 12 to meet requirement of RXDMA
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uint8_t data[12];
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memset(data, 0xff, sizeof(data));
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spi_transaction_t t = {
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.length = 10*8,
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.tx_buffer = data,
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.rx_buffer = data,
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};
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spi_device_transmit(spi_handle(slot), &t);
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// don't care if this failed
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}
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/// Return true if the pointer can be used for DMA
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static bool ptr_dma_compatible(const void* ptr)
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{
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return (uintptr_t) ptr >= 0x3FFAE000 &&
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(uintptr_t) ptr < 0x40000000;
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}
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/**
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* Initialize SPI device. Used to change clock speed.
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* @param slot SPI host number
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* @param clock_speed_hz clock speed, Hz
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* @return ESP_OK on success
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*/
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static esp_err_t init_spi_dev(int slot, int clock_speed_hz)
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{
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if (spi_handle(slot)) {
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// Reinitializing
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spi_bus_remove_device(spi_handle(slot));
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s_slots[slot].handle = NULL;
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}
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spi_device_interface_config_t devcfg = {
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.clock_speed_hz = clock_speed_hz,
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.mode = 0,
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// For SD cards, CS must stay low during the whole read/write operation,
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// rather than a single SPI transaction.
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2018-12-28 18:04:37 +00:00
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.spics_io_num = GPIO_NUM_NC,
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2018-07-04 23:01:03 +00:00
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.queue_size = SDSPI_TRANSACTION_COUNT,
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};
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return spi_bus_add_device((spi_host_device_t) slot, &devcfg, &s_slots[slot].handle);
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}
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2019-07-16 09:33:30 +00:00
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esp_err_t sdspi_host_init(void)
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2018-07-04 23:01:03 +00:00
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{
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return ESP_OK;
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}
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2019-07-16 09:33:30 +00:00
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esp_err_t sdspi_host_deinit(void)
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2018-07-04 23:01:03 +00:00
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{
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for (size_t i = 0; i < sizeof(s_slots)/sizeof(s_slots[0]); ++i) {
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if (s_slots[i].handle) {
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spi_bus_remove_device(s_slots[i].handle);
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free(s_slots[i].block_buf);
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s_slots[i].block_buf = NULL;
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free(s_slots[i].transactions);
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s_slots[i].transactions = NULL;
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spi_bus_free((spi_host_device_t) i);
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s_slots[i].handle = NULL;
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}
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2018-12-28 18:04:37 +00:00
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if (s_slots[i].semphr_int) {
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vSemaphoreDelete(s_slots[i].semphr_int);
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s_slots[i].semphr_int = NULL;
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}
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2018-07-04 23:01:03 +00:00
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}
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return ESP_OK;
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}
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esp_err_t sdspi_host_set_card_clk(int slot, uint32_t freq_khz)
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{
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if (!is_valid_slot(slot)) {
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return ESP_ERR_INVALID_ARG;
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}
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if (!is_slot_initialized(slot)) {
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return ESP_ERR_INVALID_STATE;
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}
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ESP_LOGD(TAG, "Setting card clock to %d kHz", freq_khz);
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return init_spi_dev(slot, freq_khz * 1000);
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}
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2018-12-28 18:04:37 +00:00
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static void gpio_intr(void* arg)
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{
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BaseType_t awoken = pdFALSE;
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slot_info_t* slot = (slot_info_t*)arg;
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xSemaphoreGiveFromISR(slot->semphr_int, &awoken);
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gpio_intr_disable(slot->gpio_int);
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if (awoken) {
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portYIELD_FROM_ISR();
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}
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}
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2018-07-04 23:01:03 +00:00
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esp_err_t sdspi_host_init_slot(int slot, const sdspi_slot_config_t* slot_config)
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{
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ESP_LOGD(TAG, "%s: SPI%d miso=%d mosi=%d sck=%d cs=%d cd=%d wp=%d, dma_ch=%d",
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__func__, slot + 1,
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slot_config->gpio_miso, slot_config->gpio_mosi,
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slot_config->gpio_sck, slot_config->gpio_cs,
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slot_config->gpio_cd, slot_config->gpio_wp,
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slot_config->dma_channel);
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spi_host_device_t host = (spi_host_device_t) slot;
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if (!is_valid_slot(slot)) {
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return ESP_ERR_INVALID_ARG;
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}
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spi_bus_config_t buscfg = {
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.miso_io_num = slot_config->gpio_miso,
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.mosi_io_num = slot_config->gpio_mosi,
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.sclk_io_num = slot_config->gpio_sck,
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2018-12-28 18:04:37 +00:00
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.quadwp_io_num = GPIO_NUM_NC,
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.quadhd_io_num = GPIO_NUM_NC
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2018-07-04 23:01:03 +00:00
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};
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// Initialize SPI bus
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esp_err_t ret = spi_bus_initialize((spi_host_device_t)slot, &buscfg,
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slot_config->dma_channel);
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if (ret != ESP_OK) {
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ESP_LOGD(TAG, "spi_bus_initialize failed with rc=0x%x", ret);
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return ret;
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}
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// Attach the SD card to the SPI bus
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ret = init_spi_dev(slot, SDMMC_FREQ_PROBING * 1000);
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if (ret != ESP_OK) {
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ESP_LOGD(TAG, "spi_bus_add_device failed with rc=0x%x", ret);
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2018-12-28 18:04:37 +00:00
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goto cleanup;
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2018-07-04 23:01:03 +00:00
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}
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// Configure CS pin
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s_slots[slot].gpio_cs = (uint8_t) slot_config->gpio_cs;
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gpio_config_t io_conf = {
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.intr_type = GPIO_PIN_INTR_DISABLE,
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.mode = GPIO_MODE_OUTPUT,
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2019-11-18 12:42:22 +00:00
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.pin_bit_mask = 1ULL << slot_config->gpio_cs,
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2018-07-04 23:01:03 +00:00
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};
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ret = gpio_config(&io_conf);
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if (ret != ESP_OK) {
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ESP_LOGD(TAG, "gpio_config (CS) failed with rc=0x%x", ret);
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2018-12-28 18:04:37 +00:00
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goto cleanup;
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2018-07-04 23:01:03 +00:00
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}
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cs_high(slot);
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// Configure CD and WP pins
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io_conf = (gpio_config_t) {
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.intr_type = GPIO_PIN_INTR_DISABLE,
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.mode = GPIO_MODE_INPUT,
|
|
|
|
.pin_bit_mask = 0,
|
|
|
|
.pull_up_en = true
|
|
|
|
};
|
|
|
|
if (slot_config->gpio_cd != SDSPI_SLOT_NO_CD) {
|
2019-11-18 12:42:22 +00:00
|
|
|
io_conf.pin_bit_mask |= (1ULL << slot_config->gpio_cd);
|
2018-07-04 23:01:03 +00:00
|
|
|
s_slots[slot].gpio_cd = slot_config->gpio_cd;
|
|
|
|
} else {
|
|
|
|
s_slots[slot].gpio_cd = GPIO_UNUSED;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (slot_config->gpio_wp != SDSPI_SLOT_NO_WP) {
|
2019-11-18 12:42:22 +00:00
|
|
|
io_conf.pin_bit_mask |= (1ULL << slot_config->gpio_wp);
|
2018-07-04 23:01:03 +00:00
|
|
|
s_slots[slot].gpio_wp = slot_config->gpio_wp;
|
|
|
|
} else {
|
|
|
|
s_slots[slot].gpio_wp = GPIO_UNUSED;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (io_conf.pin_bit_mask != 0) {
|
|
|
|
ret = gpio_config(&io_conf);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
ESP_LOGD(TAG, "gpio_config (CD/WP) failed with rc=0x%x", ret);
|
2018-12-28 18:04:37 +00:00
|
|
|
goto cleanup;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (slot_config->gpio_int != SDSPI_SLOT_NO_INT) {
|
|
|
|
s_slots[slot].gpio_int = slot_config->gpio_int;
|
|
|
|
io_conf = (gpio_config_t) {
|
|
|
|
.intr_type = GPIO_INTR_LOW_LEVEL,
|
|
|
|
.mode = GPIO_MODE_INPUT,
|
|
|
|
.pull_up_en = true,
|
2019-11-18 12:42:22 +00:00
|
|
|
.pin_bit_mask = (1ULL << slot_config->gpio_int),
|
2018-12-28 18:04:37 +00:00
|
|
|
};
|
|
|
|
ret = gpio_config(&io_conf);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
ESP_LOGE(TAG, "gpio_config (interrupt) failed with rc=0x%x", ret);
|
|
|
|
goto cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
gpio_intr_disable(slot_config->gpio_int);
|
|
|
|
|
|
|
|
s_slots[slot].semphr_int = xSemaphoreCreateBinary();
|
|
|
|
if (s_slots[slot].semphr_int == NULL) {
|
|
|
|
ret = ESP_ERR_NO_MEM;
|
|
|
|
goto cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
// 1. the interrupt is better to be disabled before the ISR is registered
|
|
|
|
// 2. the semaphore MUST be initialized before the ISR is registered
|
|
|
|
// 3. the gpio_int member should be filled before the ISR is registered
|
|
|
|
ret = gpio_isr_handler_add(slot_config->gpio_int, &gpio_intr, &s_slots[slot]);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
ESP_LOGE(TAG, "gpio_isr_handle_add failed with rc=0x%x", ret);
|
|
|
|
goto cleanup;
|
2018-07-04 23:01:03 +00:00
|
|
|
}
|
2018-12-28 18:04:37 +00:00
|
|
|
} else {
|
|
|
|
s_slots[slot].gpio_int = GPIO_UNUSED;
|
2018-07-04 23:01:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
s_slots[slot].transactions = calloc(SDSPI_TRANSACTION_COUNT, sizeof(spi_transaction_t));
|
|
|
|
if (s_slots[slot].transactions == NULL) {
|
2018-12-28 18:04:37 +00:00
|
|
|
ret = ESP_ERR_NO_MEM;
|
|
|
|
goto cleanup;
|
2018-07-04 23:01:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return ESP_OK;
|
2018-12-28 18:04:37 +00:00
|
|
|
cleanup:
|
|
|
|
if (s_slots[slot].semphr_int) {
|
|
|
|
vSemaphoreDelete(s_slots[slot].semphr_int);
|
|
|
|
s_slots[slot].semphr_int = NULL;
|
|
|
|
}
|
|
|
|
if (s_slots[slot].handle) {
|
|
|
|
spi_bus_remove_device(spi_handle(slot));
|
|
|
|
s_slots[slot].handle = NULL;
|
|
|
|
}
|
|
|
|
spi_bus_free(host);
|
|
|
|
return ret;
|
2018-07-04 23:01:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
esp_err_t sdspi_host_start_command(int slot, sdspi_hw_cmd_t *cmd, void *data,
|
|
|
|
uint32_t data_size, int flags)
|
|
|
|
{
|
|
|
|
if (!is_valid_slot(slot)) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
if (!is_slot_initialized(slot)) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
if (card_missing(slot)) {
|
|
|
|
return ESP_ERR_NOT_FOUND;
|
|
|
|
}
|
|
|
|
// save some parts of cmd, as its contents will be overwritten
|
|
|
|
int cmd_index = cmd->cmd_index;
|
|
|
|
uint32_t cmd_arg;
|
|
|
|
memcpy(&cmd_arg, cmd->arguments, sizeof(cmd_arg));
|
|
|
|
cmd_arg = __builtin_bswap32(cmd_arg);
|
|
|
|
ESP_LOGV(TAG, "%s: slot=%i, CMD%d, arg=0x%08x flags=0x%x, data=%p, data_size=%i crc=0x%02x",
|
|
|
|
__func__, slot, cmd_index, cmd_arg, flags, data, data_size, cmd->crc7);
|
|
|
|
|
|
|
|
|
|
|
|
// For CMD0, clock out 80 cycles to help the card enter idle state,
|
|
|
|
// *before* CS is asserted.
|
|
|
|
if (cmd_index == MMC_GO_IDLE_STATE) {
|
|
|
|
go_idle_clockout(slot);
|
|
|
|
}
|
|
|
|
// actual transaction
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
cs_low(slot);
|
|
|
|
if (flags & SDSPI_CMD_FLAG_DATA) {
|
2018-12-28 18:04:37 +00:00
|
|
|
const bool multi_block = flags & SDSPI_CMD_FLAG_MULTI_BLK;
|
|
|
|
//send stop transmission token only when multi-block write and non-SDIO mode
|
|
|
|
const bool stop_transmission = multi_block && !(flags & SDSPI_CMD_FLAG_RSP_R5);
|
2018-07-04 23:01:03 +00:00
|
|
|
if (flags & SDSPI_CMD_FLAG_WRITE) {
|
2018-12-28 18:04:37 +00:00
|
|
|
ret = start_command_write_blocks(slot, cmd, data, data_size, multi_block, stop_transmission);
|
2018-07-04 23:01:03 +00:00
|
|
|
} else {
|
2018-12-28 18:04:37 +00:00
|
|
|
ret = start_command_read_blocks(slot, cmd, data, data_size, stop_transmission);
|
2018-07-04 23:01:03 +00:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = start_command_default(slot, flags, cmd);
|
|
|
|
}
|
|
|
|
cs_high(slot);
|
|
|
|
|
|
|
|
release_bus(slot);
|
|
|
|
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
ESP_LOGD(TAG, "%s: cmd=%d error=0x%x", __func__, cmd_index, ret);
|
|
|
|
} else {
|
|
|
|
// Update internal state when some commands are sent successfully
|
|
|
|
if (cmd_index == SD_CRC_ON_OFF) {
|
|
|
|
s_slots[slot].data_crc_enabled = (uint8_t) cmd_arg;
|
|
|
|
ESP_LOGD(TAG, "data CRC set=%d", s_slots[slot].data_crc_enabled);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t start_command_default(int slot, int flags, sdspi_hw_cmd_t *cmd)
|
|
|
|
{
|
|
|
|
size_t cmd_size = SDSPI_CMD_R1_SIZE;
|
|
|
|
if ((flags & SDSPI_CMD_FLAG_RSP_R1) ||
|
|
|
|
(flags & SDSPI_CMD_FLAG_NORSP)) {
|
|
|
|
cmd_size = SDSPI_CMD_R1_SIZE;
|
|
|
|
} else if (flags & SDSPI_CMD_FLAG_RSP_R2) {
|
|
|
|
cmd_size = SDSPI_CMD_R2_SIZE;
|
|
|
|
} else if (flags & SDSPI_CMD_FLAG_RSP_R3) {
|
|
|
|
cmd_size = SDSPI_CMD_R3_SIZE;
|
2018-12-28 18:04:37 +00:00
|
|
|
} else if (flags & SDSPI_CMD_FLAG_RSP_R4) {
|
|
|
|
cmd_size = SDSPI_CMD_R4_SIZE;
|
|
|
|
} else if (flags & SDSPI_CMD_FLAG_RSP_R5) {
|
|
|
|
cmd_size = SDSPI_CMD_R5_SIZE;
|
2018-07-04 23:01:03 +00:00
|
|
|
} else if (flags & SDSPI_CMD_FLAG_RSP_R7) {
|
|
|
|
cmd_size = SDSPI_CMD_R7_SIZE;
|
|
|
|
}
|
2018-12-28 18:04:37 +00:00
|
|
|
//add extra clocks to avoid polling
|
|
|
|
cmd_size += (SDSPI_NCR_MAX_SIZE-SDSPI_NCR_MIN_SIZE);
|
2018-07-04 23:01:03 +00:00
|
|
|
spi_transaction_t t = {
|
|
|
|
.flags = 0,
|
|
|
|
.length = cmd_size * 8,
|
|
|
|
.tx_buffer = cmd,
|
2018-12-28 18:04:37 +00:00
|
|
|
.rx_buffer = cmd,
|
2018-07-04 23:01:03 +00:00
|
|
|
};
|
|
|
|
esp_err_t ret = spi_device_transmit(spi_handle(slot), &t);
|
|
|
|
if (cmd->cmd_index == MMC_STOP_TRANSMISSION) {
|
|
|
|
/* response is a stuff byte from previous transfer, ignore it */
|
|
|
|
cmd->r1 = 0xff;
|
|
|
|
}
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
ESP_LOGD(TAG, "%s: spi_device_transmit returned 0x%x", __func__, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (flags & SDSPI_CMD_FLAG_NORSP) {
|
|
|
|
/* no (correct) response expected from the card, so skip polling loop */
|
|
|
|
ESP_LOGV(TAG, "%s: ignoring response byte", __func__);
|
|
|
|
cmd->r1 = 0x00;
|
|
|
|
}
|
2018-12-28 18:04:37 +00:00
|
|
|
// we have sent and received bytes with enough length.
|
|
|
|
// now shift the response to match the offset of sdspi_hw_cmd_t
|
|
|
|
ret = shift_cmd_response(cmd, cmd_size);
|
|
|
|
if (ret != ESP_OK) return ESP_ERR_TIMEOUT;
|
|
|
|
|
2018-07-04 23:01:03 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Wait until MISO goes high
|
|
|
|
static esp_err_t poll_busy(int slot, spi_transaction_t* t, int timeout_ms)
|
|
|
|
{
|
|
|
|
uint8_t t_rx;
|
|
|
|
*t = (spi_transaction_t) {
|
|
|
|
.tx_buffer = &t_rx,
|
|
|
|
.flags = SPI_TRANS_USE_RXDATA, //data stored in rx_data
|
|
|
|
.length = 8,
|
|
|
|
};
|
|
|
|
esp_err_t ret;
|
|
|
|
|
|
|
|
uint64_t t_end = esp_timer_get_time() + timeout_ms * 1000;
|
|
|
|
int nonzero_count = 0;
|
|
|
|
do {
|
|
|
|
t_rx = SDSPI_MOSI_IDLE_VAL;
|
|
|
|
t->rx_data[0] = 0;
|
|
|
|
ret = spi_device_transmit(spi_handle(slot), t);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (t->rx_data[0] != 0) {
|
|
|
|
if (++nonzero_count == 2) {
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} while(esp_timer_get_time() < t_end);
|
|
|
|
ESP_LOGD(TAG, "%s: timeout", __func__);
|
|
|
|
return ESP_ERR_TIMEOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Wait for data token, reading 8 bytes at a time.
|
|
|
|
// If the token is found, write all subsequent bytes to extra_ptr,
|
|
|
|
// and store the number of bytes written to extra_size.
|
|
|
|
static esp_err_t poll_data_token(int slot, spi_transaction_t* t,
|
|
|
|
uint8_t* extra_ptr, size_t* extra_size, int timeout_ms)
|
|
|
|
{
|
|
|
|
uint8_t t_rx[8];
|
|
|
|
*t = (spi_transaction_t) {
|
|
|
|
.tx_buffer = &t_rx,
|
|
|
|
.rx_buffer = &t_rx,
|
|
|
|
.length = sizeof(t_rx) * 8,
|
|
|
|
};
|
|
|
|
esp_err_t ret;
|
|
|
|
uint64_t t_end = esp_timer_get_time() + timeout_ms * 1000;
|
|
|
|
do {
|
|
|
|
memset(t_rx, SDSPI_MOSI_IDLE_VAL, sizeof(t_rx));
|
|
|
|
ret = spi_device_transmit(spi_handle(slot), t);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
bool found = false;
|
|
|
|
for (int byte_idx = 0; byte_idx < sizeof(t_rx); byte_idx++) {
|
|
|
|
uint8_t rd_data = t_rx[byte_idx];
|
|
|
|
if (rd_data == TOKEN_BLOCK_START) {
|
|
|
|
found = true;
|
|
|
|
memcpy(extra_ptr, t_rx + byte_idx + 1, sizeof(t_rx) - byte_idx - 1);
|
|
|
|
*extra_size = sizeof(t_rx) - byte_idx - 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (rd_data != 0xff && rd_data != 0) {
|
|
|
|
ESP_LOGD(TAG, "%s: received 0x%02x while waiting for data",
|
|
|
|
__func__, rd_data);
|
|
|
|
return ESP_ERR_INVALID_RESPONSE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (found) {
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
} while (esp_timer_get_time() < t_end);
|
|
|
|
ESP_LOGD(TAG, "%s: timeout", __func__);
|
|
|
|
return ESP_ERR_TIMEOUT;
|
|
|
|
}
|
|
|
|
|
2018-12-28 18:04:37 +00:00
|
|
|
// the r1 respond could appear 1-8 clocks after the command token is sent
|
|
|
|
// this function search for r1 in the buffer after 1 clocks to max 8 clocks
|
|
|
|
// then shift the data after R1, to match the definition of sdspi_hw_cmd_t.
|
|
|
|
static esp_err_t shift_cmd_response(sdspi_hw_cmd_t* cmd, int sent_bytes)
|
2018-07-04 23:01:03 +00:00
|
|
|
{
|
2018-12-28 18:04:37 +00:00
|
|
|
uint8_t* pr1 = &cmd->r1;
|
|
|
|
int ncr_cnt = 1;
|
|
|
|
while(true) {
|
|
|
|
if ((*pr1 & SD_SPI_R1_NO_RESPONSE) == 0) break;
|
|
|
|
pr1++;
|
|
|
|
if (++ncr_cnt > 8) return ESP_ERR_NOT_FOUND;
|
2018-07-04 23:01:03 +00:00
|
|
|
}
|
2018-12-28 18:04:37 +00:00
|
|
|
|
|
|
|
int copy_bytes = sent_bytes - SDSPI_CMD_SIZE - ncr_cnt;
|
|
|
|
if (copy_bytes > 0) {
|
|
|
|
memcpy(&cmd->r1, pr1, copy_bytes);
|
2018-07-04 23:01:03 +00:00
|
|
|
}
|
2018-12-28 18:04:37 +00:00
|
|
|
|
2018-07-04 23:01:03 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Receiving one or more blocks of data happens as follows:
|
|
|
|
* 1. send command + receive r1 response (SDSPI_CMD_R1_SIZE bytes total)
|
|
|
|
* 2. keep receiving bytes until TOKEN_BLOCK_START is encountered (this may
|
|
|
|
* take a while, depending on card's read speed)
|
|
|
|
* 3. receive up to SDSPI_MAX_DATA_LEN = 512 bytes of actual data
|
|
|
|
* 4. receive 2 bytes of CRC
|
|
|
|
* 5. for multi block transfers, go to step 2
|
|
|
|
*
|
|
|
|
* These steps can be done separately, but that leads to a less than optimal
|
|
|
|
* performance on large transfers because of delays between each step.
|
|
|
|
* For example, if steps 3 and 4 are separate SPI transactions queued one after
|
|
|
|
* another, there will be ~16 microseconds of dead time between end of step 3
|
|
|
|
* and the beginning of step 4. A delay between two blocking SPI transactions
|
|
|
|
* in step 2 is even higher (~60 microseconds).
|
|
|
|
*
|
|
|
|
* To improve read performance the following sequence is adopted:
|
|
|
|
* 1. Do the first transfer: command + r1 response + 8 extra bytes.
|
|
|
|
* Set pre_scan_data_ptr to point to the 8 extra bytes, and set
|
|
|
|
* pre_scan_data_size to 8.
|
|
|
|
* 2. Search pre_scan_data_size bytes for TOKEN_BLOCK_START.
|
|
|
|
* If found, the rest of the bytes contain part of the actual data.
|
|
|
|
* Store pointer to and size of that extra data as extra_data_{ptr,size}.
|
|
|
|
* If not found, fall back to polling for TOKEN_BLOCK_START, 8 bytes at a
|
|
|
|
* time (in poll_data_token function). Deal with extra data in the same way,
|
|
|
|
* by setting extra_data_{ptr,size}.
|
|
|
|
* 3. Receive the remaining 512 - extra_data_size bytes, plus 4 extra bytes
|
|
|
|
* (i.e. 516 - extra_data_size). Of the 4 extra bytes, first two will capture
|
|
|
|
* the CRC value, and the other two will capture 0xff 0xfe sequence
|
|
|
|
* indicating the start of the next block. Actual scanning is done by
|
|
|
|
* setting pre_scan_data_ptr to point to these last 2 bytes, and setting
|
|
|
|
* pre_scan_data_size = 2, then going to step 2 to receive the next block.
|
|
|
|
* When the final block is being received, the number of extra bytes is 2
|
|
|
|
* (only for CRC), because we don't need to wait for start token of the
|
|
|
|
* next block, and some cards are getting confused by these two extra bytes.
|
|
|
|
*
|
|
|
|
* With this approach the delay between blocks of a multi-block transfer is
|
|
|
|
* ~95 microseconds, out of which 35 microseconds are spend doing the CRC check.
|
|
|
|
* Further speedup is possible by pipelining transfers and CRC checks, at an
|
|
|
|
* expense of one extra temporary buffer.
|
|
|
|
*/
|
|
|
|
static esp_err_t start_command_read_blocks(int slot, sdspi_hw_cmd_t *cmd,
|
2018-12-28 18:04:37 +00:00
|
|
|
uint8_t *data, uint32_t rx_length, bool need_stop_command)
|
2018-07-04 23:01:03 +00:00
|
|
|
{
|
|
|
|
spi_transaction_t* t_command = get_transaction(slot);
|
|
|
|
*t_command = (spi_transaction_t) {
|
|
|
|
.length = (SDSPI_CMD_R1_SIZE + SDSPI_RESPONSE_MAX_DELAY) * 8,
|
|
|
|
.tx_buffer = cmd,
|
|
|
|
.rx_buffer = cmd,
|
|
|
|
};
|
|
|
|
esp_err_t ret = spi_device_transmit(spi_handle(slot), t_command);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
release_transaction(slot);
|
|
|
|
|
|
|
|
uint8_t* cmd_u8 = (uint8_t*) cmd;
|
|
|
|
size_t pre_scan_data_size = SDSPI_RESPONSE_MAX_DELAY;
|
|
|
|
uint8_t* pre_scan_data_ptr = cmd_u8 + SDSPI_CMD_R1_SIZE;
|
|
|
|
|
|
|
|
/* R1 response is delayed by 1-8 bytes from the request.
|
|
|
|
* This loop searches for the response and writes it to cmd->r1.
|
|
|
|
*/
|
|
|
|
while ((cmd->r1 & SD_SPI_R1_NO_RESPONSE) != 0 && pre_scan_data_size > 0) {
|
|
|
|
cmd->r1 = *pre_scan_data_ptr;
|
|
|
|
++pre_scan_data_ptr;
|
|
|
|
--pre_scan_data_size;
|
|
|
|
}
|
|
|
|
if (cmd->r1 & SD_SPI_R1_NO_RESPONSE) {
|
|
|
|
ESP_LOGD(TAG, "no response token found");
|
|
|
|
return ESP_ERR_TIMEOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (rx_length > 0) {
|
|
|
|
size_t extra_data_size = 0;
|
|
|
|
const uint8_t* extra_data_ptr = NULL;
|
|
|
|
bool need_poll = true;
|
|
|
|
|
|
|
|
for (int i = 0; i < pre_scan_data_size; ++i) {
|
|
|
|
if (pre_scan_data_ptr[i] == TOKEN_BLOCK_START) {
|
|
|
|
extra_data_size = pre_scan_data_size - i - 1;
|
|
|
|
extra_data_ptr = pre_scan_data_ptr + i + 1;
|
|
|
|
need_poll = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (need_poll) {
|
|
|
|
// Wait for data to be ready
|
|
|
|
spi_transaction_t* t_poll = get_transaction(slot);
|
|
|
|
ret = poll_data_token(slot, t_poll, cmd_u8 + SDSPI_CMD_R1_SIZE, &extra_data_size, cmd->timeout_ms);
|
|
|
|
release_transaction(slot);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (extra_data_size) {
|
|
|
|
extra_data_ptr = cmd_u8 + SDSPI_CMD_R1_SIZE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Arrange RX buffer
|
|
|
|
size_t will_receive = MIN(rx_length, SDSPI_MAX_DATA_LEN) - extra_data_size;
|
|
|
|
uint8_t* rx_data;
|
|
|
|
ret = get_block_buf(slot, &rx_data);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
// receive actual data
|
|
|
|
const size_t receive_extra_bytes = (rx_length > SDSPI_MAX_DATA_LEN) ? 4 : 2;
|
|
|
|
memset(rx_data, 0xff, will_receive + receive_extra_bytes);
|
|
|
|
spi_transaction_t* t_data = get_transaction(slot);
|
|
|
|
*t_data = (spi_transaction_t) {
|
|
|
|
.length = (will_receive + receive_extra_bytes) * 8,
|
|
|
|
.rx_buffer = rx_data,
|
|
|
|
.tx_buffer = rx_data
|
|
|
|
};
|
|
|
|
|
|
|
|
ret = spi_device_transmit(spi_handle(slot), t_data);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
release_transaction(slot);
|
|
|
|
|
|
|
|
// CRC bytes need to be received even if CRC is not enabled
|
|
|
|
uint16_t crc = UINT16_MAX;
|
|
|
|
memcpy(&crc, rx_data + will_receive, sizeof(crc));
|
|
|
|
|
|
|
|
// Bytes to scan for the start token
|
|
|
|
pre_scan_data_size = receive_extra_bytes - sizeof(crc);
|
|
|
|
pre_scan_data_ptr = rx_data + will_receive + sizeof(crc);
|
|
|
|
|
|
|
|
// Copy data to the destination buffer
|
|
|
|
memcpy(data + extra_data_size, rx_data, will_receive);
|
|
|
|
if (extra_data_size) {
|
|
|
|
memcpy(data, extra_data_ptr, extra_data_size);
|
|
|
|
}
|
|
|
|
|
|
|
|
// compute CRC of the received data
|
|
|
|
uint16_t crc_of_data = 0;
|
|
|
|
if (data_crc_enabled(slot)) {
|
|
|
|
crc_of_data = sdspi_crc16(data, will_receive + extra_data_size);
|
|
|
|
if (crc_of_data != crc) {
|
|
|
|
ESP_LOGE(TAG, "data CRC failed, got=0x%04x expected=0x%04x", crc_of_data, crc);
|
|
|
|
esp_log_buffer_hex(TAG, data, 16);
|
|
|
|
return ESP_ERR_INVALID_CRC;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
data += will_receive + extra_data_size;
|
|
|
|
rx_length -= will_receive + extra_data_size;
|
|
|
|
extra_data_size = 0;
|
|
|
|
extra_data_ptr = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (need_stop_command) {
|
|
|
|
// To end multi block transfer, send stop command and wait for the
|
|
|
|
// card to process it
|
|
|
|
sdspi_hw_cmd_t stop_cmd;
|
|
|
|
make_hw_cmd(MMC_STOP_TRANSMISSION, 0, cmd->timeout_ms, &stop_cmd);
|
|
|
|
ret = start_command_default(slot, SDSPI_CMD_FLAG_RSP_R1, &stop_cmd);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (stop_cmd.r1 != 0) {
|
|
|
|
ESP_LOGD(TAG, "%s: STOP_TRANSMISSION response 0x%02x", __func__, stop_cmd.r1);
|
|
|
|
}
|
|
|
|
spi_transaction_t* t_poll = get_transaction(slot);
|
|
|
|
ret = poll_busy(slot, t_poll, cmd->timeout_ms);
|
|
|
|
release_transaction(slot);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2018-12-28 18:04:37 +00:00
|
|
|
/* For CMD53, we can send in byte mode, or block mode
|
|
|
|
* The data start token is different, and cannot be determined by the length
|
|
|
|
* That's why we need ``multi_block``.
|
|
|
|
* It's also different that stop transmission token is not needed in the SDIO mode.
|
|
|
|
*/
|
2018-07-04 23:01:03 +00:00
|
|
|
static esp_err_t start_command_write_blocks(int slot, sdspi_hw_cmd_t *cmd,
|
2018-12-28 18:04:37 +00:00
|
|
|
const uint8_t *data, uint32_t tx_length, bool multi_block, bool stop_trans)
|
2018-07-04 23:01:03 +00:00
|
|
|
{
|
|
|
|
if (card_write_protected(slot)) {
|
|
|
|
ESP_LOGW(TAG, "%s: card write protected", __func__);
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
2018-12-28 18:04:37 +00:00
|
|
|
// Send the minimum length that is sure to get the complete response
|
|
|
|
// SD cards always return R1 (1bytes), SDIO returns R5 (2 bytes)
|
|
|
|
const int send_bytes = SDSPI_CMD_R5_SIZE+SDSPI_NCR_MAX_SIZE-SDSPI_NCR_MIN_SIZE;
|
|
|
|
|
2018-07-04 23:01:03 +00:00
|
|
|
spi_transaction_t* t_command = get_transaction(slot);
|
|
|
|
*t_command = (spi_transaction_t) {
|
2018-12-28 18:04:37 +00:00
|
|
|
.length = send_bytes * 8,
|
2018-07-04 23:01:03 +00:00
|
|
|
.tx_buffer = cmd,
|
|
|
|
.rx_buffer = cmd,
|
|
|
|
};
|
|
|
|
esp_err_t ret = spi_device_queue_trans(spi_handle(slot), t_command, 0);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
wait_for_transactions(slot);
|
|
|
|
|
2018-12-28 18:04:37 +00:00
|
|
|
// check if command response valid
|
|
|
|
ret = shift_cmd_response(cmd, send_bytes);
|
2018-07-04 23:01:03 +00:00
|
|
|
if (ret != ESP_OK) {
|
2018-12-28 18:04:37 +00:00
|
|
|
ESP_LOGD(TAG, "%s: check_cmd_response returned 0x%x", __func__, ret);
|
2018-07-04 23:01:03 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-12-28 18:04:37 +00:00
|
|
|
uint8_t start_token = multi_block ?
|
|
|
|
TOKEN_BLOCK_START_WRITE_MULTI : TOKEN_BLOCK_START;
|
2018-07-04 23:01:03 +00:00
|
|
|
|
|
|
|
while (tx_length > 0) {
|
|
|
|
// Write block start token
|
|
|
|
spi_transaction_t* t_start_token = get_transaction(slot);
|
|
|
|
*t_start_token = (spi_transaction_t) {
|
|
|
|
.length = sizeof(start_token) * 8,
|
|
|
|
.tx_buffer = &start_token
|
|
|
|
};
|
|
|
|
ret = spi_device_queue_trans(spi_handle(slot), t_start_token, 0);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Prepare data to be sent
|
|
|
|
size_t will_send = MIN(tx_length, SDSPI_MAX_DATA_LEN);
|
|
|
|
const uint8_t* tx_data = data;
|
|
|
|
if (!ptr_dma_compatible(tx_data)) {
|
|
|
|
// If the pointer can't be used with DMA, copy data into a new buffer
|
|
|
|
uint8_t* tmp;
|
|
|
|
ret = get_block_buf(slot, &tmp);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
memcpy(tmp, tx_data, will_send);
|
|
|
|
tx_data = tmp;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Write data
|
|
|
|
spi_transaction_t* t_data = get_transaction(slot);
|
|
|
|
*t_data = (spi_transaction_t) {
|
|
|
|
.length = will_send * 8,
|
|
|
|
.tx_buffer = tx_data,
|
|
|
|
};
|
|
|
|
ret = spi_device_queue_trans(spi_handle(slot), t_data, 0);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-12-28 18:04:37 +00:00
|
|
|
// Write CRC and get the response in one transaction
|
2018-07-04 23:01:03 +00:00
|
|
|
uint16_t crc = sdspi_crc16(data, will_send);
|
2018-12-28 18:04:37 +00:00
|
|
|
const int size_crc_response = sizeof(crc) + 1;
|
|
|
|
|
|
|
|
spi_transaction_t* t_crc_rsp = get_transaction(slot);
|
|
|
|
*t_crc_rsp = (spi_transaction_t) {
|
|
|
|
.length = size_crc_response * 8,
|
|
|
|
.flags = SPI_TRANS_USE_TXDATA|SPI_TRANS_USE_RXDATA,
|
2018-07-04 23:01:03 +00:00
|
|
|
};
|
2018-12-28 18:04:37 +00:00
|
|
|
memset(t_crc_rsp->tx_data, 0xff, 4);
|
|
|
|
memcpy(t_crc_rsp->tx_data, &crc, sizeof(crc));
|
|
|
|
|
|
|
|
ret = spi_device_queue_trans(spi_handle(slot), t_crc_rsp, 0);
|
2018-07-04 23:01:03 +00:00
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Wait for data to be sent
|
|
|
|
wait_for_transactions(slot);
|
|
|
|
|
2018-12-28 18:04:37 +00:00
|
|
|
uint8_t data_rsp = t_crc_rsp->rx_data[2];
|
|
|
|
if (!SD_SPI_DATA_RSP_VALID(data_rsp)) return ESP_ERR_INVALID_RESPONSE;
|
|
|
|
switch (SD_SPI_DATA_RSP(data_rsp)) {
|
|
|
|
case SD_SPI_DATA_ACCEPTED:
|
|
|
|
break;
|
|
|
|
case SD_SPI_DATA_CRC_ERROR:
|
|
|
|
return ESP_ERR_INVALID_CRC;
|
|
|
|
case SD_SPI_DATA_WR_ERROR:
|
|
|
|
return ESP_FAIL;
|
|
|
|
default:
|
|
|
|
return ESP_ERR_INVALID_RESPONSE;
|
2018-07-04 23:01:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Wait for the card to finish writing data
|
2018-12-28 18:04:37 +00:00
|
|
|
spi_transaction_t* t_poll = get_transaction(slot);
|
2018-07-04 23:01:03 +00:00
|
|
|
ret = poll_busy(slot, t_poll, cmd->timeout_ms);
|
|
|
|
release_transaction(slot);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
tx_length -= will_send;
|
|
|
|
data += will_send;
|
|
|
|
}
|
|
|
|
|
2018-12-28 18:04:37 +00:00
|
|
|
if (stop_trans) {
|
2018-07-04 23:01:03 +00:00
|
|
|
uint8_t stop_token[2] = {
|
2018-12-28 18:04:37 +00:00
|
|
|
TOKEN_BLOCK_STOP_WRITE_MULTI,
|
|
|
|
SDSPI_MOSI_IDLE_VAL
|
2018-07-04 23:01:03 +00:00
|
|
|
};
|
2018-12-28 18:04:37 +00:00
|
|
|
spi_transaction_t *t_stop_token = get_transaction(slot);
|
2018-07-04 23:01:03 +00:00
|
|
|
*t_stop_token = (spi_transaction_t) {
|
|
|
|
.length = sizeof(stop_token) * 8,
|
|
|
|
.tx_buffer = &stop_token,
|
|
|
|
};
|
|
|
|
ret = spi_device_queue_trans(spi_handle(slot), t_stop_token, 0);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
wait_for_transactions(slot);
|
|
|
|
|
2018-12-28 18:04:37 +00:00
|
|
|
spi_transaction_t *t_poll = get_transaction(slot);
|
2018-07-04 23:01:03 +00:00
|
|
|
ret = poll_busy(slot, t_poll, cmd->timeout_ms);
|
|
|
|
release_transaction(slot);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
2018-12-28 18:04:37 +00:00
|
|
|
|
|
|
|
esp_err_t sdspi_host_io_int_enable(int slot)
|
|
|
|
{
|
|
|
|
//the pin and its interrupt is already initialized, nothing to do here.
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
//the interrupt will give the semaphore and then disable itself
|
|
|
|
esp_err_t sdspi_host_io_int_wait(int slot, TickType_t timeout_ticks)
|
|
|
|
{
|
|
|
|
slot_info_t* pslot = &s_slots[slot];
|
|
|
|
//skip the interrupt and semaphore if the gpio is already low.
|
|
|
|
if (gpio_get_level(pslot->gpio_int)==0) return ESP_OK;
|
|
|
|
|
|
|
|
//clear the semaphore before wait
|
|
|
|
xSemaphoreTake(pslot->semphr_int, 0);
|
|
|
|
//enable the interrupt and wait for the semaphore
|
|
|
|
gpio_intr_enable(pslot->gpio_int);
|
|
|
|
BaseType_t ret = xSemaphoreTake(pslot->semphr_int, timeout_ticks);
|
|
|
|
if (ret == pdFALSE) {
|
|
|
|
gpio_intr_disable(pslot->gpio_int);
|
|
|
|
return ESP_ERR_TIMEOUT;
|
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|