2019-10-02 17:19:26 +00:00
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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2019-05-27 06:29:43 +00:00
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#include "bootloader_common.h"
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#include "sdkconfig.h"
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#include "soc/efuse_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/io_mux_reg.h"
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#include "esp32s2beta/rom/efuse.h"
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#include "esp32s2beta/rom/gpio.h"
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#include "esp32s2beta/rom/spi_flash.h"
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#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
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#define FLASH_CS_IO SPI_CS0_GPIO_NUM
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#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
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#define FLASH_SPID_IO SPI_D_GPIO_NUM
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#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
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#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
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void bootloader_configure_spi_pins(int drv)
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{
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
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gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
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gpio_matrix_out(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
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gpio_matrix_out(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPID_IO, SPID_IN_IDX, 0);
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gpio_matrix_out(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
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gpio_matrix_out(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
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//select pin function gpio
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIHD_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIWP_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICS0_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIQ_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPID_U, PIN_FUNC_GPIO);
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// flash clock signal should come from IO MUX.
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// set drive ability for clock
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICLK_U, FUNC_SPICLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICLK_U, FUN_DRV, drv, FUN_DRV_S);
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#if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64
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uint32_t flash_id = g_rom_flashchip.device_id;
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if (flash_id == FLASH_ID_GD25LQ32C) {
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// Set drive ability for 1.8v flash in 80Mhz.
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIHD_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIWP_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICS0_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICLK_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIQ_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPID_U, FUN_DRV, 3, FUN_DRV_S);
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}
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#endif
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}
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}
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