58 lines
1.9 KiB
C
58 lines
1.9 KiB
C
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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The cache has an interrupt that can be raised as soon as an access to a cached
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region (flash, psram) is done without the cache being enabled. We use that here
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to panic the CPU, which from a debugging perspective is better than grabbing bad
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data from the bus.
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*/
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#include "sdkconfig.h"
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include <esp_types.h>
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#include "esp_err.h"
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#include "esp_intr.h"
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#include "esp_attr.h"
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#include "driver/timer.h"
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#include "soc/dport_reg.h"
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#include "esp_int_wdt.h"
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void esp_cache_err_int_init() {
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ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
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intr_matrix_set(xPortGetCoreID(), ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
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//We do not register a handler for the interrupt because it is interrupt level 4 which
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//is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for
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//this interrupt.
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//These (undocumented) settings will enable the ETS_CACHE_IA_INTR_SOURCE behaviour for both PSRAM
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//as well as flash RAM.
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SET_PERI_REG_MASK(DPORT_PRO_DCACHE_DBUG0_REG, 0x3F<<DPORT_PRO_CPU_DISABLED_CACHE_IA_S);
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SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG, (0x3F<<22)|(0x3F<<8)|(0x3F<<14)|(0x3F<<0));
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ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
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}
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