2018-10-25 04:52:32 +00:00
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#pragma once
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2017-11-08 04:27:57 +00:00
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/* declare the performance here */
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2018-02-01 01:57:00 +00:00
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#define IDF_PERFORMANCE_MAX_HTTPS_REQUEST_BIN_SIZE 800
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2017-11-08 04:27:57 +00:00
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP 200
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2018-06-27 06:47:31 +00:00
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM 300
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2017-11-08 04:27:57 +00:00
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE 130
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#define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL 1000
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2018-02-07 07:45:10 +00:00
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 30
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2018-01-31 03:15:23 +00:00
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 27
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2018-01-31 03:15:23 +00:00
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
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2018-05-17 11:12:45 +00:00
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/* Due to code size & linker layout differences interacting with cache, VFS
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microbenchmark currently runs slower with PSRAM enabled. */
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2018-11-23 07:07:59 +00:00
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME 20000
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM 25000
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2018-01-07 12:28:09 +00:00
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// throughput performance by iperf
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#define IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT 50
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#define IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT 40
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#define IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT 80
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#define IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT 50
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2018-10-26 05:14:19 +00:00
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// events dispatched per second by event loop library
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2018-11-01 03:01:35 +00:00
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH 25000
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM 21000
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2019-03-11 07:24:32 +00:00
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// esp_sha() time to process 32KB of input data from RAM
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#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA1_32KB 5000
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#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA512_32KB 4500
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