275 lines
12 KiB
C
275 lines
12 KiB
C
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/*
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* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
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*
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* NOTE: The location and contents of this file are highly subject to change.
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*
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* Source for configuration-independent binaries (which link in a
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* configuration-specific HAL library) must NEVER include this file.
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* The HAL itself has historically included this file in some instances,
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* but this is not appropriate either, because the HAL is meant to be
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* core-specific but system independent.
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*/
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/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2000-2010 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef XTENSA_CONFIG_SYSTEM_H
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#define XTENSA_CONFIG_SYSTEM_H
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/*#include <xtensa/hal.h>*/
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/*----------------------------------------------------------------------
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CONFIGURED SOFTWARE OPTIONS
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----------------------------------------------------------------------*/
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#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
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#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
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#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */
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/* The above maps to one of the following constants: */
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#define XTHAL_ABI_WINDOWED 0
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#define XTHAL_ABI_CALL0 1
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/* Alternatives: */
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/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
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/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
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#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
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/* The above maps to one of the following constants: */
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#define XTHAL_CLIB_NEWLIB 0
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#define XTHAL_CLIB_UCLIBC 1
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#define XTHAL_CLIB_XCLIB 2
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/* Alternatives: */
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/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
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/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
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/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
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#define XSHAL_USE_FLOATING_POINT 1
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#define XSHAL_FLOATING_POINT_ABI 0
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/* SW workarounds enabled for HW errata: */
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/*----------------------------------------------------------------------
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DEVICE ADDRESSES
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----------------------------------------------------------------------*/
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/*
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* Strange place to find these, but the configuration GUI
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* allows moving these around to account for various core
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* configurations. Specific boards (and their BSP software)
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* will have specific meanings for these components.
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*/
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/* I/O Block areas: */
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#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
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#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
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#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
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#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
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#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
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#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
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/* System ROM: */
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#define XSHAL_ROM_VADDR 0x50000000
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#define XSHAL_ROM_PADDR 0x50000000
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#define XSHAL_ROM_SIZE 0x01000000
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/* Largest available area (free of vectors): */
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#define XSHAL_ROM_AVAIL_VADDR 0x50000000
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#define XSHAL_ROM_AVAIL_VSIZE 0x01000000
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/* System RAM: */
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#define XSHAL_RAM_VADDR 0x60000000
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#define XSHAL_RAM_PADDR 0x60000000
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#define XSHAL_RAM_VSIZE 0x20000000
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#define XSHAL_RAM_PSIZE 0x20000000
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#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
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/* Largest available area (free of vectors): */
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#define XSHAL_RAM_AVAIL_VADDR 0x60000000
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#define XSHAL_RAM_AVAIL_VSIZE 0x20000000
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/*
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* Shadow system RAM (same device as system RAM, at different address).
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* (Emulation boards need this for the SONIC Ethernet driver
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* when data caches are configured for writeback mode.)
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* NOTE: on full MMU configs, this points to the BYPASS virtual address
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* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
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* addresses are viewed through the BYPASS static map rather than
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* the CACHED static map.
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*/
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#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
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#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
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#define XSHAL_RAM_BYPASS_PSIZE 0x20000000
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/* Alternate system RAM (different device than system RAM): */
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/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
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/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
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/* Some available location in which to place devices in a simulation (eg. XTMP): */
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#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
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#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
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#define XSHAL_SIMIO_PADDR 0xC0000000
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#define XSHAL_SIMIO_SIZE 0x20000000
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/*----------------------------------------------------------------------
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* For use by reference testbench exit and diagnostic routines.
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*/
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#define XSHAL_MAGIC_EXIT 0x0
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/*----------------------------------------------------------------------
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* DEVICE-ADDRESS DEPENDENT...
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*
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* Values written to CACHEATTR special register (or its equivalent)
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* to enable and disable caches in various modes.
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*----------------------------------------------------------------------*/
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/*----------------------------------------------------------------------
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BACKWARD COMPATIBILITY ...
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----------------------------------------------------------------------*/
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/*
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* NOTE: the following two macros are DEPRECATED. Use the latter
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* board-specific macros instead, which are specially tuned for the
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* particular target environments' memory maps.
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*/
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#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
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#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
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/*----------------------------------------------------------------------
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GENERIC
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----------------------------------------------------------------------*/
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/* For the following, a 512MB region is used if it contains a system (PIF) RAM,
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* system (PIF) ROM, local memory, or XLMI. */
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/* These set any unused 512MB region to cache-BYPASS attribute: */
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#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22221112 /* enable caches in write-back mode */
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#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
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#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
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#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
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#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
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/* These set any unused 512MB region to ILLEGAL attribute: */
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#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF111F /* enable caches in write-back mode */
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#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
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#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
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#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
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#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
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/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
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* NULL-pointer dereference bugs; all other unused 512MB regions are set
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* to cache-BYPASS attribute: */
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#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */
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#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
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#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
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#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
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#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
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/*----------------------------------------------------------------------
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ISS (Instruction Set Simulator) SPECIFIC ...
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----------------------------------------------------------------------*/
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/* For now, ISS defaults to the TRAPNULL settings: */
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#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
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#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
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#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
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#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
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#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
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#define XSHAL_ISS_PIPE_REGIONS 0
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#define XSHAL_ISS_SDRAM_REGIONS 0
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/*----------------------------------------------------------------------
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XT2000 BOARD SPECIFIC ...
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----------------------------------------------------------------------*/
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/* For the following, a 512MB region is used if it contains any system RAM,
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* system ROM, local memory, XLMI, or other XT2000 board device or memory.
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* Regions containing devices are forced to cache-BYPASS mode regardless
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* of whether the macro is _WRITEBACK vs. _BYPASS etc. */
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/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
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#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22111F /* enable caches in write-back mode */
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#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
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#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
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#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
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#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
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#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
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#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
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/*----------------------------------------------------------------------
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VECTOR INFO AND SIZES
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----------------------------------------------------------------------*/
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#define XSHAL_VECTORS_PACKED 0
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#define XSHAL_STATIC_VECTOR_SELECT 1
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#define XSHAL_RESET_VECTOR_VADDR 0x40000400
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#define XSHAL_RESET_VECTOR_PADDR 0x40000400
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/*
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* Sizes allocated to vectors by the system (memory map) configuration.
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* These sizes are constrained by core configuration (eg. one vector's
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* code cannot overflow into another vector) but are dependent on the
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* system or board (or LSP) memory map configuration.
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*
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* Whether or not each vector happens to be in a system ROM is also
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* a system configuration matter, sometimes useful, included here also:
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*/
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#define XSHAL_RESET_VECTOR_SIZE 0x00000300
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#define XSHAL_RESET_VECTOR_ISROM 0
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#define XSHAL_USER_VECTOR_SIZE 0x00000038
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#define XSHAL_USER_VECTOR_ISROM 0
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#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
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#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
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#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
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#define XSHAL_KERNEL_VECTOR_ISROM 0
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#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
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#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
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#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
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#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
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#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
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#define XSHAL_WINDOW_VECTORS_ISROM 0
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#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
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#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
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#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
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#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
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#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
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#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
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#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
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#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
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#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
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#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
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#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
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#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
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#define XSHAL_NMI_VECTOR_SIZE 0x00000038
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#define XSHAL_NMI_VECTOR_ISROM 0
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#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
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#endif /*XTENSA_CONFIG_SYSTEM_H*/
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