257 lines
13 KiB
C
257 lines
13 KiB
C
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _DRIVER_RMT_CTRL_H_
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#define _DRIVER_RMT_CTRL_H_
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#include <stdbool.h>
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#include "soc/rmt_reg.h"
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#include "soc/dport_reg.h"
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#include "driver/gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define RMT_CHANNEL_MEMORY_CHAR_CNT (256)
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#define RMT_CHANNEL_MEMORY_WORD_CNT (RMT_CHANNEL_MEMORY_CHAR_CNT/4)
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#define RMT_DIV_CLK_KHZ (320)//Do not change this
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#define RMT_CHXCONF1(CHANNEL) ((RMT_CH0CONF1_REG)+((CHANNEL)*0X08))
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#define RMT_CHXCONF0(CHANNEL) ((RMT_CH0CONF0_REG)+((CHANNEL)*0X08))
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#define RMT_CHXSTATUS(CHANNEL) ((RMT_CH0STATUS_REG)+((CHANNEL)*0X04))
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#define RMT_CHXCARRIER_DUTY(CHANNEL) ((RMT_CH0CARRIER_DUTY_REG)+(CHANNEL)*0X04)
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#define RMT_CHXADDR_REG(CHANNEL) (RMT_CH0ADDR_REG+((CHANNEL)*0X04))
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#define RMT_CHXSTATUS_REG(CHANNEL) (RMT_CH0STATUS_REG+((CHANNEL)*0X04))
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#define RMT_CHX_MEMEOY(channel) (DR_REG_RMT_BASE+0X800+0X4*(channel*0x40))
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//Config0
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#define RMT_GET_REG_CARRIER_OUT_LV_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF0(CHANNEL),RMT_CARRIER_OUT_LV_CH0_V, RMT_CARRIER_OUT_LV_CH0_S)
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#define RMT_SET_REG_CARRIER_OUT_LV_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF0(CHANNEL),RMT_CARRIER_OUT_LV_CH0_V,(val),RMT_CARRIER_OUT_LV_CH0_S)
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#define RMT_GET_REG_CARRIER_EN_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF0(CHANNEL),RMT_CARRIER_EN_CH0_V, RMT_CARRIER_EN_CH0_S)
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#define RMT_SET_REG_CARRIER_EN_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF0(CHANNEL),RMT_CARRIER_EN_CH0_V,(val),RMT_CARRIER_EN_CH0_S)
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#define RMT_GET_REG_MEM_SIZE_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF0(CHANNEL),RMT_MEM_SIZE_CH0_V, RMT_MEM_SIZE_CH0_S)
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#define RMT_SET_REG_MEM_SIZE_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF0(CHANNEL),RMT_MEM_SIZE_CH0_V,(val),RMT_MEM_SIZE_CH0_S)
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#define RMT_GET_REG_IDLE_THRES_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF0(CHANNEL),RMT_IDLE_THRES_CH0_V, RMT_IDLE_THRES_CH0_S)
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#define RMT_SET_REG_IDLE_THRES_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF0(CHANNEL),RMT_IDLE_THRES_CH0_V,(val),RMT_IDLE_THRES_CH0_S)
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#define RMT_GET_REG_DIV_CNT_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF0(CHANNEL),RMT_DIV_CNT_CH0_V, RMT_DIV_CNT_CH0_S)
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#define RMT_SET_REG_DIV_CNT_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF0(CHANNEL),RMT_DIV_CNT_CH0_V,(val),RMT_DIV_CNT_CH0_S)
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//Config1
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#define RMT_GET_REG_IDLE_OUT_EN_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_IDLE_OUT_EN_CH0_V, RMT_IDLE_OUT_EN_CH0_S)
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#define RMT_SET_REG_IDLE_OUT_EN_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_IDLE_OUT_EN_CH0_V,(val),RMT_IDLE_OUT_EN_CH0_S)
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#define RMT_GET_REG_IDLE_OUT_LV_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_IDLE_OUT_LV_CH0_V, RMT_IDLE_OUT_LV_CH0_S)
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#define RMT_SET_REG_IDLE_OUT_LV_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_IDLE_OUT_LV_CH0_V,(val),RMT_IDLE_OUT_LV_CH0_S)
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#define RMT_GET_REG_REF_ALWAYS_ON_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_REF_ALWAYS_ON_CH0_V, RMT_REF_ALWAYS_ON_CH0_S)
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#define RMT_SET_REG_REF_ALWAYS_ON_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_REF_ALWAYS_ON_CH0_V,(val),RMT_REF_ALWAYS_ON_CH0_S)
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#define RMT_GET_REG_REF_CNT_RST_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_REF_CNT_RST_CH0_V, RMT_REF_CNT_RST_CH0_S)
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#define RMT_SET_REG_REF_CNT_RST_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_REF_CNT_RST_CH0_V,(val),RMT_REF_CNT_RST_CH0_S)
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#define RMT_GET_REG_RX_FILTER_THRES_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_RX_FILTER_THRES_CH0_V, RMT_RX_FILTER_THRES_CH0_S)
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#define RMT_SET_REG_RX_FILTER_THRES_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_RX_FILTER_THRES_CH0_V,(val),RMT_RX_FILTER_THRES_CH0_S)
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#define RMT_GET_REG_RX_FILTER_EN_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_RX_FILTER_EN_CH0_V, RMT_RX_FILTER_EN_CH0_S)
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#define RMT_SET_REG_RX_FILTER_EN_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_RX_FILTER_EN_CH0_V,(val),RMT_RX_FILTER_EN_CH0_S)
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#define RMT_GET_REG_TX_CONTI_MODE_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_TX_CONTI_MODE_CH0_V, RMT_TX_CONTI_MODE_CH0_S)
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#define RMT_SET_REG_TX_CONTI_MODE_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_TX_CONTI_MODE_CH0_V,(val),RMT_TX_CONTI_MODE_CH0_S)
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#define RMT_GET_REG_MEM_OWNER_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_MEM_OWNER_CH0_V, RMT_MEM_OWNER_CH0_S)
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#define RMT_SET_REG_MEM_OWNER_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_MEM_OWNER_CH0_V,(val),RMT_MEM_OWNER_CH0_S)
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#define RMT_GET_REG_APB_MEM_RST_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_APB_MEM_RST_CH0_V, RMT_APB_MEM_RST_CH0_S)
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#define RMT_SET_REG_APB_MEM_RST_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_APB_MEM_RST_CH0_V,(val),RMT_APB_MEM_RST_CH0_S)
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#define RMT_GET_REG_MEM_RD_RST_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL) , RMT_MEM_RD_RST_CH0_V, RMT_MEM_RD_RST_CH0_S)
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#define RMT_SET_REG_MEM_RD_RST_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_MEM_RD_RST_CH0_V,(val),RMT_MEM_RD_RST_CH0_S)
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#define RMT_GET_REG_MEM_WR_RST_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL) , RMT_MEM_WR_RST_CH0_V, RMT_MEM_WR_RST_CH0_S)
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#define RMT_SET_REG_MEM_WR_RST_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_MEM_WR_RST_CH0_V,(val),RMT_MEM_WR_RST_CH0_S)
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#define RMT_GET_REG_RX_EN_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL) , RMT_RX_EN_CH0_V, RMT_RX_EN_CH0_S)
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#define RMT_SET_REG_RX_EN_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_RX_EN_CH0_V,(val),RMT_RX_EN_CH0_S)
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#define RMT_GET_REG_TX_START_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL) , RMT_TX_START_CH0_V, RMT_TX_START_CH0_S)
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#define RMT_SET_REG_TX_START_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_TX_START_CH0_V,(val),RMT_TX_START_CH0_S)
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//Carrier
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#define RMT_GET_REG_CARRIER_HIGH_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCARRIER_DUTY(CHANNEL) , RMT_CARRIER_HIGH_CH0_V, RMT_CARRIER_HIGH_CH0_S)
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#define RMT_SET_REG_CARRIER_HIGH_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCARRIER_DUTY(CHANNEL) ,RMT_CARRIER_HIGH_CH0_V,(val),RMT_CARRIER_HIGH_CH0_S)
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#define RMT_GET_REG_CARRIER_LOW_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCARRIER_DUTY(CHANNEL) , RMT_CARRIER_LOW_CH0_V, RMT_CARRIER_LOW_CH0_S)
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#define RMT_SET_REG_CARRIER_LOW_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCARRIER_DUTY(CHANNEL) ,RMT_CARRIER_LOW_CH0_V,(val),RMT_CARRIER_LOW_CH0_S)
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#define RMT_GET_MEM_TX_WRAP_EN() GET_PERI_REG_BITS2(RMT_APB_CONF_REG , RMT_MEM_TX_WRAP_EN_V, RMT_MEM_TX_WRAP_EN_S)
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#define RMT_SET_MEM_TX_WRAP_EN(val) SET_PERI_REG_BITS(RMT_APB_CONF_REG ,RMT_MEM_TX_WRAP_EN_V,(val),RMT_MEM_TX_WRAP_EN_S)
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#define RMT_GET_APB_FIFO_MASK() GET_PERI_REG_BITS2(RMT_APB_CONF_REG , RMT_APB_FIFO_MASK_V, RMT_APB_FIFO_MASK_S)
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#define RMT_SET_APB_FIFO_MASK(val) SET_PERI_REG_BITS(RMT_APB_CONF_REG ,RMT_APB_FIFO_MASK_V,(val),RMT_APB_FIFO_MASK_S)
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enum rmt_channel{
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RMT_CTRL_CHANNEL0=0, /**< Rmt Channel0 */
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RMT_CTRL_CHANNEL1, /**< Rmt Channel1 */
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RMT_CTRL_CHANNEL2, /**< Rmt Channel2 */
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RMT_CTRL_CHANNEL3, /**< Rmt Channel3 */
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RMT_CTRL_CHANNEL4, /**< Rmt Channel4 */
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RMT_CTRL_CHANNEL5, /**< Rmt Channel5 */
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RMT_CTRL_CHANNEL6, /**< Rmt Channel6 */
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RMT_CTRL_CHANNEL7, /**< Rmt Channel7 */
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};
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enum rmt_ram_owner{
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RMT_RAM_OWNER_HARDWARE=0,/**< Rmt Rx mode ,Memory owner RMT_RAM_OWNER_HARDWARE */
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RMT_RAM_OWNER_SOFTWARE=1,/**< Rmt Rx mode ,Memory owner RMT_RAM_OWNER_SOFTWARE */
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};
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enum rmt_source_clk{
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RMT_BASECLK_REF=0,/**< Rmt Clk is Refclk defautl is 1MHz */
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RMT_BASECLK_APB,/**< Rmt Clk is APB CLK defautl is 80MHz */
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};
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enum rmt_ctrl_mode{
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RMT_TX_MODE=0,/**< Rmt TX Mode */
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RMT_RX_MODE, /**< Rmt RX Mode */
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};
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enum rmt_idle_level{
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RMT_IDLE_LOW_LEVEL=0,/**< Rmt TX IDLE Low Level */
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RMT_IDLE_HIGH_LEVEL, /**< Rmt TX IDLE High Level */
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};
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enum rmt_carrier_level{
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RMT_CARRIER_LOW_LEVEL=0,/**< Rmt Carrier Low Level */
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RMT_CARRIER_HIGH_LEVEL, /**< Rmt Carrier High Level */
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};
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typedef struct rmt_ctrl_tx{
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uint32_t carrier_fre_Hz; /**< Rmt Carrier Fre */
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uint8_t carrier_duty; /**< Rmt Carrier duty */
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enum rmt_idle_level idle_level; /**< Rmt Idle level */
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enum rmt_carrier_level carrier_level;/**< Rmt Carrier level */
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}rmt_ctrl_tx_config_t;
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typedef struct rmt_ctrl_rx{
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uint8_t filter_tick_cnt; /**< Rmt filter tick cnt */
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uint16_t rx_threshold_tick_cnt;/**< Rmt rx interrupt threshold */
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}rmt_ctrl_rx_config_t;
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typedef struct rmt_ctrl_config{
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enum rmt_ctrl_mode rmt_mode;
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enum rmt_channel channel;
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gpio_num_t gpio_num;
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uint8_t channel_mem_cnt;//NAME
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bool intr_enable;
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union{
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rmt_ctrl_tx_config_t tx_config;
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rmt_ctrl_rx_config_t rx_config;
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}mode_config;
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}rmt_ctrl_channel_config_t;
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typedef struct rmt_event_message{
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enum rmt_ctrl_mode mode;
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enum rmt_channel channel;
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}rmt_event_msg_t;
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typedef void (*rmt_event_callback)(rmt_event_msg_t rmt_message);
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/**
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* @brief register rmt interrupt occur callback function
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*
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* Use this Function,register interrupt event callback . when rmt interrupt is triggered , the event callback
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* will give appliacation .rmt_event_callback is called by rmt interrupt , so the rmt_event_callback
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* should be completed in a very short period of time. If you want to deal with a lot of things,Please Creat
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* a task ,and post message from the rmt_event_callback to the task.
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* @param[in] func : the func will be called,when rmt interrupt is triggered ,and the param of func is the
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* mode of rmt and channel of rmt
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*
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*
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* @return None
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*
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*/
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void rmt_register_event_callback(rmt_event_callback func);
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/**
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* @brief rmt common configuration
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*
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* User this Function,config rmt the channel tx mode or rx mode
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*
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* @param[in] rmt_config rmt_config.rmt_mode : select rmt tx mode or rx mode.
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* rmt_config.rmt_channel : current configuration channel.
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* rmt_config.gpio_num : tx or rx mode ,signagle use the gpio.
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* rmt_config.channel_mem_cnt : the tx or rx used the memory block cnt,every mem cnt have 256Byte contents
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* rmt_config.intr_enable : enable or disable tx or rx interrupt.when enable tx mode , send the tx memory end ,will trigger
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* tx event . when enable rx mode ,rx line idle time beyond rx_threshold_tick_cnt will trigger rx
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* event.
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* rmt_config.mode_config.tx_config : tx common config.
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* rmt_config.mode_config.rx_config : rx common config.
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*
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* @return None
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*
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*/
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void rmt_ctrl_init(rmt_ctrl_channel_config_t* rmt_config);
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/**
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* @brief write rmt tx memory
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*
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* When rmt tx memory content is 0x00,the tx will stop,and trigger tx intr event
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*
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* @param[in] channel : rmt tx channel
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* mem : write the mem to tx memory
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* cnt : the cnt max is rmt_config.channel_mem_cnt *32
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*
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* @return None
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*
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*/
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void rmt_ctrl_tx_wr_memory(enum rmt_channel channel,uint32_t* mem,uint16_t cnt);
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/**
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* @brief rmt rx start
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*
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* @param[in] channel : rmt rx channel
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*
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* @return None
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*
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*/
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void rmt_ctrl_rx_start(enum rmt_channel channel);
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/**
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* @brief rmt tx start
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*
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* @param[in] channel : rmt tx channel
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*
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* @return None
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*
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*/
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void rmt_ctrl_tx_start(enum rmt_channel channel);
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/**
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* @brief rmt read rx memory
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*
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* @param[in] channel : rmt rx channel
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*
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* @param[in] mem : the rx memory data copy to the mem,the mem content cnt = rmt_config.channel_mem_cnt *32
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*
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* @return rx memory number of received data
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*
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*/
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uint16_t rmt_ctrl_rx_rd_memory(enum rmt_channel channel,uint32_t* mem);
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/**
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* @brief register rmt interrupt handler
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*
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||
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* @param uint8_t ledc_intr_num : rmt interrupt num,check the info in soc.h, and please see the core-isa.h for more details
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* @param void (* fn)(void* ) : intr handler function
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* @param void * arg : parameter for handler
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*
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* @return null
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||
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*/
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void rmt_intr_handler_register(uint8_t rmt_intr_num,void (* fn)(void* ),void * arg);
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/**
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* @brief default rmt interrupt init function to initialize the rmt intrrupt parameters.
|
||
|
|
*
|
||
|
|
* @param uint8_t rmt_intr_num : ledc interrupt num,check the info in soc.h, and please see the core-isa.h for more details
|
||
|
|
*
|
||
|
|
* @return null
|
||
|
|
*/
|
||
|
|
|
||
|
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void rmt_intr_init_default(uint8_t rmt_intr_num);
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||
|
|
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||
|
|
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||
|
|
#ifdef __cplusplus
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||
|
|
}
|
||
|
|
#endif
|
||
|
|
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||
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#endif /* _DRIVER_RMT_CTRL_H_ */
|