57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#define MHZ (1000000)
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#define DPORT_CPUPERIOD_SEL_80 0
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#define DPORT_CPUPERIOD_SEL_160 1
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#define DPORT_CPUPERIOD_SEL_240 2
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#define DPORT_SOC_CLK_SEL_XTAL 0
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#define DPORT_SOC_CLK_SEL_PLL 1
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#define DPORT_SOC_CLK_SEL_8M 2
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#define DPORT_SOC_CLK_SEL_APLL 3
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#define RTC_FAST_CLK_FREQ_8M 8500000
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#ifdef __cplusplus
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extern "C" {
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#endif
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void rtc_clk_cpu_freq_to_xtal(int freq, int div);
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/* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
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* lower and upper 16-bit halves. These are the routines to work with such a
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* representation.
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*/
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static inline bool clk_val_is_valid(uint32_t val) {
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return (val & 0xffff) == ((val >> 16) & 0xffff) &&
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val != 0 &&
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val != UINT32_MAX;
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}
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static inline uint32_t reg_val_to_clk_val(uint32_t val) {
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return val & UINT16_MAX;
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}
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static inline uint32_t clk_val_to_reg_val(uint32_t val) {
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return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
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}
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#ifdef __cplusplus
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}
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#endif
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