310 lines
9.2 KiB
C
310 lines
9.2 KiB
C
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _DRIVER_LEDC_PWM_STRUCT_H_
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#define _DRIVER_LEDC_PWM_STRUCT_H_
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#include "soc/ledc_reg.h"
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#define ledc_reg_s ((ledc_reg*)(DR_REG_LEDC_BASE))
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typedef struct ledc_pwm_s {
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struct ledcH_channel_config{
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union {
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struct {
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unsigned int timer_sel_hsch0: 2;
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unsigned int sig_out_en_hsch0: 1;
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unsigned int idle_lv_hsch0: 1;
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unsigned int reserved4: 27;
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unsigned int clk_en: 1;
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} ;
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uint32_t val;
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} LEDC_HSCHX_CONF0;
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union {
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struct {
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unsigned int hpoint_hsch0: 20;
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unsigned int reserved20: 12;
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} ;
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uint32_t val;
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} LEDC_HSCHX_HPOINT;
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union {
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struct {
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unsigned int duty_hsch0: 25;
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unsigned int reserved25: 7;
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} ;
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uint32_t val;
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} LEDC_HSCHX_DUTY;
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union {
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struct {
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unsigned int duty_scale_hsch0: 10;
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unsigned int duty_cycle_hsch0: 10;
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unsigned int duty_num_hsch0: 10;
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unsigned int duty_inc_hsch0: 1;
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unsigned int duty_start_hsch0: 1;
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} ;
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uint32_t val;
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} LEDC_HSCHX_CONF1;
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union {
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struct {
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unsigned int duty_hsch0: 25;
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unsigned int reserved25: 7;
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} ;
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uint32_t val;
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} LEDC_HSCHX_DUTY_R;
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}ledch_channel_config[8];
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struct ledcL_channel_config{
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union {
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struct {
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unsigned int timer_sel_lsch0: 2;
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unsigned int sig_out_en_lsch0: 1;
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unsigned int idle_lv_lsch0: 1;
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unsigned int para_up_lsch0: 1;
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unsigned int reserved5: 27;
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} ;
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uint32_t val;
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} LEDC_LSCHX_CONF0;
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union {
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struct {
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unsigned int hpoint_lsch0: 20;
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unsigned int reserved20: 12;
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} ;
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uint32_t val;
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} LEDC_LSCHX_HPOINT;
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union {
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struct {
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unsigned int duty_lsch0: 25;
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unsigned int reserved25: 7;
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} ;
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uint32_t val;
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} LEDC_LSCHX_DUTY;
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union {
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struct {
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unsigned int duty_scale_lsch0: 10;
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unsigned int duty_cycle_lsch0: 10;
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unsigned int duty_num_lsch0: 10;
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unsigned int duty_inc_lsch0: 1;
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unsigned int duty_start_lsch0: 1;
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} ;
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uint32_t val;
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} LEDC_LSCHX_CONF1;
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union {
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struct {
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unsigned int duty_lsch0: 25;
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unsigned int reserved25: 7;
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} ;
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uint32_t val;
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} LEDC_LSCHX_DUTY_R;
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}ledcl_channel_config[8];
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struct ledcH_time_config{
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union {
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struct {
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unsigned int hstimer0_lim: 5;
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unsigned int div_num_hstimer0: 18;
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unsigned int hstimer0_pause: 1;
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unsigned int hstimer0_rst: 1;
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unsigned int tick_sel_hstimer0: 1;
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unsigned int reserved26: 6;
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} ;
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uint32_t val;
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} LEDC_HSTIMERX_CONF;
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union {
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struct {
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unsigned int hstimer0_cnt: 20;
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unsigned int reserved20: 12;
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} ;
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uint32_t val;
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} LEDC_HSTIMERX_VALUE;
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}ledch_time_config[4];
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struct ledcL_timer_config{
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union {
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struct {
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unsigned int lstimer0_lim: 5;
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unsigned int div_num_lstimer0: 18;
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unsigned int lstimer0_pause: 1;
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unsigned int lstimer0_rst: 1;
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unsigned int tick_sel_lstimer0: 1;
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unsigned int lstimer0_para_up: 1;
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unsigned int reserved27: 5;
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} ;
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uint32_t val;
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} LEDC_LSTIMERX_CONF;
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union {
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struct {
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unsigned int lstimer0_cnt: 20;
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unsigned int reserved20: 12;
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} ;
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uint32_t val;
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} LEDC_LSTIMERX_VALUE;
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}ledcl_time_config[4];
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union {
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struct {
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unsigned int hstimer0_ovf_int_raw: 1;
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unsigned int hstimer1_ovf_int_raw: 1;
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unsigned int hstimer2_ovf_int_raw: 1;
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unsigned int hstimer3_ovf_int_raw: 1;
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unsigned int lstimer0_ovf_int_raw: 1;
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unsigned int lstimer1_ovf_int_raw: 1;
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unsigned int lstimer2_ovf_int_raw: 1;
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unsigned int lstimer3_ovf_int_raw: 1;
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unsigned int duty_chng_end_hsch0_int_raw: 1;
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unsigned int duty_chng_end_hsch1_int_raw: 1;
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unsigned int duty_chng_end_hsch2_int_raw: 1;
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unsigned int duty_chng_end_hsch3_int_raw: 1;
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unsigned int duty_chng_end_hsch4_int_raw: 1;
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unsigned int duty_chng_end_hsch5_int_raw: 1;
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unsigned int duty_chng_end_hsch6_int_raw: 1;
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unsigned int duty_chng_end_hsch7_int_raw: 1;
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unsigned int duty_chng_end_lsch0_int_raw: 1;
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unsigned int duty_chng_end_lsch1_int_raw: 1;
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unsigned int duty_chng_end_lsch2_int_raw: 1;
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unsigned int duty_chng_end_lsch3_int_raw: 1;
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unsigned int duty_chng_end_lsch4_int_raw: 1;
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unsigned int duty_chng_end_lsch5_int_raw: 1;
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unsigned int duty_chng_end_lsch6_int_raw: 1;
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unsigned int duty_chng_end_lsch7_int_raw: 1;
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unsigned int reserved24: 8;
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} ;
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uint32_t val;
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} LEDC_INT_RAW;
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union {
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struct {
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unsigned int hstimer0_ovf_int_st: 1;
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unsigned int hstimer1_ovf_int_st: 1;
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unsigned int hstimer2_ovf_int_st: 1;
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unsigned int hstimer3_ovf_int_st: 1;
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unsigned int lstimer0_ovf_int_st: 1;
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unsigned int lstimer1_ovf_int_st: 1;
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unsigned int lstimer2_ovf_int_st: 1;
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unsigned int lstimer3_ovf_int_st: 1;
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unsigned int duty_chng_end_hsch0_int_st: 1;
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unsigned int duty_chng_end_hsch1_int_st: 1;
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unsigned int duty_chng_end_hsch2_int_st: 1;
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unsigned int duty_chng_end_hsch3_int_st: 1;
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unsigned int duty_chng_end_hsch4_int_st: 1;
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unsigned int duty_chng_end_hsch5_int_st: 1;
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unsigned int duty_chng_end_hsch6_int_st: 1;
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unsigned int duty_chng_end_hsch7_int_st: 1;
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unsigned int duty_chng_end_lsch0_int_st: 1;
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unsigned int duty_chng_end_lsch1_int_st: 1;
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unsigned int duty_chng_end_lsch2_int_st: 1;
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unsigned int duty_chng_end_lsch3_int_st: 1;
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unsigned int duty_chng_end_lsch4_int_st: 1;
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unsigned int duty_chng_end_lsch5_int_st: 1;
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unsigned int duty_chng_end_lsch6_int_st: 1;
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unsigned int duty_chng_end_lsch7_int_st: 1;
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unsigned int reserved24: 8;
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} ;
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uint32_t val;
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} LEDC_INT_ST;
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union {
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struct {
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unsigned int hstimer0_ovf_int_ena: 1;
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unsigned int hstimer1_ovf_int_ena: 1;
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unsigned int hstimer2_ovf_int_ena: 1;
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unsigned int hstimer3_ovf_int_ena: 1;
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unsigned int lstimer0_ovf_int_ena: 1;
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unsigned int lstimer1_ovf_int_ena: 1;
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unsigned int lstimer2_ovf_int_ena: 1;
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unsigned int lstimer3_ovf_int_ena: 1;
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unsigned int duty_chng_end_hsch0_int_ena: 1;
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unsigned int duty_chng_end_hsch1_int_ena: 1;
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unsigned int duty_chng_end_hsch2_int_ena: 1;
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unsigned int duty_chng_end_hsch3_int_ena: 1;
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unsigned int duty_chng_end_hsch4_int_ena: 1;
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unsigned int duty_chng_end_hsch5_int_ena: 1;
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unsigned int duty_chng_end_hsch6_int_ena: 1;
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unsigned int duty_chng_end_hsch7_int_ena: 1;
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unsigned int duty_chng_end_lsch0_int_ena: 1;
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unsigned int duty_chng_end_lsch1_int_ena: 1;
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unsigned int duty_chng_end_lsch2_int_ena: 1;
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unsigned int duty_chng_end_lsch3_int_ena: 1;
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unsigned int duty_chng_end_lsch4_int_ena: 1;
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unsigned int duty_chng_end_lsch5_int_ena: 1;
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unsigned int duty_chng_end_lsch6_int_ena: 1;
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unsigned int duty_chng_end_lsch7_int_ena: 1;
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unsigned int reserved24: 8;
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} ;
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uint32_t val;
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} LEDC_INT_ENA;
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union {
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struct {
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unsigned int hstimer0_ovf_int_clr: 1;
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unsigned int hstimer1_ovf_int_clr: 1;
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unsigned int hstimer2_ovf_int_clr: 1;
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unsigned int hstimer3_ovf_int_clr: 1;
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unsigned int lstimer0_ovf_int_clr: 1;
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unsigned int lstimer1_ovf_int_clr: 1;
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unsigned int lstimer2_ovf_int_clr: 1;
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unsigned int lstimer3_ovf_int_clr: 1;
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unsigned int duty_chng_end_hsch0_int_clr: 1;
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unsigned int duty_chng_end_hsch1_int_clr: 1;
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unsigned int duty_chng_end_hsch2_int_clr: 1;
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unsigned int duty_chng_end_hsch3_int_clr: 1;
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unsigned int duty_chng_end_hsch4_int_clr: 1;
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unsigned int duty_chng_end_hsch5_int_clr: 1;
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unsigned int duty_chng_end_hsch6_int_clr: 1;
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unsigned int duty_chng_end_hsch7_int_clr: 1;
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unsigned int duty_chng_end_lsch0_int_clr: 1;
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unsigned int duty_chng_end_lsch1_int_clr: 1;
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unsigned int duty_chng_end_lsch2_int_clr: 1;
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unsigned int duty_chng_end_lsch3_int_clr: 1;
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unsigned int duty_chng_end_lsch4_int_clr: 1;
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unsigned int duty_chng_end_lsch5_int_clr: 1;
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unsigned int duty_chng_end_lsch6_int_clr: 1;
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unsigned int duty_chng_end_lsch7_int_clr: 1;
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unsigned int reserved24: 8;
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} ;
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uint32_t val;
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} LEDC_INT_CLR;
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union {
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struct {
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unsigned int apb_clk_sel: 1;
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unsigned int reserved1: 31;
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} ;
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uint32_t val;
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} LEDC_CONF;
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uint32_t reserved_194;
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uint32_t reserved_198;
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uint32_t reserved_19c;
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uint32_t reserved_1a0;
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uint32_t reserved_1a4;
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uint32_t reserved_1a8;
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uint32_t reserved_1ac;
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uint32_t reserved_1b0;
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uint32_t reserved_1b4;
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uint32_t reserved_1b8;
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uint32_t reserved_1bc;
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uint32_t reserved_1c0;
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uint32_t reserved_1c4;
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uint32_t reserved_1c8;
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uint32_t reserved_1cc;
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uint32_t reserved_1d0;
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uint32_t reserved_1d4;
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uint32_t reserved_1d8;
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uint32_t reserved_1dc;
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uint32_t reserved_1e0;
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uint32_t reserved_1e4;
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uint32_t reserved_1e8;
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uint32_t reserved_1ec;
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uint32_t reserved_1f0;
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uint32_t reserved_1f4;
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uint32_t reserved_1f8;
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struct {
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uint32_t val;
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} LEDC_DATE1;
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}ledc_reg;
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#endif /* _DRIVER_LEDC_PWM_STRUCT_H_ */
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