86 lines
3.9 KiB
ReStructuredText
86 lines
3.9 KiB
ReStructuredText
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ESP SDIO slave protocol
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=======================
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The protocol is based on Function 1 access by CMD52 and CMD53, offering 3 services: (1) sending and receiving FIFO, (2) 52 8-bit R/W
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register shared by host and slave, (3) 8 general purpose interrupt sources from host to slave and 8 in the oppsite direction.
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The host should access the registers below as described to communicate with slave.
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Slave register table
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--------------------
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32-bit
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^^^^^^^
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- 0x044 (TOKEN_RDATA): in which bit 27-16 holds the receiving buffer number.
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- 0x058 (INT_ST): holds the interrupt source bits from slave to host.
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- 0x060 (PKT_LEN): holds the accumulated length (by byte) to be sent from slave to host.
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- 0x0D4 (INT_CLR): write 1 to clear interrupt bits corresponding to INT_ST.
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- 0x0DC (INT_ENA): mask bits for interrupts from slave to host.
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8-bit
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^^^^^
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Shared general purpose registers:
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- 0x06C-0x077: R/W registers 0-11 shared by slave and host.
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- 0x07A-0x07B: R/W registers 14-15 shared by slave and host.
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- 0x07E-0x07F: R/W registers 18-19 shared by slave and host.
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- 0x088-0x08B: R/W registers 24-27 shared by slave and host.
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- 0x09C-0x0BB: R/W registers 32-63 shared by slave and host.
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Interrupt Registers:
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- 0x08D (SLAVE_INT): bits for host to interrupt slave. auto clear.
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FIFO (sending and receiving)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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0x090 - 0x1F7FF are reserved for FIFOs.
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.. note:: This includes the CMD52 and CMD53 (block mode or byte mode).
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The function number should be set to 1, OP Code should be set to 1 (for CMD53).
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The slave will respond with the length according to the length field in CMD53 (1 of CMD52), with the data longer
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than *requested length* filled with 0 (sending) or discard (receiving).
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Interrupts
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----------
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For the host interrupts, the slave raise the interrupt by pulling DAT1 line down at a proper time (level sensitive).
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The host detect this and read the INT_ST register to see the source. Then the host can clear it by writing the INT_CLR
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register and do something with the interrupt. The host can also mask unneeded sources by clearing the bits in INT_ENA
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register corresponding to the sources. If all the sources are cleared (or masked), the DAT1 line goes inactive.
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``sdio_slave_hostint_t`` (:doc:`sdio_slave`) shows the bit definition corresponding to host interrupt sources.
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For the slave interrupts, the host send transfers to write the SLAVE_INT register. Once a bit is written from 0 to 1,
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the slave hardware and driver will detect it and inform the app.
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Receiving FIFO
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--------------
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To write the receiving FIFO in the slave, host should work in the following steps:
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1. Read the TOKEN1 field (bits 27-16) of TOKEN_RDATA (0x044) register. The buffer number remaining is TOKEN1 minus
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the number of buffers used by host.
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2. Make sure the buffer number is sufficient (*buffer_size* * *buffer_num* is greater than data to write, *buffer_size*
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is pre-defined between the host and the slave before the communication starts). Or go back to step 1 until the buffer
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is enough.
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3. Write to the FIFO address with CMD53. Note that the *requested length* should not be larger than calculated in step 2,
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and the FIFO address is related to *rquested length*.
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4. Calculate used buffers, note that non-full buffer at the tail should be seen as one that is used.
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Sending FIFO
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------------
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To read the sending FIFO in the slave, host should work in the following steps:
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1. Wait for the interrupt line to be active (optional, low by default).
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2. Read (poll) the interrupt bits in INT_ST register to see whether new packets exists.
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3. If new packets are ready, reads the PKT_LEN reg. The data length to read from slave is PKT_LEN minuses the length
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that has been read from the host. If the PKT_LEN is not larger than used, wait and poll until the slave is ready and
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update the PKT_LEN.
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4. Read from the FIFO with CMD53. Note that the *requested length* should not be larger than calculated in step3, and
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the FIFO address is related to *requested length*.
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5. Recored read length.
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